JP2011159690A - Semiconductor device, and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To bring a source-drain region composed of a silicon mixed crystal layer in an MIS transistor close to a channel region while preventing trouble due to diffusion of an impurity. <P>SOLUTION: A semiconductor device has gate electrodes 13 formed on an n-type active region including a semiconductor substrate 10 with gate insulating films 12 interposed, p-type source-drain regions 20 formed in regions of both sides of the gate electrodes 13 in the active region, and n-type pocket regions 18 formed from side faces of the respective p-type source-drain regions 20 in the active region toward below the gate electrodes 13 respectively. Each of the p-type source-drain regions 20 is composed of a mixed crystal layer of silicon and a group IV element, and the mixed crystal layer has a projection 20a which is formed by protruding the side face of the mixed crystal layer on a gate electrode side in a gate-length direction toward a gate electrode side. A tip of the projection 20a is covered with the pocket region 18. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a metal-insulator semiconductor field effect transistor (MISFET) including a silicon mixed crystal layer in a source / drain region and a manufacturing method thereof.

  In order to realize high performance of a semiconductor integrated circuit device, a distortion technique that improves the driving capability of a transistor by applying stress to the channel region of a MISFET (hereinafter referred to as MIS transistor) has come to be used. ing. In the p-type MIS transistor, it is known that the carrier mobility is improved by applying a compressive stress in the gate length direction of the channel region. As a method of applying compressive stress to the channel region, a method of forming a silicon germanium (SiGe) layer having a lattice constant larger than that of silicon (Si) used for a semiconductor substrate in a source / drain region (for example, (See Patent Document 1).

  FIG. 9 shows a conventional semiconductor device having a silicon mixed crystal layer made of SiGe in the source / drain region of a p-type MIS transistor.

  As shown in FIG. 9, a gate electrode 102 with a gate insulating film 101 interposed is formed on a semiconductor substrate 100 made of silicon. Offset sidewalls 103 made of an insulating film are formed on both side surfaces of the gate electrode 102, and a first sidewall 104 and a second sidewall 105 having an L-shaped cross section are formed outside the gate insulating film 101 including the gate insulating film 101. And are formed respectively.

  An n-type channel region in the semiconductor substrate 100, and below the first sidewall 104 and the second sidewall 105, respectively, covers a p-type extension region 106 and a lower portion of the p-type extension region 106. An n-type pocket region 107 is formed.

  A silicon mixed crystal layer 108 made of p-type SiGe is formed as a source / drain region outside the p-type extension region 106 and the n-type pocket region 107 in the semiconductor substrate 100.

JP 2006-186240 A

  In general, the compressive stress applied to the channel region by the silicon mixed crystal layer made of SiGe improves the driving capability of the p-type transistor. However, as the miniaturization of the transistor progresses, the area of the channel region becomes smaller, so that the silicon mixed crystal layer approaches the channel region. As a result, the threshold voltage Vt of the p-type transistor fluctuates due to the diffusion of the p-type impurity from the silicon mixed crystal layer, thereby degrading the driving capability of the transistor. Therefore, when a silicon mixed crystal layer is formed in the source / drain formation region of the p-type transistor, the silicon mixed crystal layer is brought closer to the channel region while taking into account the diffusion of p-type impurities from the silicon mixed crystal layer. There is a need.

  Therefore, as shown in FIG. 9, the source / drain region where the silicon mixed crystal layer is formed is formed outside the sidewall in consideration of the diffusion of impurities from the silicon mixed crystal layer. However, when the silicon mixed crystal layer is separated from the channel region, the compressive stress in the gate length direction cannot be effectively applied to the channel region.

  In other words, from the viewpoint of applying stress, the request to make the silicon mixed crystal layer as close as possible to the channel region has a problem that it cannot be sufficiently achieved because it is necessary to prevent problems caused by diffusion of impurities from the silicon mixed crystal layer. is there.

  In view of the above problems, an object of the present invention is to enable a source / drain region formed of a silicon mixed crystal layer in a MIS transistor to be close to a channel region while preventing problems due to impurity diffusion.

  In order to achieve the above object, according to the present invention, a semiconductor device is provided in a first conductivity type silicon mixed crystal layer, and a tip of a convex portion (Σ tip) protruding to the gate electrode side is a second conductivity type pocket. The structure is covered with the region.

  Specifically, a semiconductor device according to the present invention includes a gate electrode formed on a first conductivity type active region made of a semiconductor substrate with a gate insulating film interposed therebetween, and on both sides of the gate electrode in the active region. A source / drain region of the second conductivity type formed in the region, and a pocket region of the first conductivity type formed from the side surface of each source / drain region in the active region toward the lower side of the gate electrode. The region is composed of a mixed crystal layer of silicon and a group IV element, and the mixed crystal layer has a protruding portion whose side surface on the gate electrode side in the gate length direction protrudes to the gate electrode side, and the tip of the protruding portion is a pocket region. Covered by.

  According to the semiconductor device of the present invention, the source / drain region of the second conductivity type is composed of a mixed crystal layer of silicon and a group IV element, and the side surface of the mixed crystal layer on the gate electrode side in the gate length direction is the gate electrode. A convex portion protruding to the side is provided, and the tip of the convex portion is covered with a pocket region of the first conductivity type. For this reason, it is possible to prevent the impurities from the silicon mixed crystal layer from diffusing into the channel region, and to prevent fluctuations in the threshold voltage. In addition, since the silicon mixed crystal layer can be formed on the inner side of the sidewall, compressive stress can be effectively applied to the gate electrode side of the channel region.

  In the semiconductor device of the present invention, the tip position in the depth direction of the convex portion in the mixed crystal layer is preferably deeper than or equal to the peak position of the impurity concentration in the pocket region.

  The semiconductor device of the present invention further includes an extension region of a second conductivity type formed from the side surface of each source / drain region above the active region toward the lower side of the gate electrode, and the depth of the convex portion in the mixed crystal layer. The tip position in the vertical direction is preferably deeper than the maximum junction depth of the extension region and deeper than one half of the maximum junction depth of the pocket region.

  In addition, the semiconductor device of the present invention further includes sidewalls made of insulating films formed on both side surfaces of the gate electrode on the gate length direction side, and the position intersecting the upper surface of the active region in the mixed crystal layer is the sidewall. It is preferable to be formed inside the outermost surface on the outside.

  In the semiconductor device of the present invention, the tip position of the convex portion in the mixed crystal layer may be 18 nm or more and 23 nm or less from the surface of the active region.

  In the semiconductor device of the present invention, the group IV element constituting the mixed crystal layer is preferably germanium.

  In the semiconductor device of the present invention, the group IV element constituting the mixed crystal layer may be carbon.

  The semiconductor device according to the present invention is formed so as to cover the gate electrode and the mixed crystal layer including the metal silicide layer on the active region and the metal silicide layer formed on the gate electrode and the mixed crystal layer, respectively. And a liner insulating film.

  In the semiconductor device of the present invention, the pocket regions facing each other may be in contact with each other below the gate electrode.

  The method of manufacturing a semiconductor device according to the present invention includes a step (a) of forming a gate electrode on an active region of a first conductivity type made of a semiconductor substrate with a gate insulating film interposed therebetween, and masking the gate electrode in the active region A step (b) of selectively forming a pocket region of the second conductivity type, a step (c) of forming a hard mask layer made of an insulating film on both sides of the gate electrode, and an active region Etching using the hard mask layer as a mask to form a recess in a region outside the hard mask layer in the active region, and the recess comprising a mixed crystal of silicon and a group IV element and the first A step (e) of selectively forming a conductive type mixed crystal layer, and in the step (d), the wall surface on the gate electrode side in the recess has a recess protruding toward the gate electrode side, and the step (e) smell , The tip of the convex portion of the side surface mixed crystal layer is formed by a recess of the recess is covered by the pocket region.

  According to the method for manufacturing a semiconductor device of the present invention, the tip of the convex portion on the side surface where the first conductive type mixed crystal layer is formed by the concave portion of the recess is covered with the pocket region of the second conductive type. Diffusion of impurities from the mixed crystal layer into the channel region is suppressed, and variation in threshold voltage can be prevented.

  In the method for manufacturing a semiconductor device of the present invention, in the step (c), the hard mask layer includes a first hard mask layer having an L-shaped cross section and a second hard mask layer formed on the first hard mask layer. The method may further comprise a step (f) of removing the second hard mask layer after the step (e).

  According to the semiconductor device and the manufacturing method thereof according to the present invention, since the tip of the convex portion of the mixed crystal layer is covered with the pocket region, it is possible to suppress diffusion of impurities from the mixed crystal layer into the channel region due to heat treatment or the like. Therefore, fluctuations in the threshold voltage can be prevented. In addition, since the inner wall of the silicon mixed crystal layer can be formed inside the outermost surface of the sidewall, a compressive stress in the channel length direction of the channel region can be effectively applied.

It is typical sectional drawing which shows the principal part of the semiconductor device which concerns on one Embodiment of this invention. (A)-(c) is sectional drawing of the typical process order which shows the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention. (A)-(c) is sectional drawing of the typical process order which shows the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention. (A)-(c) is sectional drawing of the typical process order which shows the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention. (A)-(c) is sectional drawing of the typical process order which shows the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention. (A) And (b) is sectional drawing of the typical process order which shows the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention. 6 is a graph comparing a relationship between a gate length dimension and a threshold voltage in a semiconductor device according to an embodiment of the present invention and a modified example thereof with a conventional example. (A)-(d) shows the semiconductor device which concerns on this invention used for the measurement of FIG. 7, and a prior art example, (a) is typical sectional drawing which concerns on a prior art example, (b)-(d) These are typical sectional drawings concerning the present invention and its modification. It is typical sectional drawing which shows the principal part of the conventional semiconductor device.

(One embodiment)
An embodiment of the present invention will be described with reference to FIG.

  As shown in FIG. 1, the semiconductor device according to the present embodiment includes a CMIS (complementary metal-insulator semiconductor) transistor.

  As an example, the semiconductor substrate is made of p-type silicon (Si), and the main surface has a {100} plane orientation, and the main surface of the semiconductor substrate 10 is a shallow trench made of an insulating film. By the isolation (element isolation region) 11, an n-type transistor region A where an n-type MIS transistor is formed, a non-silicide p-type transistor region B where a non-silicide p-type MIS transistor is formed, and a silicon germanium layer (SiGe layer) The p-type MIS transistor is divided into p-type transistor regions C where the p-type MIS transistors are formed. The silicon germanium layer is a mixed crystal layer of silicon and germanium which is a group IV element.

In the n-type transistor region A, a gate electrode 13 made of polysilicon, for example, is formed on an active region made of a semiconductor substrate 10 with a gate insulating film 12 interposed, and both sides of the gate electrode 13 on the gate length direction side are formed. An offset sidewall 15 made of silicon nitride (SiN) is formed on the surface. A first hard mask layer 19 made of silicon oxide and having an L-shaped cross section and a first sidewall 21 made of silicon oxide (SiO ₂ ) are formed outside the offset sidewall 15. An n-type extension region 16 is formed below the first hard mask layer 19 above the active region of the semiconductor substrate 10, and an n-type source / drain region 23 is formed outside the n-type extension region 16. Has been. A silicide layer 26 made of a metal such as nickel (Ni) is formed on the upper portion of the gate electrode 13 and the upper portion of the source / drain region 23, respectively. Further, a first liner insulating film 27 that generates tensile stress in the gate length direction in the channel region is formed so as to cover the n-type source / drain region 23 including the gate electrode 13.

  In the non-silicide p-type transistor region B, a gate electrode 13 made of polysilicon with a gate insulating film 12 interposed on an active region made of a semiconductor substrate 10 is formed, and on the gate electrode 13, silicon nitride is formed. A gate hard mask 14 is formed. Further, offset sidewalls 15 made of silicon nitride are formed on both side surfaces of the gate electrode 13 on the gate length direction side. Outside the offset sidewall 15 are a first hard mask layer 19 made of silicon oxide and having an L-shaped cross section, a first sidewall 21 made of silicon oxide, and a second sidewall 22 made of silicon nitride. Are sequentially formed. A p-type extension region 17 is formed below the first hard mask layer 19 above the active region of the semiconductor substrate 10, and a p-type source / drain region 24 is formed outside the p-type extension region 17. Has been. Further, an n-type pocket region 18 is formed above the active region of the semiconductor substrate 10 so as to cover the lower side of the p-type extension region 17 and the p-type source / drain region 24. Further, a silicide block layer 25 made of silicon oxide is formed so as to cover the p-type source / drain region 24 including the gate electrode 13, and compressive stress is applied on the silicide block layer 25 in the gate length direction in the channel region. The resulting second liner insulating film 28 is formed.

  In the p-type transistor region C, a gate electrode 13 made of polysilicon with a gate insulating film 12 interposed on an active region made of a semiconductor substrate 10 is formed, on both side surfaces of the gate electrode 13 on the gate length direction side. An offset sidewall 15 made of silicon nitride is formed. Outside the offset sidewall 15, a first hard mask layer 19 made of silicon oxide and having an L-shaped cross section and a first sidewall 21 made of silicon oxide are formed. A p-type extension region 17 is formed below the first hard mask layer 19 in the upper part of the active region of the semiconductor substrate 10. A p-type silicon germanium layer 20 is formed outside the p-type extension region 17. A p-type source / drain region is formed. In FIG. 1, only the silicon germanium layer 20 is illustrated in the source / drain formation region. However, the present invention is not limited to this, and the silicon germanium layer 20 is formed on the semiconductor substrate 10 around the silicon germanium layer 20. A p-type diffusion region formed by diffusing type impurities may be provided. Further, an n-type pocket region 18 is formed in the active region of the semiconductor substrate 10 so as to cover the lower side of the p-type extension region 17 and the side surface of the silicon germanium layer 20. A silicide layer 26 made of a metal such as nickel (Ni) is formed on the upper portion of the gate electrode 13 and the upper portion of the silicon germanium layer 20, respectively. Further, a second liner insulating film 28 that generates compressive stress in the gate length direction in the channel region is formed so as to cover the silicon germanium layer 20 including the gate electrode 13.

  In the p-type MIS transistor formed in the p-type transistor region C, the p-type source / drain region is formed from the p-type silicon germanium layer 20 by epitaxial growth. At least the side surface on the gate electrode side in the silicon germanium layer 20 has a {111} plane of silicon crystal and has a protrusion 20a protruding toward the gate electrode side. In this specification, the convex portion 20a on the side surface is also referred to as a Σ tip portion. The gate electrode side means the gate electrode side in the gate length direction when viewed from the silicon germanium layer 20.

  As a feature of the present embodiment, the tip of the convex portion (Σ tip portion) 20 a is covered with the n-type pocket region 18. Here, the tip position in the depth direction of the protrusion 20 a in the silicon germanium layer 20 is preferably deeper than or equal to the peak position of the impurity concentration in the n-type pocket region 18. Further, the tip position in the depth direction of the convex portion 20 a in the silicon germanium layer 20 is deeper than the maximum junction depth of the p-type extension region 17 and from one-half of the maximum junction depth of the n-type pocket region 18. And deeper than the maximum junction depth of the n-type pocket region 18. Furthermore, the position of the silicon germanium layer 20 that intersects the main surface of the semiconductor substrate 10 (the upper surface of the active region immediately below the first hard mask layer 19) is outside the first hard mask layer 19 constituting the sidewall. It is formed inside the outermost surface (end). Here, the outermost outer surface of the first hard mask layer 19 means an end side surface of a lower portion extending from the gate electrode side to the source / drain region side of the first hard mask layer 19. Accordingly, the silicon germanium layer 20 is formed in contact with the lower surface of the first hard mask layer 19 so as to overlap the end portion of the first hard mask layer 19.

  In the semiconductor device according to the present embodiment, in particular, in the p-type MIS transistor formed in the p-type transistor region C, the p-type source / drain region is composed of the silicon germanium layer 20 and at least on the gate electrode side in the silicon germanium layer 20. The side surface has a protrusion 20a protruding toward the gate electrode. In addition, since the protrusion 20a is covered with the n-type pocket region 18, the diffusion of the p-type impurity from the silicon germanium layer 20 into the channel region can be suppressed. Furthermore, the tip position in the gate length direction of the protrusion 20a in the silicon germanium layer 20 is outside the side surface of the gate electrode 13 and the outermost surface on the outside of the first hard mask layer 19 constituting the sidewall ( It is formed inside the end portion. As a result, fluctuations in the threshold voltage Vt of the p-type MIS transistor can be prevented. Further, since the silicon germanium layer 20 can be formed on the channel region side with respect to the outer end portions of the sidewalls 19 and 21, it is possible to effectively apply compressive stress in the gate length direction of the channel region. it can.

  Hereinafter, an example of a method for manufacturing the semiconductor device configured as described above will be described with reference to FIGS.

  First, as shown in FIG. 2A, a shallow trench isolation (element isolation region) 11 is selectively formed on a semiconductor substrate 10 made of p-type silicon, and an n-type transistor region A, non-silicide p A type transistor region B and a p type transistor region C are partitioned. Subsequently, a p-type impurity such as boron (B) for forming a p-type well or a p-type channel region is introduced into the n-type transistor region A in the semiconductor substrate 10 by ion implantation. Further, in the non-silicide p-type transistor region B and the p-type transistor region C in the semiconductor substrate 10, an n-type impurity such as arsenic (As) for forming an n-type well or an n-type channel region is ion-implanted. Introduce. The order of the p-type impurity implantation and the n-type impurity implantation is not particularly limited.

  Subsequently, a gate insulating film forming film made of, for example, silicon oxide having a thickness of 1.5 nm is formed on the semiconductor substrate 10. Thereafter, a gate electrode formation film made of polysilicon having a film thickness of, for example, 50 nm is formed on the gate insulating film formation film by chemical vapor deposition (CVD). Here, the gate insulating film forming film is not limited to silicon oxide, and may be a stacked film in which silicon oxide and a high dielectric material such as hafnium oxide or zirconium oxide are stacked. Further, a metal layer may be inserted between the gate insulating film forming film and the gate electrode forming film to form a polymetal gate structure. The gate insulating film forming film is not limited to polysilicon.

  Subsequently, a gate hard mask forming film made of, for example, silicon nitride having a thickness of 30 nm is deposited on the gate electrode forming film by a CVD method. Thereafter, the gate hard mask forming film, the gate electrode forming film, and the gate insulating film forming film are sequentially patterned by lithography and dry etching. As a result, the gate insulating film 12 is formed from the gate insulating film forming film on each active region including the semiconductor substrate 10 in the n-type transistor region A, the non-silicide p-type transistor region B, and the p-type transistor region C. Then, the gate electrode 13 is formed from the gate electrode formation film, and the gate hard mask 14 is formed from the gate hard mask formation film. Here, the gate length dimension of each gate electrode 13 is about 28 nm to 35 nm.

Subsequently, a silicon nitride film having a thickness of, for example, 5 nm is deposited on the semiconductor substrate 10 so as to cover each gate hard mask 14 and the gate electrode 13 by a CVD method, and the deposited silicon nitride film is dry-etched. The offset sidewalls 15 are formed on both side surfaces of each gate electrode 13 by anisotropic etching. Thereafter, an n-type impurity region having a shallow junction depth is formed in the active region of the n-type transistor region A by ion-implanting an n-type impurity such as arsenic in the regions on both sides of the gate electrode 13 in the active region. An n-type extension region 16 is formed. Further, each active region of the non-silicide p-type transistor region B and the p-type MIS transistor region C is ion-implanted with p-type impurities such as boron and further ion-implanted with n-type impurities such as arsenic. A p-type extension region 17 which is a p-type impurity region having a shallow junction depth in regions on both sides of the gate electrode 13 in the active region, and a junction depth larger than the p-type extension region 17 so as to cover the bottom surface of the p-type extension region 17. An n-type pocket region 18 which is a deep n-type impurity region is formed. Here, as an ion implantation method for the n-type pocket region 18, for example, the implantation energy is set to 15 keV to 75 keV in an arsenic atmosphere, and the dose amount of the n-type impurity is set to 1 × 10 ¹³ ions / cm ² to 2 × 10 ¹³ ions / cm. ^The angle injection is performed with the inclination angle in the range of 15 ° to 38 °. As a result, the n-type impurity is implanted inside the offset sidewalls 15 on both side surfaces of the gate electrode 13. At this time, the depth of the n-type pocket region 18 is preferably about 35 nm to 45 nm, and is 40 nm here. The depth of the p-type extension region 17 is preferably about 8 nm to 12 nm, for example, 10 nm, and the dose amount of the p-type impurity is 1 × 10 ¹⁵ ions / cm ² to 2 × 10 ¹⁵ ions / cm ² . The order of implantation of the p-type extension region 17 and the n-type pocket region 18 is not particularly limited.

  Next, as shown in FIG. 2B, for example, the film thickness is 5 nm so as to cover each gate electrode 13 including each gate hard mask 14 and each offset sidewall 15 on the semiconductor substrate 10 by the CVD method. A first hard mask layer 19 made of silicon oxide is formed. Thereafter, a second hard mask layer 30 made of, for example, silicon nitride having a film thickness of 15 nm is formed on the first hard mask layer 19 by CVD.

  Next, as shown in FIG. 2C, a resist film is formed on the entire surface of the semiconductor substrate 10, and an opening pattern is formed in the p-type transistor region C by lithography on the formed resist film. Then, a resist film 31 covering the n-type transistor region A and the non-silicide p-type transistor region B is formed.

  Next, by anisotropic dry etching using the resist film 31 having an opening pattern as a mask, as shown in FIG. 3A, the second hard mask layer 30 in the p-type transistor region C and the first The hard mask layer 19 is etched sequentially. Thereby, in the p-type transistor region C, the second hard mask layer 30 and the first hard mask layer 19 remain only on the side surface of each offset sidewall 15. The first hard mask layer 19 has an L-shaped cross section at the adjacent portion between the offset sidewall 15 and the semiconductor substrate 10 due to the second hard mask layer 30. Here, the exposed width of the upper surface of the active region of the p-type transistor region C can be controlled by increasing or decreasing the thickness of each of the second hard mask layer 30 and the first hard mask layer 19. Note that the width dimension (total maximum width) of the sidewall made of the offset sidewall 15, the first hard mask layer 19, and the second hard mask layer 30 is in the range of 20 nm to 25 nm from the side surface of the gate electrode 13. It is preferable.

  Next, the resist film 31 is removed, and then the active region of the p-type transistor region C is masked with the second hard mask layer 30 by, for example, an anisotropic dry etching method and an anisotropic wet etching method. Etching is performed. Thereby, a recess region 10a for forming a source / drain region of the p-type MIS transistor is formed. At this time, since the gate hard mask 14, the offset sidewall 15 and the first hard mask layer 19 are formed on the upper surface and the side surface of the gate electrode 13, these serve as an etching mask, so that the gate electrode 13 is etched. It will never be done. In addition, the p-type extension region 17 and the n-type pocket region 18 formed in FIG. 2A are formed on the inner side of the outer side surface (end surface) of the first hard mask layer 19 by forming the recess region 10a ( Remains only on the channel side.

  The recess region 10a formed by etching has a {111} plane whose wall surface is oriented, and a substantially central portion in the depth direction is a recess (Σ tip portion) projecting to the gate electrode side below the first hard mask layer 19 ) 10b is formed. The tip position of the recess 10b in the depth direction is deeper than the maximum junction depth of the p-type extension region 17, and further deeper than half the maximum junction depth of the n-type pocket region 18b, and the n-type pocket. It is formed to be shallower than the maximum junction depth of region 18b. That is, the tip position in the depth direction of the recess 10 b is formed so as to be deeper than or equal to the peak position of the impurity concentration of the n-type pocket region 18.

  The recess region 10a formed in the semiconductor substrate 10 may be performed by combining anisotropic dry etching, isotropic dry etching, and anisotropic wet etching. That is, for example, when the semiconductor substrate 10 made of silicon whose principal plane is the {100} plane is used, an etching method in which a {111} plane wall surface is formed may be employed.

  As an example, the tip position in the depth direction of the recess 10b is preferably 18 nm to 23 nm from the upper surface of the semiconductor substrate 10 (the surface of the active region immediately below the gate electrode 13), and is 20 nm here.

  Further, in the present embodiment, in FIG. 3A, the first hard mask layer 19 and the second hard mask layer 30 thereon are mainly used as a mask when forming the recess region 10a. . That is, in the p-type transistor region C, temporary sidewalls including the first hard mask layer 19 and the second hard mask layer 30 are formed on both side surfaces of the offset sidewall 15 in the gate electrode 13. The temporary sidewall is used as a mask for forming the recess region 10a. For this reason, in the present embodiment, when a hard mask layer is formed on a normal sidewall as in the conventional manufacturing method, a residue of a hard mask layer (so-called petit petition) generated in the lower portion outside the normal sidewall is formed. Sidewall) is not formed. Therefore, in the present embodiment, the end of the recess region 10a on the gate electrode 13 side can be brought closer to the channel region by the amount that the petit side wall is not formed.

Next, as shown in FIG. 3B, the silicon germanium layer 20 doped with the p-type impurity is formed in the recess region 10a using the second hard mask layer 30 as a mask, for example, by CVD. Is epitaxially grown so as to be higher than the main surface of the semiconductor substrate 10 (the upper surface of the active region immediately below the gate electrode 13). Here, the p-type impurity concentration doped in the silicon germanium layer 20 is 3.5 × 10 ¹⁹ / cm ³ . At this time, in the p-type transistor region C, a gate hard mask 14 is formed on the gate electrode 13, and each of the active regions of the n-type transistor region A and the non-silicide p-type transistor region B is in the second hard region. Since it is covered with the mask layer 30, the silicon germanium layer 20 is selectively grown only in the recess region 10a where silicon is exposed. Note that the position of the silicon germanium layer 20 that intersects the main surface of the semiconductor substrate 10 (the upper surface of the active region immediately below the first hard mask layer 19) is outside the first hard mask layer 19 constituting the sidewall. It is formed on the inner side (channel side) than the side surface (end surface). At this time, the tip position in the gate length direction of the convex portion 20a grown in the concave portion 10b of the recess region 10a in the silicon germanium layer 20 does not reach below the gate electrode 13, and the first hard mask layer 19 is located below.

  Next, as shown in FIG. 3C, the second hard mask 30 made of silicon nitride and the gate hard mask 14 in the p-type transistor region C are selectively formed by hot phosphoric acid having a temperature of 160 ° C., for example. Remove. At this time, since the first hard mask 19 made of silicon oxide remains in the n-type transistor region A and the non-silicide p-type transistor region B, the gate hard mask 14 is not etched.

  Next, as shown in FIG. 4A, a first sidewall formation film 21A made of silicon oxide having a film thickness of, for example, 4 nm is formed on the entire surface of the semiconductor substrate 10 by CVD. Specifically, in the n-type transistor region A and the non-silicide p-type transistor region B, the first sidewall formation film 21 A is formed on the first hard mask 19. In the p-type transistor region C, the first sidewall formation film 21A is continuously formed on the silicon germanium layer 20 and the first hard mask layer 19, the upper end of the offset sidewall 15 and the upper surface of the gate electrode 13. The film is formed. Subsequently, a second sidewall formation film 22A made of, for example, silicon nitride having a film thickness of 15 nm is formed on the entire surface of the first sidewall formation film 21A.

  Next, as shown in FIG. 4B, the second sidewall formation film 22A, the first sidewall formation film 21A, and the first hard mask layer 19 are sequentially etched by anisotropic dry etching. To do. As a result, in the n-type transistor region A, the non-silicide p-type transistor region B, and the p-type transistor region C, the cross-sectional shape formed on the side surface of each gate electrode 13 is on the L-shaped first hard mask layer 19. In addition, a first sidewall 21 having a substantially L-shaped cross section is formed from the first sidewall formation film 21A, and the second sidewall formation film 22A to the second sidewall 21A are formed on the first sidewall 21. Sidewalls 22 are formed.

  At this time, the width dimension (total maximum width) of the side wall composed of the first hard mask layer 19, the first side wall 21 and the second side wall 22 is the first side wall 21 and the second side wall. It can be controlled by changing the film thickness of the side wall 22. Here, the width of the sidewall is set to about 22 nm to 26 nm. In FIG. 4B, the lower end face positions outside the first sidewall 21 and the second sidewall 22 coincide with the lower end face positions outside the first hard mask layer 19, The first side wall 21 and the second side wall 22 do not necessarily need to be matched. When the film thickness of the first side wall 21 and the second side wall 22 is increased, the first side is covered so as to cover the lower end surface outside the first hard mask layer 19. A wall 21 and a second sidewall 22 are formed.

  The heights of the gate electrode 13, the first hard mask layer 19, the first sidewall 21, and the second sidewall 22 in the p-type transistor region C are exposed to the etching gas during the etching of the first sidewall 21. And the gate hard mask 14 does not remain, so that it is finished lower than the side walls 21 and 22 formed in the n-type transistor region A and the non-silicide p-type transistor region B. In addition, the first hard mask layer 19 in the p-type transistor region C has a recess region 10a and a silicon germanium layer as compared with the first hard mask layers 19 in the n-type transistor region A and the non-silicide p-type transistor region B. Since the etching is performed at the time of forming 20 and before and after the cleaning process, the film thickness is reduced. For this reason, the width dimension of the sidewall in the p-type transistor region C is smaller than that in the case of the n-type transistor region A and the non-silicide p-type transistor region B.

  Next, as shown in FIG. 4C, in the active region of the n-type transistor region A, the gate electrode 13 is used as a mask, that is, the gate hard mask 14, the offset sidewall 15, the first hard mask layer 19, For example, n-type impurities such as arsenic are selectively ion-implanted using the first sidewall 21 and the second sidewall 22 as a mask. As a result, an n-type source / drain region 23 which is an n-type impurity region having a deep junction depth is formed outside the n-type extension region 16 in the active region of the n-type transistor region A. Subsequently, a p-type impurity such as boron is selectively ion-implanted into the active region of the non-silicide p-type transistor region B using the gate electrode 13 and the like as a mask. As a result, the p-type source / drain region 24 which is a p-type impurity region having a deep junction depth is formed outside the p-type extension region 17 and above the n-type pocket region 18 in the active region of the non-silicide p-type transistor region B. It is formed. The order of forming the n-type source / drain region 23 and the p-type source / drain region 24 is not particularly limited. Thereafter, each impurity introduced by ion implantation is activated by, for example, rapid annealing at a temperature of 950 ° C. and 1 second or less.

  Next, as shown in FIG. 5A, a silicide block layer 25 made of, for example, silicon oxide having a thickness of 16 nm is deposited on the entire surface of the semiconductor substrate 10 by CVD. The diffusion distance of boron diffused from the silicon germanium layer 20 to the channel region by the heat treatment up to this step is, for example, about 3 nm to 8 nm. Thereafter, although not shown, a resist film that covers the non-silicide p-type transistor region B and has an opening pattern in the n-type transistor region A and the p-type transistor region C is formed by lithography.

  Next, as shown in FIG. 5B, the silicide block layer 25 is etched from the n-type transistor region A and the p-type transistor region C by etching the silicide block layer 25 using a resist film (not shown) as a mask. Remove.

  Next, as shown in FIG. 5C, the second layer made of silicon nitride in the n-type transistor region A and the p-type transistor region C is formed by hot phosphoric acid having a temperature of 160 ° C., for example, using the silicide block layer 25 as a mask. The side wall insulating film 22 and the gate hard mask 14 made of silicon nitride in the n-type transistor region A are selectively removed. At this time, since the non-silicide p-type transistor region B is masked by the silicide block film 25, the gate hard mask 107 and the second sidewall 22 remain.

  Next, as shown in FIG. 6A, a salicide method is performed in which, for example, a nickel film is deposited on the entire surface of the semiconductor substrate 10 and a predetermined heat treatment and unreacted nickel are removed. Thus, in the n-type transistor region A and the p-type transistor region C, silicide layers 26 made of nickel and silicon are formed on the gate electrode 13, the n-type source / drain region 23, and the silicon germanium layer 20, respectively. Although nickel is used to form the silicide layer 26, the silicide layer 26 is not limited to nickel, and a silicide layer made of another metal such as platinum (Pt) or cobalt (Co) may be used.

  Next, as shown in FIG. 6B, the first liner insulating film 27 having a tensile stress made of, for example, silicon nitride having a film thickness of 16 nm is selected by the CVD method so as to cover the n-type transistor region A. Form. Subsequently, the second liner insulating film 28 made of, for example, silicon nitride having a film thickness of 20 nm is selectively formed by CVD so as to cover the non-silicide p-type transistor region B and the p-type transistor region C. Form.

  Thereafter, although not shown, a semiconductor device including a CMIS transistor can be obtained by forming necessary contacts and wirings.

  As described above, according to the present embodiment, the silicon germanium layer 20 that is the p-type source / drain region formed in the p-type transistor region C can be reliably brought close to the channel region below the gate electrode 13. In addition, even if the silicon germanium layer 20 is brought close to the channel region, the p-type introduced into the silicon germanium layer 20 by the n-type pocket region 18 covering the tip of the convex portion 20a of the silicon germanium layer 20. It is possible to prevent boron, which is an impurity, from diffusing into the channel region due to heat. As a result, as in the prior art, it is possible to prevent problems such as the fact that boron due to thermal diffusion disturbs the distribution profile of the impurity element previously implanted and the driving force of the p-type MIS transistor is reduced.

  In the present embodiment, the MIS transistor having a strained structure that applies compressive stress to the channel region is a p-type transistor, but the present invention is not limited to a p-type transistor. That is, it is possible to apply a tensile stress to the channel region of the n-type MIS transistor. In this case, a silicon-carbon mixed crystal layer constituting the source / drain region is used. Some silicon carbide (SiC) can be used.

  Hereinafter, a comparison result of electrical characteristics between the p-type MIS transistor according to the conventional example and the p-type MIS transistor according to the present embodiment will be shown. FIG. 7 shows the relationship between the gate length dimension (Lg) and the threshold voltage (Vtsc). FIGS. 8A to 8D are transistor structures corresponding to a to d in the graph shown in FIG. 7, wherein FIG. 8A is a conventional structure, and FIGS. The structure which concerns on a form and its modification is shown. Specifically, in the conventional transistor structure shown in FIG. 8A, the n-type pocket region 107 does not completely cover the tip of the convex portion of the silicon mixed crystal layer 108 made of SiGe. On the other hand, in the transistor structure according to the present invention shown in FIGS. 8B to 8D, the n-type pocket region 17 completely covers the tip of the convex portion of the silicon germanium layer 18.

  As shown in FIG. 7, in the case of the conventional structure a shown in FIG. 8A, the threshold voltage characteristic tends to fluctuate when the gate length dimension is smaller than 0.1 μm. Further, it can be seen that when the gate length dimension is 0.06 μm or less, the threshold voltage characteristics are significantly lowered, and the short channel effect becomes apparent. As described above, this is because boron is diffused from the silicon mixed crystal layer 108 serving as the source and drain into the channel region, and the distribution profile of the n-type impurity element implanted into the channel region is disturbed. This is because the characteristics deteriorate.

  On the other hand, in the case of this embodiment, even when the gate length dimension is 0.04 μm, the threshold voltage characteristic is small, which is advantageous for the short channel characteristic. In addition, since the silicon germanium layer 20 can be brought close to the channel region, the driving force of the p-type MIS transistor can be effectively improved.

  As a modification of the configuration in which the n-type pocket region 18 covers the convex portion of the silicon germanium layer 20, as shown in FIG. 8C, a configuration in which the n-type pocket regions 18 facing each other are in contact with each other, or FIG. As shown in FIG. 8D, it can be seen that even if the n-type pocket regions 18 overlap each other, the same or higher effect can be obtained.

  The semiconductor device and the manufacturing method thereof according to the present invention can prevent threshold voltage fluctuations and can effectively apply compressive stress in the gate length direction of the channel region. This is useful for a semiconductor device including a MISFET including a silicon mixed crystal layer.

A n-type transistor region B Non-silicide p-type transistor region C p-type transistor region 10 Semiconductor substrate 10a Recess region 10b Recess 11 Shallow trench isolation 12 Gate insulating film 13 Gate electrode 14 Gate hard mask 15 Offset sidewall 16 n-type extension region 17 p-type extension region 18 n-type pocket region 19 first hard mask layer 20 silicon germanium layer (p-type source / drain region)
20a Convex (Σ tip)
21 first sidewall 21A first sidewall formation film 22 second sidewall 22A second sidewall formation film 23 n-type source / drain region 24 p-type source / drain region 25 silicide block layer 26 silicide layer 27 first Liner insulating film 28 second liner insulating film 30 second hard mask layer 31 resist film

Claims (11)

A gate electrode formed on a first conductivity type active region made of a semiconductor substrate with a gate insulating film interposed therebetween;
A source / drain region of a second conductivity type formed in regions on both sides of the gate electrode in the active region;
A pocket region of a first conductivity type formed from the side surface of each source / drain region in the active region toward the lower side of the gate electrode,
The source / drain region is composed of a mixed crystal layer of silicon and a group IV element,
The mixed crystal layer has a convex portion in which the side surface on the gate electrode side in the gate length direction protrudes to the gate electrode side,
The semiconductor device according to claim 1, wherein a tip end of the convex portion is covered with the pocket region.   2. The semiconductor device according to claim 1, wherein a tip position in the depth direction of the convex portion in the mixed crystal layer is deeper than or equal to a peak position of the impurity concentration of the pocket region. An extension region of a second conductivity type formed from the side surface of each source / drain region above the active region toward the lower side of the gate electrode;
The tip position in the depth direction of the convex portion in the mixed crystal layer is deeper than the maximum junction depth of the extension region and deeper than half of the maximum junction depth of the pocket region. The semiconductor device according to claim 1 or 2. Further comprising a sidewall made of an insulating film formed on both side surfaces of the gate electrode on the gate length direction side,
The position where the mixed crystal layer intersects with the upper surface of the active region is formed on the inner side of the outermost surface on the outer side of the sidewall. Semiconductor device.   The semiconductor device according to claim 1, wherein a tip position of the convex portion in the mixed crystal layer is 18 nm or more and 23 nm or less from the surface of the active region.   The semiconductor device according to claim 1, wherein the group IV element constituting the mixed crystal layer is germanium.   6. The semiconductor device according to claim 1, wherein the group IV element constituting the mixed crystal layer is carbon. Metal silicide layers respectively formed on the gate electrode and the mixed crystal layer;
8. The liner insulating film according to claim 1, further comprising a liner insulating film formed on the active region so as to cover the gate electrode and the mixed crystal layer including the metal silicide layer. The semiconductor device according to item.   The semiconductor device according to claim 1, wherein the pocket regions facing each other are in contact with each other under the gate electrode. A step (a) of forming a gate electrode on a first conductivity type active region made of a semiconductor substrate with a gate insulating film interposed therebetween;
A step (b) of selectively forming a pocket region of the second conductivity type in the active region using the gate electrode as a mask;
A step (c) of forming a hard mask layer made of the insulating film on both side surfaces of the gate electrode;
(D) forming a recess in a region outside the hard mask layer in the active region by etching the active region using the hard mask layer as a mask;
A step (e) of selectively forming a mixed crystal layer of a first conductivity type composed of a mixed crystal of silicon and a group IV element in the recess;
In the step (d), the wall surface on the gate electrode side in the recess has a recess protruding to the gate electrode side,
In the step (e), the tip of the convex portion on the side surface where the mixed crystal layer is formed by the concave portion of the recess is covered with the pocket region. In the step (c), the hard mask layer includes a first hard mask layer having an L-shaped cross section and a second hard mask layer formed on the first hard mask layer,
11. The method for manufacturing a semiconductor device according to claim 10, further comprising a step (f) of removing the second hard mask layer after the step (e).

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