JP2002057118A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form a shallower impurity diffusion layer. SOLUTION: A thin impurity diffusion inhibition layer with an approximately 1 nm thickness is buried into a semiconductor region for forming such impurity diffusion layer as source/drain regions in advance. In annealing, the thermal diffusion of impurity is inhibited by the impurity diffusion inhibition layer, electrical junction depth becomes shallower, and at the same time impurity concentration becomes higher at a region being shallower than the impurity diffusion layer, thus reducing resistance in the impurity diffusion layer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having a shallow impurity diffusion layer and a method of manufacturing the same.

[0002]

2. Description of the Related Art A MOSFET (Metal Oxide Semiconducto
r Field-Effect Transistor) is becoming finer.
In order to suppress a decrease in threshold voltage due to a short channel effect accompanying miniaturization of MOSFETs, the junction depth (xj) of a source / drain region as a diffusion layer must be further reduced.

Conventionally, in order to form a shallow diffusion layer, a method of lowering the acceleration energy at the time of ion implantation or a thermal diffusion step (annealing step) for activating the diffusion layer is performed in a shorter time at a lower temperature. And the like.

[0004]

However, in the above-described method of forming a shallow diffusion layer, since a high concentration impurity layer exists near the surface of the diffusion layer, some of these impurities are adjacent to each other due to outward diffusion. Easily escapes into the insulating layer provided. Therefore, it becomes difficult to form a low-resistance diffusion layer because the resistance of the diffusion layer increases due to the manifestation of such out-diffusion of impurities.

Further, when point defects are formed by ion implantation, the damage speeds up the diffusion of impurities, so that it has been difficult to stably form a shallow diffusion layer of 50 nm or less.

An object of the present invention is to provide a semiconductor device capable of forming a shallow diffusion layer more reliably and stably, and a method of manufacturing the same.

[0007]

The semiconductor device of the present invention is characterized in that a semiconductor region of a first conductivity type, an impurity diffusion region of a second conductivity type formed in an upper layer in the semiconductor region,
An impurity diffusion suppressing layer formed in a film shape in the impurity diffusion region.

According to the semiconductor device having the above-described features, the impurity diffusion suppressing layer suppresses thermal diffusion of impurities to a deeper region in the process of forming the impurity diffusion region. That is, the junction depth can be reduced. Since the junction depth can be adjusted depending on the position of the impurity diffusion suppression layer, a more accurate diffusion layer can be formed. In the layer above the impurity diffusion suppressing layer, a uniform high concentration impurity diffusion region is formed in the depth direction.

That is, in the impurity diffusion region of the semiconductor device having the above-described characteristics, the impurity concentration contributing to the second conductivity type in the depth direction is formed by annealing with the impurity diffusion suppressing layer as a boundary. There is a region that shows a steeper decrease in impurity concentration than the concentration distribution in the depth direction.

In the semiconductor device having the characteristics described above, it is preferable that the impurity diffusion suppressing layer has a lower diffusion coefficient for the impurity in the impurity diffusion region than that of the semiconductor region. In this case, in the process of forming the impurity diffusion region, the thermal diffusion of the impurity can be more reliably suppressed.

In the semiconductor device having the characteristics described above, it is preferable that the impurity diffusion suppressing layer has a thickness that does not affect the electric conductivity of the impurity contributing to the second conductivity type. As described above, by setting the thickness of the impurity diffusion layer so as not to affect the electric conductivity, it is possible to prevent the electric conductivity from being adversely affected.

Further, in the semiconductor device having the above-mentioned characteristics, the semiconductor region is a silicon-based semiconductor,
The impurity diffusion suppressing layer may be any one of a silicon oxynitride film, a silicon oxide film and a silicon nitride film.

Further, in the semiconductor device having the above-described characteristics, the thickness of the impurity diffusion suppressing layer may be 1 nm or less. In this case, the diffusion of the impurity can be suppressed, and the electric conductivity of the impurity can be more reliably prevented from being affected.

In the semiconductor device having the characteristics described above, the second conductivity type impurity diffusion region may be made of a different semiconductor material in an upper layer and a lower layer with the impurity diffusion suppressing layer as a boundary. For example, the upper layer is made of SiGe
And a lower layer may be a Si layer.

In the semiconductor device having the above-mentioned characteristics, the MOS device having the impurity diffusion region as a source / drain region
It may have an FET. Reliable MOSFE with low resistance and shallower source / drain regions
T can be provided.

Next, a first feature of the method of manufacturing a semiconductor device according to the present invention is that a step of forming an impurity diffusion suppressing layer on a main surface of a semiconductor region of the first conductivity type includes the impurity diffusion suppressing layer. Forming a first semiconductor layer of the first conductivity type on the main surface; and adding an impurity contributing to the second conductivity type to a region shallower than the impurity diffusion suppression layer with respect to the main surface including the first semiconductor layer. And an annealing step for activating the impurities.

According to the first feature of the manufacturing method described above,
At the time of the annealing step, the impurity diffusion suppressing layer suppresses the thermal diffusion of the impurity to the substrate deeper, so that the junction depth can be made shallower than when there is no impurity diffusion suppressing layer. In addition, a high-concentration impurity diffusion region having a substantially uniform depth can be formed in the depth direction from the substrate surface to the impurity diffusion suppressing layer, so that the resistance can be reduced.

In the above-described manufacturing method, the step of adding may be an ion implantation step.

A second feature of the method of manufacturing a semiconductor device according to the present invention is that, in the method of manufacturing a MOSFET, a step of forming an impurity diffusion suppression layer on a main surface of a semiconductor region of the first conductivity type; Patterning a layer so as to remain in a region where a source / drain region is formed; forming a first semiconductor layer of a first conductivity type on a main surface including the impurity diffusion suppressing layer; A step of forming a gate insulating film on the surface of the semiconductor layer, a step of forming a gate electrode on the gate insulating film, and using the gate electrode as a mask, removing impurities contributing to a second conductivity type from the impurity diffusion suppressing layer. A shallow ion implantation step; and an annealing step for activating the impurities.

According to a second feature of the manufacturing method described above,
In forming the source / drain regions, during the annealing step, the impurity diffusion suppressing layer suppresses the thermal diffusion of impurities deeper into the substrate.
The junction depth of the drain region can be made shallower than when there is no impurity diffusion suppression layer. In addition, since a high-concentration impurity diffusion region that is substantially uniform in the depth direction can be formed from the substrate surface to the impurity diffusion suppression layer, the resistance of the source / drain region can be reduced.

A third feature of the manufacturing method of the present invention is that a MOS
In the method for manufacturing an FET, a step of forming an impurity diffusion suppression layer on a main surface of a semiconductor region of the first conductivity type, and forming a first semiconductor layer of the first conductivity type on a main surface including the impurity diffusion suppression layer And removing a portion of the impurity diffusion suppressing layer in a region to be a channel layer and a layer including the first semiconductor layer thereon by etching to form a groove on the bottom surface such that the semiconductor region is exposed. And the groove is formed of a second conductive type.
Embedding with a semiconductor layer, forming a gate insulating film on the second semiconductor layer, forming a gate electrode on the gate insulating film, and contributing to the second conductivity type using the gate electrode as a mask A step of ion-implanting an impurity to be formed shallower than the impurity diffusion suppressing layer; and a step of performing annealing for activating the impurity.

According to the third feature of the manufacturing method described above,
In forming the source / drain regions, during the annealing step, the impurity diffusion suppressing layer suppresses the thermal diffusion of impurities deeper into the substrate.
The junction depth of the drain region can be made shallower than when there is no impurity diffusion suppression layer. In addition, since a high-concentration impurity diffusion region that is substantially uniform in the depth direction can be formed from the substrate surface to the impurity diffusion suppression layer, the resistance of the source / drain region can be reduced. Further, in the above manufacturing method, the impurity diffusion suppressing layer in the channel region is removed by etching to form a groove, and the second semiconductor layer is deposited after exposing the underlying semiconductor region. The degree of freedom in selecting the material of one semiconductor layer is increased. Further, it is also possible to easily use different film materials for the source / drain region and the channel region.

In the method of manufacturing a semiconductor device having the above-described first to third features, the impurity diffusion suppressing layer may determine a diffusion coefficient of an impurity contributing to the second conductivity type at an annealing temperature with the first conductivity type. It is preferable to make it smaller than the type semiconductor region. In this case, the impurity diffusion suppression layer more reliably suppresses impurity diffusion in the annealing step, and makes the junction position shallower.

In the manufacturing method having the above-described first to third features, the impurity diffusion layer may have a thickness that does not affect the electrical conductivity of impurities contributing to the second conductivity type. In this case, the impurity diffusion suppressing layer does not affect the conductivity, and the thickness is sufficiently small, so that epitaxial growth can be promoted on the impurity diffusion suppressing layer.

In the method of manufacturing a semiconductor device having the above-described first to third features, the semiconductor region is a silicon-based semiconductor, and the impurity diffusion suppressing layer is a silicon oxynitride film, a silicon oxide film, It may be a nitride film.

Further, the first semiconductor layer may be composed mainly of the same material as the semiconductor region, or may be composed mainly of a material different from the semiconductor region. For example, the semiconductor region may include Si as a main component, and the first semiconductor layer may include SiGe as a main component. The semiconductor region includes Si as a main component, and the first semiconductor layer includes SiGe as a main component. Is also good.

[0027]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view of a MOSFET showing a structure of a semiconductor device according to a first embodiment of the present invention.

As shown in FIG. 1, the semiconductor device according to the first embodiment has a gate electrode 30 on a semiconductor substrate 10 with a gate insulating film 20 interposed therebetween, similarly to a normal MOSFET.
The oxide film 40 and the sidewall oxide film 50 are formed from both side surfaces of the gate electrode 30 to the substrate.

A feature of the MOSFET of the present embodiment is that an impurity diffusion suppressing layer 60 is formed in the source / drain region 70. The source / drain region 70 usually has an extension structure having a two-stage junction depth, but an impurity diffusion suppression layer 60 (hereinafter referred to as a diffusion suppression layer 60) is provided at a position slightly shallower than a shallow junction. Have been.

The diffusion suppressing layer 60 is formed before forming the source / drain regions. The diffusion suppressing layer 60 is
A conductor, an insulator, or a semiconductor material may be used, but it is preferable to use a material having a smaller impurity diffusion coefficient than at least the semiconductor substrate 10. Further, it is preferable that the thickness is small enough not to affect the conductive characteristics of the impurity carrier.

FIG. 2 shows a MOSFET according to this embodiment.
FIG. 4 is an expected conceptual diagram of an impurity concentration distribution in a depth direction in a source / drain region of FIG. Note that this impurity concentration distribution corresponds to the position of broken line AB in FIG.

FIG. 2 shows the impurity concentration distribution during ion implantation and the impurity concentration distribution after annealing. In the semiconductor device according to the present embodiment, an ion-implanted layer formed by ion implantation is formed at a position shallower than diffusion-suppressing layer 60. By the annealing performed thereafter, the impurities are activated and thermally diffuse deeper into the substrate.

The diffusion suppressing layer 60 blocks impurities implanted into the substrate surface from being diffused in a deeper direction in the annealing step, and makes the impurity concentration between the substrate surface and the diffusion suppressing layer 60 substantially uniform. It is considered to have an effect. Note that some impurities pass through the diffusion suppression layer 60 and diffuse more deeply.
The pn junction position, which is electrically offset by the impurity concentration of the opposite conductivity type of the semiconductor substrate 10 itself, is formed at a slightly deeper position in the diffusion suppression layer 60, and the junction position is smaller than when the diffusion suppression layer 60 is not present. Expected to be quite shallow.

FIGS. 3A and 3B show the diffusion suppressing layer 6.
In order to confirm the effect of 0, M obtained by simulation based on the more detailed conditions of this embodiment shown in FIG.
FIG. 4 is a diagram showing an impurity concentration distribution in a source / drain region of an OSFET.

FIG. 3A shows an impurity concentration distribution corresponding to the present embodiment in which the diffusion suppressing layer 60 is formed. As the simulation conditions, a p-type Si single crystal substrate having an impurity concentration of 3 × 10 ¹⁷ cm ⁻³ is used as the semiconductor substrate 10, a 1-nm-thick SiON film is used as the diffusion suppression layer 60, and It was assumed that a Si epitaxial layer having a thickness of 30 nm was formed. A SiO ₂ film having a thickness of 2 nm was formed as a gate insulating film 20 on the surface of the Si substrate, and ion implantation of impurities was performed from above the SiO ₂ film.

The ion implantation conditions were that As (arsenic) ions contributing to the n-type were used as the impurities to be implanted, the acceleration energy was 5 keV, and the dose was 5 × 10 ¹⁵ cm ⁻² . Annealing conditions for activating impurities after ion implantation were set at an annealing temperature of 1050 ° C. and an annealing time of 60 seconds longer than usual.

For comparison, FIG. 3B shows the result of an impurity concentration distribution simulation performed under the condition without the diffusion suppressing layer 60.

3A and 3B, the impurity concentration distribution at the time of ion implantation is indicated by a broken line A, and the impurity concentration distribution after annealing is indicated by a solid line A '. As can be seen from a comparison between the two, the impurity concentration distribution of As greatly changes depending on the presence or absence of the diffusion suppressing layer 60. As expected in FIG. 2, under the conditions of the present embodiment, the impurity concentration distribution after annealing is greatly suppressed here by the presence of the SiON film serving as the diffusion suppressing layer 60, and the impurity concentration sharply increases. decrease. The degree of the decrease is steeper than the change in the impurity concentration formed by annealing. On the other hand, only some As exceeds the diffusion suppressing layer 60, and the pn junction position is
It can be just below 0.

That is, when there is no diffusion suppressing layer as shown in FIG. 3B, the junction depth is about 70 μm, whereas in the present embodiment, as shown in FIG. , The pn junction position is about 50 nm from the substrate surface.
It can be seen that the film is formed at a shallower position.

Further, as shown in FIG.
Under the conditions, As from the substrate surface to the diffusion suppressing layer 60
The concentration shows a high concentration almost uniformly, and the concentration is about 1.8 ×
10 ²⁰cm^-3And the diffusion suppressing layer shown in FIG.
About 1.3 × 10 when there is no²⁰cm
^-3It can be seen that the concentration can be made higher than that of.

As can be seen from the above simulation results, in the MOSFET structure shown in FIG. 1, when the source / drain diffusion layer 70 is formed, the above-described diffusion suppressing layer 60 is formed in advance, so that the resistance is lower than in the conventional case. And shallower source / drain diffusion layer 7
0 can be formed.

The diffusion suppressing layer 60 functions as a barrier with respect to thermal diffusion of impurities. However, since its thickness is as thin as about 1 nm, it does not act as an insulator for carriers such as electrons and holes, but as a conductor or conductor. Can be treated like a semiconductor. In other words, when the diffusion suppressing layer 60 is formed to be a thin film of about 1 nm or less, the transport of carriers is hardly hindered due to a tunnel effect or a decrease in band gap due to a change in film quality due to the thinning.

However, the thickness of the diffusion suppressing layer 60 can be slightly changed as long as the conductivity of the impurity is not affected. For example, when the temperature of the annealing step is set higher, it is desirable to increase the thickness of the diffusion suppressing layer 60 to increase the diffusion suppressing force. Conversely, when the annealing temperature is lower, the film thickness can be reduced.

The diffusion suppressing power of the diffusion suppressing layer 60 can be adjusted not by the film thickness but by the film quality.
For example, when using the diffusion suppression layer 60SiON film,
By increasing the ratio of N to O, the diffusion suppressing power can be increased.

In the above example, the diffusion suppressing layer 60 is made of S
Although an iON film is used, the invention is not limited to this. SiON
Other than film, for example, SiC film or SiN film SiO₂Membrane, Ta
₂O ₅Other insulating films such as films, or conductive films not limited to insulating films
An electric film or a semiconductor film may be used. When annealing from the semiconductor substrate
Small impurity diffusion coefficient, effective in suppressing diffusion of implanted impurities
Anything that has fruit can be used.

Under the above simulation conditions, a 30 nm Si layer is formed on the diffusion suppressing layer 60, but the semiconductor layer formed on the diffusion suppressing layer 60 does not necessarily need to use the same material as the semiconductor substrate. For example, when a Si substrate is used, a semiconductor layer other than Si, such as SiGe, may be formed. For example, when SiGe is used, there is an advantage that a high-speed operation device can be formed.

In the above simulation conditions, As is used as the impurity, but any impurity other than As can be used.

Next, with reference to FIGS. 4A to 4C, an example of a method for forming a diffusion suppressing layer formed in a source / drain diffusion layer having a MOSFET structure will be described.
Here, the case where the diffusion suppressing layer is embedded in the Si substrate will be described.

First, as shown in FIG. 4A, an SiON film 61 is formed on the surface of the Si substrate 11 to a thickness of about 1 nm. As a film forming condition, a method of performing a heat treatment in an oxynitriding atmosphere such as NO or N ₂ O, or a method of forming an oxide film and then performing a heat treatment in an ammonia atmosphere to form a SiON film are used. It does not matter.

Next, as shown in FIG.
A resist film 81 is formed on the film 61 and patterning is performed. Using this resist pattern as an etching mask,
The SiON film 61 is etched. An SiON film 61 pattern is formed in the source / drain formation regions on both sides of the MOSFET channel formation region. The etching may be wet etching using dilute hydrofluoric acid or the like, or may be dry etching using RIE (Reactive Ion Etching) or the like.

As shown in FIG. 4C, after the remaining resist is removed by ashing, an Si epitaxial layer 12 of about 30 nm is formed on the substrate surface. Usually SiON
It is inherently difficult to epitaxially grow Si on the film due to lattice mismatch due to the hetero interface, but SiO
Since the thickness of the N film 61 is very thin, 1 nm, the SiON film itself is greatly affected by the crystal structure of the underlying Si substrate,
Even with the SiON film 61 interposed, an Si epitaxial growth layer can be formed. Thus, the Si substrates (11, 12) in which the diffusion suppressing layer made of the SiON film 61 is embedded can be formed.

Thereafter, a gate insulating film and a gate electrode are formed in accordance with a normal MOSFET manufacturing process, and if an ion implantation process using the gate electrode as a mask and a subsequent annealing process are performed, low resistance is obtained. A MOSFET having a shallow source / drain diffusion layer can be formed.
As in the case of the MOSFET shown in FIG. 1, in order to form a source / drain diffusion layer having an extension structure, after ion implantation of impurities using a gate electrode as a mask, sidewall oxide films are formed on both side walls of the gate electrode. To form
A second impurity ion implantation step using the gate electrode and the sidewall oxide film as a mask may be added.

FIGS. 5A to 5H are process diagrams showing another example of a method for manufacturing a MOSFET according to the present embodiment. This will be described below with reference to the drawings.

First, as shown in FIG. 5A, an SiON film 65 having a thickness of about 1 nm is formed on a p-type single crystal Si substrate 13. Subsequently, as shown in FIG. 5B, an Si layer 14 is deposited on the SiON film 65 to a thickness of about 30 nm. Si layer 14
May be polycrystalline or amorphous.

As shown in FIG. 5C, the surface of the Si layer 14 is thermally oxidized to form a SiO ₂ film 100. Then, S
A dummy gate electrode 110 is formed by depositing p-type polycrystalline Si on the iO ₂ film 100 and performing patterning. The material of the dummy gate electrode 110 is not particularly limited because it is removed by etching in a later step. Further, a dummy side wall oxide film 120 made of a SiN film is formed on the side wall of the dummy gate electrode 110, and the BPSG (Bron Phosphor Silicon) is formed.
cate Glass) is deposited, and CM is deposited.
The substrate surface is flattened by P (Chemical Mechanical Polishing). Note that these dummy gate structures are formed in accordance with the manufacture of other elements formed on the same substrate in a normal LSI process.

Thereafter, as shown in FIG. 5D, the dummy gate electrode 110 and the underlying SiO ₂ film 100, Si
The layer 14, the SiON film 65, and a part of the Si substrate 13 thereunder are removed by etching using RIE. The crystal plane of Si substrate 13 is exposed at the bottom of the etched groove.

As shown in FIG. 5E, a p-type epitaxial Si layer 13A is formed in the trench by epitaxial growth.
Is formed and SiON is formed on its surface as a gate insulating film 25.
A film is formed with a thickness of about 3 nm. Subsequently, polycrystalline Si is formed on the gate insulating film 25 so as to fill the trench, the surface is flattened by a CMP process, and after the gate electrode 35 is formed, the interlayer insulating film 90 and the dummy sidewall oxide film 120 are formed. Is removed by etching using a chemical solution such as dilute hydrofluoric acid or hot phosphoric acid.

Next, as shown in FIG. 5 (f), using the gate electrode 35 as a mask, the n-type impurity As
To form an ion-implanted layer 75 shallower than the SiON film 65. The ion implantation conditions at this time include, for example, an acceleration energy of 5 keV and a dose of 1 × 10 ¹⁵ cm.
^-2 .

As shown in FIG. 5G, an oxide film 45 is formed from the side wall of the gate electrode 35 to the surface of the substrate in order to make the source / drain diffusion layers have an extension structure. As shown, sidewall oxide films 55 are formed on both sides of the gate electrode 35. The second ion implantation is performed again using the gate electrode 35 and the sidewall oxide film 55 as a mask. Thereafter, to activate the injected As,
Annealing is performed. The annealing condition is that the annealing temperature is 10
50 ° C., treatment time about 10 seconds. As ions implanted by this annealing process are thermally diffused in a deeper direction, but SiO 2 formed as an impurity diffusion suppressing layer is diffused.
Due to the effect of the N film 65, thermal diffusion is suppressed. Particularly in the shallow diffusion layer region inside the extension structure,
A pn junction is formed at a position slightly deeper than the SiON film 65, and the junction position of the source / drain diffusion layer 75 becomes shallower.

The MOSFE shown in FIGS. 5 (a) to 5 (h)
In the manufacturing method of T, once the channel region is SiO
The Si layer 14 formed on the N film 65 is removed by etching together with the SiON film 65, and the Si layer is epitaxially grown again on the Si substrate 13 exposed on the bottom surface by this etching. Therefore, even if it is desired to form an epitaxial layer in the channel region, the Si layer 14 formed on the SiON film 65 does not need to be an epitaxial film. Therefore, according to the above-described manufacturing method, the degree of freedom can be increased depending on the film quality and the film forming conditions of the diffusion suppressing layer and the semiconductor layer formed thereon. In this manufacturing method,
Needless to say, the film quality and thickness of each layer can be changed as appropriate.

In the above-described example, the structure in which the Si layer made of the same material is formed in both the upper and lower layers of the diffusion suppressing layer has been described. However, different materials may be used. If the manufacturing method of FIGS. 5A to 5H described above is used, FIG.
It is also possible to use partially different materials as shown in FIGS.

For example, in the structure shown in FIG. 6A, a Si layer is formed on the diffusion suppressing layer 65 in the source / drain region 75.
A Ge layer 15 is formed. In the structure shown in FIG. 6B, only the channel region is replaced with SiGe17. Further, in the structure shown in FIG. 6C, the upper layer and the channel region of the diffusion suppressing layer 65 in the source / drain region 75 are both SiGe layers 15 and 17. In any structure, the SiGe layer is formed in the region where the SiGe layer is formed.
Due to the high mobility characteristics, the resistance is reduced and higher speed operation is possible. Various semiconductor layers other than the SiGe layer can be used.

In the above-described embodiment, the case where the diffusion suppressing layer is arranged in a plane in the impurity diffusion layer has been described, but the shape of the diffusion suppressing layer is not limited to the planar shape. FIGS. 7A and 7B show other examples of the diffusion suppressing layer. For example, as shown in FIG.
An L-shaped diffusion suppression layer (SiON) 67 may be formed in the source / drain diffusion layer 75 having the ET extension structure. Further, as shown in FIG. 7B, a diffusion suppressing layer (SiON) 68 having a stepped cross section along the bottom surface shape of the source / drain diffusion layer 75 may be formed. Such L-shaped or stair-shaped diffusion suppressing layers 67, 68
Is effective for controlling the shape of the source / drain region 75, and enables the formation of the higher concentration source / drain region 75 which is shallower and has a higher impurity concentration. That is, the diffusion of impurities in the extension region or in the channel direction of the source / drain diffusion layers can be suppressed, so that a high-performance fine device can be manufactured.

In the above-described embodiment, since the description has been made mainly on the MOSFET structure, the present invention is applicable to CMOS, Bi-CMOS, etc. having the MOSFET structure. The effect of this is that a semiconductor structure that needs to form a shallow impurity diffusion layer, a semiconductor structure that needs to control the shape of the impurity diffusion layer itself, or a semiconductor structure that needs to form a higher concentration impurity diffusion layer. Of the present invention can be applied to the semiconductor device. Although the n-type MOSFET has been described, it is of course possible to apply the present invention to a p-type MOSFET.

As described above, the contents of the present invention have been described according to the embodiments, but the present invention is not limited to the above-described embodiments. Obviously, various modifications and improvements, such as substitution of materials and changes in film thickness and manufacturing conditions, are possible.

[0067]

As described above in detail, according to the semiconductor device of the present invention, the semiconductor device having a low resistance and shallow diffusion layer is formed by the effect of the impurity diffusion suppression layer formed in a film shape in the impurity diffusion region. A device can be formed, whereby a high-performance semiconductor device can be realized.

Further, according to the method of manufacturing a semiconductor device of the present invention, the diffusion depth of the impurity in the annealing step is reduced by a more reliable method to a shallower and lower resistance by the effect of the impurity diffusion suppressing layer formed by a simple process. You can control things.

[Brief description of the drawings]

FIG. 1 is a device sectional view showing a MOSFET structure according to an embodiment of the present invention.

FIG. 2 is a graph showing an impurity concentration distribution in a depth direction according to the embodiment of the present invention.

FIG. 3 is a graph showing a result of a simulation of an impurity concentration distribution in a depth direction in the structure according to the embodiment of the present invention;

FIG. 4 is a process chart showing a method for forming a buried diffusion suppressing layer according to an embodiment of the present invention.

FIG. 5 is a process chart showing an example of a method for manufacturing a MOSFET according to the embodiment of the present invention.

FIG. 6 is a device sectional view showing a structure of a MOSFET according to another embodiment of the present invention.

FIG. 7 is an apparatus cross-sectional view showing a structure of a MOSFET according to another embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Semiconductor substrate 11, 13 Si substrate 14, 16 Si layer 15, 17 SiGe layer 20, 25 Gate insulating film 30, 35 Gate electrode 40, 45 Oxide film 50, 55 Side wall insulating film 60 61, 67, 68 Diffusion suppression layer 65 SiON film 70, 75 Source / drain diffusion layer 81 Resist 90 Interlayer insulating film 100 Oxide film 110 Dummy gate electrode 120 Dummy sidewall oxide film

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Shigehiko Saida 8th Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa Prefecture Inside the Toshiba Yokohama Office (72) Inventor Ichiro Mizushima 8th Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa F-term (reference) 5F040 DA00 DC01 EC07 ED03 EF02 EF09 EM04 FA02 FA05 FA10 FB02 FB04 FC05

Claims (19)

[Claims] A first conductivity type semiconductor region; a second conductivity type impurity diffusion region formed in an upper layer in the semiconductor region; and an impurity diffusion suppression layer formed in the impurity diffusion region. A semiconductor device comprising: 2. The semiconductor device according to claim 1, wherein the impurity diffusion suppressing layer has a lower diffusion coefficient than the semiconductor region for impurities in the impurity diffusion region that contribute to the second conductivity type. 3. The semiconductor device according to claim 1. 3. The impurity diffusion region according to claim 1, wherein a concentration distribution in a depth direction of an impurity concentration contributing to the second conductivity type is smaller than a concentration distribution in a depth direction formed by annealing with the impurity diffusion suppression layer as a boundary. 3. The semiconductor device according to claim 1, further comprising a region showing a steep decrease in impurity concentration. 4. The semiconductor according to claim 1, wherein the impurity diffusion suppressing layer has a thickness that does not affect the electric conductivity of the impurity contributing to the second conductivity type. apparatus. 5. The semiconductor region according to claim 1, wherein the semiconductor region is a silicon-based semiconductor, and the impurity diffusion suppressing layer is any one of a silicon oxynitride film, a silicon oxide film, and a silicon nitride film. The semiconductor device according to any one of the above. 6. The impurity diffusion suppressing layer has a thickness of 1 nm.
The semiconductor device according to claim 4, wherein: 7. The semiconductor device according to claim 1, wherein the impurity diffusion region is made of a different semiconductor material between an upper layer and a lower layer with the impurity diffusion suppressing layer as a boundary.
7. The semiconductor device according to any one of 6. 8. The semiconductor device according to claim 7, wherein the upper layer is a SiGe layer, and the lower layer is a Si layer. 9. The semiconductor device according to claim 1, wherein said impurity diffusion region has a MOSFET forming a source / drain region. 10. The semiconductor device according to claim 1, wherein the semiconductor region of the first conductivity type is
Forming an impurity diffusion suppressing layer; forming a first semiconductor layer of a first conductivity type on a main surface including the impurity diffusion suppressing layer; forming a second semiconductor layer on the main surface including the first semiconductor layer; A method for manufacturing a semiconductor device, comprising: a step of adding an impurity contributing to a conductivity type to a region shallower than an impurity diffusion suppression layer; and a step of performing annealing to activate the impurity. 11. The method according to claim 10, wherein the adding step is an ion implantation step. 12. A semiconductor device according to claim 1, wherein the first conductivity type semiconductor region has
A step of forming an impurity diffusion suppressing layer; a step of patterning the impurity diffusion suppressing layer so as to remain in a region where a source / drain region is formed; and a first conductivity type on a main surface including the impurity diffusion suppressing layer. Forming a first semiconductor layer, forming a gate insulating film on the surface of the first semiconductor layer, forming a gate electrode on the gate insulating film, using the gate electrode as a mask, A method for manufacturing a MOSFET, comprising: a step of ion-implanting an impurity contributing to two-conductivity type shallower than the impurity diffusion suppressing layer; and a step of performing annealing for activating the impurity. Method. 13. A semiconductor device according to claim 1, wherein the first conductivity type semiconductor region has
Forming an impurity diffusion suppression layer; forming a first conductivity type first semiconductor layer on a main surface including the impurity diffusion suppression layer; forming one of the impurity diffusion suppression layers in a region to be a channel layer; Part and the layer containing the first semiconductor layer thereon are etched away,
Forming a groove on the bottom surface such that the semiconductor region is exposed; filling the groove with a second semiconductor layer of a first conductivity type; forming a gate insulating film on the second semiconductor layer; Forming a gate electrode on the gate insulating film, using the gate electrode as a mask, implanting an impurity contributing to the second conductivity type shallower than the impurity diffusion suppressing layer, and activating the impurity. A method for manufacturing a MOSFET, the method including a step of performing annealing. 14. The impurity diffusion suppressing layer according to claim 10, wherein a diffusion coefficient of the impurity at the annealing temperature is smaller than that of the semiconductor region.
14. The method for manufacturing a semiconductor device according to any one of 13. 15. The impurity diffusion suppressing layer according to claim 10, wherein the impurity diffusion suppressing layer has a thickness that does not affect the electric conductivity of impurities contributing to the second conductivity type. Of manufacturing a semiconductor device. 16. The semiconductor region according to claim 10, wherein the semiconductor region is a silicon-based semiconductor, and the impurity diffusion suppressing layer is any one of a silicon oxynitride film, a silicon oxide film, and a silicon nitride film. The method for manufacturing a semiconductor device according to any one of the above. 17. The method for manufacturing a semiconductor device according to claim 10, wherein said first semiconductor layer mainly contains the same semiconductor material as said semiconductor region. 18. The semiconductor device according to claim 10, wherein the semiconductor region and the first semiconductor layer are mainly composed of different materials.
17. The method for manufacturing a semiconductor device according to any one of claims to 16. 19. The method according to claim 18, wherein the semiconductor region has Si as a main component, and the first semiconductor layer has SiGe as a main component.