JP4065797B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention relates to a semiconductor device and a manufacturing method thereof. More specifically, the present invention relates to a semiconductor device having a reduced capacitance between a gate electrode and a source / drain region and a method for manufacturing the same.
[0002]
[Prior art]
  In a semiconductor integrated circuit, an insulated gate field effect transistor is often used as a basic element. In recent years, with the progress of miniaturization of semiconductor elements, variations in gate length due to the short channel effect and an increase in leakage current due to deterioration of subthreshold characteristics have become problems.
[0003]
  In order to solve these problems, it is well known that it is effective to reduce the junction depth between the source and drain regions and the semiconductor substrate. However, if the source and drain junctions are simply shallowed, the short channel effect can be suppressed. However, since the resistance values of the source and drain regions (diffusion layers) increase, the parasitic resistance of the transistor increases. Thus, there is a problem that the current driving force is reduced.
[0004]
  Therefore, in order to solve this problem, a structure in which the source and drain regions existing on both sides of the channel region immediately below the gate electrode are stacked above the semiconductor substrate, in other words, provided on both sides of the gate electrode via the gate electrode sidewall insulating film. In addition, a stacked diffusion layer structure for forming source and drain diffusion layers reaching the semiconductor substrate is disclosed in Japanese Patent Laid-Open No. 2000-82815 (Patent Document 1). Thus, by stacking the source and drain regions above the semiconductor substrate, the source and drain diffusion layers can be effectively increased in thickness to reduce the resistance, and the depth of the source and drain junctions can be reduced. It is.
[0005]
  A conventional method for manufacturing a transistor disclosed in Japanese Patent Application Laid-Open No. 2000-82815 will be described with reference to FIGS. 12 and 13 are cross-sectional views in a direction perpendicular to the longitudinal direction of the gate electrode, showing a process for manufacturing a conventional transistor. FIG. 14 is a plan view for explaining a process of removing unnecessary portions of the stacked layer and preventing the source and drain regions from being directly connected in the process from FIG. 12C to FIG. 13A. is there.
[0006]
  First, as shown in FIG. 12A, an element isolation region 502 is provided on a semiconductor substrate 501 by a well-known method, and then a well region 503 having the same conductivity type as that of the semiconductor substrate 501 is formed. Next, a gate insulating film 504, a gate electrode region 505, and a gate electrode sidewall insulating film 507 are formed. Here, the gate electrode region 505 is a polycrystalline silicon film, and a silicon oxide film 506 is formed thereon. The gate electrode side wall insulating film 507 is formed of a silicon oxide film and a silicon nitride film.
[0007]
  Next, as shown in FIG. 12B, a polycrystalline silicon film 508 is deposited by a chemical vapor deposition method (CVD method). When the polycrystalline silicon film 508 is deposited, the polycrystalline silicon film 508 may be deposited by a method that eliminates a natural oxide film as much as possible at the interface between the surface of the well region 503 and the deposited polycrystalline silicon film 508. It becomes important. This is because an impurity which becomes a donor or an acceptor is implanted into the polycrystalline silicon film 508, and then this impurity is solid-phase diffused into the well region 503 by heat treatment. The surface of the active region of the well region 503 and the polycrystalline silicon This is because when a natural oxide film exists at the interface with the film 508, the natural oxide film serves as a barrier for impurity diffusion, and uniform impurity diffusion is hindered and transistor characteristics vary. In order to control this natural oxide film, the polycrystalline silicon film 508 is formed by using a low pressure CVD (LPCVD) apparatus having a preliminary exhaust chamber, a nitrogen purge chamber in which the dew point is always kept at −100 ° C. or less, and a deposition furnace. It is accumulating.
[0008]
  Next, as shown in FIG. 12C, when the polycrystalline silicon film 508 is etched back by anisotropic etching, the polycrystalline silicon film 508 on the silicon oxide film 506 is removed and the gate electrode sidewall insulating film 507 is removed. A side wall 509 made of a polycrystalline silicon film is formed on the side. At this time, the side wall 509 is processed so that the end thereof overlaps the element isolation region 502.
[0009]
  Next, as shown in FIG. 14A, the polysilicon film side wall 509 is formed over the entire periphery of the gate electrode region 505 only by performing the above etch back. In this state, the source and drain are formed. Will directly short and the transistor will not operate normally. Therefore, as shown in FIG. 14B, the source and drain regions are separated by removing the side walls 509 of the unnecessary regions 520 at both ends in the longitudinal direction of the gate electrode region 505.
[0010]
  Next, after removing the silicon oxide film 506 on the gate electrode region 505 shown in FIG. 12C as shown in FIG. 13A, impurity ion implantation and heat treatment for forming the source and drain regions are performed. Done. Thus, the source and drain regions (diffusion layer) 510 and the gate electrode 511 doped with impurities are formed. At this time, the thickness of the polycrystalline silicon film constituting the gate electrode 511 is 200 nm to 250 nm. In ion implantation for an N-channel transistor, phosphorous ions are 1 × 10 with energy of about 20 keV to 80 keV.¹⁵~ 1x10¹⁶/ Cm²Implanted at a moderate dose. In ion implantation for a P-channel transistor, boron ions are 1 × 10 × 1 with an energy of about 10 keV to 40 keV.¹⁵~ 1x10¹⁶/ Cm²Implanted at a moderate dose. The heat treatment after the implantation is performed at a temperature of about 800 ° C. to 950 ° C. for a time of about 10 minutes to 120 minutes. Alternatively, it is performed by a rapid heating process at a temperature of about 950 ° C. to 1100 ° C. for a time of about 10 seconds to 60 seconds.
[0011]
  Of each of the source region 510 and the drain region 510, a portion of the well region 503 that is stacked above the interface between the active region of the well region 503 and the gate insulating film 504 is a stacked diffusion layer 510a.
[0012]
  Next, as shown in FIG. 13B, a refractory metal silicide film 513 is selectively formed on the source region 510, the drain region 510, and the gate electrode 511 by a known salicide process. Next, an interlayer insulating film 514 is formed by a well-known method, and a contact hole 515 is opened at a desired position of the interlayer insulating film 514. Further, although not shown, the upper wiring is formed by a well-known method. It is formed.
[0013]
[Patent Document 1]
          JP 2000-82815 A
[0014]
[Problems to be solved by the invention]
  However, the semiconductor device having the conventional stacked diffusion layer 510a has a capacitance between the gate electrode 511 and the stacked diffusion layer 510a (and thus the gate electrode 511 and the source) as compared with a semiconductor device having no stacked diffusion layer. , The capacitance between the drain region 510 and the drain region 510 becomes large, and there is a problem that the operation speed of the semiconductor device becomes slow.
[0015]
  Therefore, an object of the present invention is to provide a high-speed semiconductor device and a manufacturing method by reducing the capacitance between the stacked diffusion layer and the gate electrode.
[0016]
[Means for Solving the Problems]
  In order to solve the above problems, a semiconductor device of the present invention is
  A semiconductor substrate, a gate insulating film provided on the active region of the semiconductor substrate, a gate electrode provided on the gate insulating film, and a source region and a drain region located on both sides of the gate electrode, In each of the source region and the drain region, in the semiconductor device made of a conductor stacked above the interface between the active region and the gate insulating film,
  An insulator is provided between the conductor and the gate electrode,
  A part of the insulator protrudes upward from the gate electrode,
  A cavity is formed between the other part of the insulator and the gate electrode,
  The distance between the part of the insulator protruding upward from the gate electrode and the extended surface of the side surface of the gate electrode is the distance between the other part of the insulator and the side surface of the gate electrode. Less than the distance betweenIt is characterized by that.
[0017]
  According to the above configuration, the aboveOther parts of insulatorSince a cavity with a relative dielectric constant of 1 is present between the gate electrode and the gate electrode, the capacitance between the stacked conductor and the gate electrode can be reduced. Accordingly, the capacitance between the source and drain regions and the gate electrode is reduced, and a high-speed semiconductor device can be obtained.
[0018]
[0019]
  the aboveConstitutionAccording to the above, since the insulator is provided between the stacked conductor and the gate electrode in addition to the cavity having a relative dielectric constant of 1 and small, the capacitance between the two can be reduced, The insulation between them can be kept good.
[0020]
[0021]
  the aboveConstitutionSince the effective distance between the gate electrode and the stacked conductors is long, the insulation between the two can be kept good. In addition, since the insulator protrudes above the gate electrode, the cavity can be easily formed.Also, a cavity is formed between the gate electrode and the insulator, and the distance between the gate electrode and the insulator is narrow at the top and wide at the bottom. can do.
[0022]
  Moreover, in one embodiment, a part of the insulator protrudes upward from the conductor.
[0023]
  According to the above embodiment, since the effective distance between the gate electrode and the stacked conductors is long, the insulation between them can be kept good. Further, since the insulator protrudes upward from the conductor, the cavity can be easily formed.
[0024]
[0025]
[0026]
  In one embodiment, a refractory metal silicide film is provided on the side wall of the gate electrode facing the cavity.
[0027]
  According to the embodiment, since the refractory metal silicide film is provided on the side wall of the gate electrode by utilizing the existence of the cavity, the resistance of the gate electrode can be reduced.
[0028]
  In addition, a method for manufacturing a semiconductor device of the present invention includes
  Sequentially depositing a gate insulating film, a gate electrode, and an insulating film on a semiconductor substrate;
  Patterning the insulating film and the gate electrode;
  Forming a gate electrode sidewall insulating film in contact with the gate electrode sidewall;
  Depositing a conductive film on the semiconductor substrate;
  Etching until the conductive film on the gate electrode disappears to form a stacked conductor in contact with the gate electrode sidewall insulating film; and
  Gate electrode side wall insulating filmOneEtching the part to form a cavity region;
  Depositing an interlayer insulating film under conditions such that the cavity region becomes a cavity;
With,
  The step of forming the gate electrode sidewall insulating film includes a first gate electrode sidewall insulating film and a second gate electrode insulating film. A step of sequentially forming gate electrode sidewall insulating films,
The step of forming the cavity region is a step of etching either the first gate electrode sidewall insulating film or the second gate electrode sidewall insulating film,
  After the step of patterning the insulating film and the gate electrode, and before the step of sequentially forming the first gate electrode sidewall insulating film and the second gate electrode sidewall insulating film, the width of the insulating film is A step of making the width smaller than the width of the gate electrodeIt is characterized by that.
[0029]
  According to the above invention, a semiconductor device having a cavity between the gate electrode and the stacked conductor can be easily and inexpensively manufactured without using a special process device.
[0030]
[0031]
  the aboveinventionAccordingly, a semiconductor device having a cavity and an insulating film between the gate electrode and the stacked conductor can be easily and inexpensively manufactured without using a special process device.According to the invention, since the width of the insulating film is smaller than the width of the gate electrode, the upper portion of the second gate electrode sidewall insulating film is formed on the gate electrode in accordance with the insulating film having a small width. It is possible to easily narrow the hollow area, that is, the opening width of the recess, by bending the side. As described above, since the opening width of the upper part of the cavity can be reduced, when the interlayer insulating film is deposited, the interlayer insulating film is not mixed in the cavity region, that is, the depression. Can be formed.
[0032]
  In one embodiment, the first gate electrode sidewall insulating film is a silicon oxide film, the second gate electrode sidewall insulating film is a silicon nitride film, and the step of forming the cavity region includes This is a step of etching the silicon oxide film.
[0033]
  According to the above embodiment, a semiconductor device having an insulator made of the cavity and the silicon nitride film between the gate electrode and the stacked conductor can be simply and without using a special process device. It can be manufactured at low cost.
[0034]
[0035]
[0036]
  In one embodiment, the step of making the width of the insulating film smaller than the width of the gate electrode is a step of heat-treating the insulating film at 700 ° C. to 900 ° C.
[0037]
  According to the above embodiment, since heat treatment is used to narrow the width of the insulating film, a normal process apparatus can be used and the width of the insulating film can be reduced with good reproducibility. Further, since the heat treatment is performed at 700 ° C. or higher, the throughput is not lowered and the heat treatment is performed at 900 ° C. or lower, so that the depth of the well region and the impurity concentration are not affected.
[0038]
DETAILED DESCRIPTION OF THE INVENTION
  (Reference example 1)
  BookReference example 1In this semiconductor device, a cavity is formed between the gate electrode and the stacked conductors that are part of the source and drain regions, so that the capacity of both is remarkably reduced.
[0039]
  BookReference example 1The semiconductor device will be described with reference to FIGS. Figure 1 (a) shows the bookReference example 1FIG. 1B is a cross-sectional view taken along the line A-A ′ in FIG. In FIG. 1A, the interlayer insulating film 114 and the refractory silicide film 112 are omitted in order to clarify the position of the cavity 113 and the positional relationship between the contact hole 115 and the gate electrode 111. 2 and 3 show the bookReference example 1It is a figure explaining the procedure which creates this semiconductor device.
[0040]
  As shown in FIGS.Reference example 1The semiconductor device of FIG. 1 is a MIS (metal-insulator-semiconductor) type semiconductor element formed on the active region 120 in a semiconductor substrate 101 roughly divided into an element isolation region 102 and an active region 120. It is. This semiconductor device includes an element isolation region 102, a well region 103, a gate insulating film 104, a source region 110, a drain region 110, and a gate electrode 111.
[0041]
  The source region 110 and the drain region 110 are adjacent to the gate electrode 111. Most portions 110a of each of the source region 110 and the drain region 110 are stacked diffusion layers 110a located above the interface between the gate insulating film 104 and the well region 103, and are examples of stacked conductors. is there. Therefore, since the MIS type semiconductor element has a structure in which the parasitic resistance of the transistor is small due to the presence of the stacked diffusion layer 110a, the operation speed of the semiconductor element can be improved. In addition, since the shallow diffusion can be easily formed by the existence of the stacked diffusion layer 110a, a fine semiconductor element can be formed while suppressing the short channel effect. Furthermore, since the refractory metal silicide film 112 and the PN junction of the source / drain region (diffusion layer region) 110 are sufficiently separated from each other, a semiconductor element having a small junction leakage current can be realized.
[0042]
  A cavity 113 is formed between the gate electrode 111 and the stacked diffusion layer 110a. The stacked diffusion layer 110a is formed of a semiconductor film. As shown in FIG. 1A, the cavity 113 is formed in a region where the gate electrode 111 and the stacked diffusion layer 110a face each other.
[0043]
  A refractory metal silicide film 112 is formed on the gate electrode 111 and the source / drain regions 110, an interlayer insulating film 114 is formed, and a contact hole 115 is formed at a desired position of the interlayer insulating film 114. ing. The upper wiring is omitted because it is the same as a general transistor.
[0044]
  With the above configuration, this bookReference example 1In this semiconductor device, since the cavity 113 is formed between the gate electrode 111 and the stacked diffusion layer 110a of the source / drain regions 110, the capacitance between them can be reduced. Therefore, the speed of the semiconductor device can be improved and the power consumption can be reduced.
[0045]
  Here, the effect of reducing the capacitance between the gate electrode 111 and the source / drain region 110 will be described. In the transistor having the structure in which the source and drain regions 510 are stacked as in the conventional semiconductor device shown in FIG. 13, the gate electrode 511 and the source are compared with a normal transistor having no stacked diffusion layer 510a due to the structure. Since the area facing the drain region 510 is increased, the capacitance between the two is increased. In addition, in order to suppress the short channel effect, it is necessary to make the junction shallower as the transistor becomes finer, but the gate electrode sidewall insulating film prevents the transistor from being offset and dropping the driving force even if the junction is shallow. Since the width of 507 is reduced, the capacitance between the gate electrode 511 and the source / drain region 510 is further increased. For this reason, in a transistor having a structure in which the source and drain regions 510 are stacked, reducing the capacitance is a very important issue.
[0046]
  BookReference example 1This semiconductor device solves the above problems by providing a cavity 113 to reduce the capacity, and includes a very important technical idea.
[0047]
  BookReference example 1In this semiconductor device, a 211-stage ring oscillator circuit was created and the circuit speed was evaluated. As a result, the speed was improved by about 8% compared to the conventional example. In the conventional example shown in FIG. 13, a silicon nitride film having a relative dielectric constant ε of 6 is used for the gate electrode sidewall insulating film 507.Reference example 1In this semiconductor device, the region of the gate electrode side wall insulating film forms a cavity 113, that is, a vacuum in which the relative dielectric constant ε is 1. For this reason, the capacity of the ring oscillator circuit is reduced and the speed is improved.
[0048]
  Further, by providing the cavity 113, stress due to the stacked diffusion layer 110a and the refractory silicide film 112 in the source and drain regions 110 can be relieved, so that the carrier mobility of the transistor due to the stress is not deteriorated. . The reason for this will be described below.
[0049]
  When the gate sidewall insulating film 507 is formed between the gate electrode 511 and the stacked diffusion layer 510a of the source / drain region 510 as in the conventional example shown in FIG. 13, the stacked diffusion layer 510a and the refractory metal silicide are formed. The stress generated by the film 513 is transmitted to the gate electrode 511 through the gate electrode sidewall insulating film 507, and as a result, the stress is deteriorated so that the mobility of carriers in the channel (near the surface of the well region 503 directly under the gate electrode 511) is deteriorated. Worked. Contrary to this, the bookReference example 1In this semiconductor device, since the cavity 113 absorbs the stress generated in the source / drain region 110, the deterioration of carrier mobility can be prevented. Therefore, the semiconductor device can maintain its original performance without reducing the driving force, and can operate at high speed.
[0050]
  Then bookReference example 1A procedure for forming the semiconductor device will be described with reference to FIGS.
[0051]
  First, as shown in FIG. 2A, an element isolation region 102 is provided in a semiconductor substrate 101 made of, for example, a silicon substrate by a well-known method, and then a well region 103 is formed in the semiconductor substrate 101. Next, a gate insulating film 104, a polycrystalline silicon film (hereinafter referred to as a gate electrode region) 105 to be a gate electrode, and a gate electrode sidewall insulating film 107 are formed. Here, a silicon oxide film 106 is formed on the gate electrode region 105. Although not shown, the gate electrode sidewall insulating film 107 is formed of a silicon oxide film on the gate electrode region 105 side and the bottom, and a silicon nitride film which is the other part, and the silicon oxide film and the silicon nitride film The film thickness of each is 3 to 10 nm and 30 to 60 nm.
[0052]
  Next, as shown in FIG. 2B, after the polycrystalline silicon film is deposited on the entire surface by LPCVD (low pressure chemical vapor deposition), the polycrystalline silicon film above the gate electrode region 105 disappears. By performing anisotropic etching back to the end, the sidewall 109 of the polycrystalline silicon film is formed. At this time, the polycrystalline silicon film was deposited by the same method as described in the conventional example in which a natural oxide film does not grow at the interface with the semiconductor substrate 101.
[0053]
  Then bookReference example 1Although not shown, the source region and the drain region are directly short-circuited by the side wall 109 of the polycrystalline silicon film formed over the entire periphery of the gate electrode region 105 as described with reference to FIG. In order to prevent this, the side walls 109 of unnecessary regions at both ends in the longitudinal direction of the gate electrode region 105 are removed to separate the source and drain regions.
[0054]
  Next, after the silicon oxide film 106 on the gate electrode region 105 shown in FIG. 2B is removed as shown in FIG. 2C, portions that become the gate electrode 111, the source region 110, and the drain region 110 are removed. That is, an impurity which becomes a donor or an acceptor is simultaneously introduced into the gate electrode region 105 and the sidewall 109 by ion implantation. The ion implantation at this time is 1 × 10 with an energy of about 20 keV to 80 keV for adjacent ions in the N channel transistor.¹⁵/ Cm²~ 1x10¹⁶/ Cm²For a P-channel transistor with a dose of about 1 × 10 5 with an energy of about 5 keV to 30 keV.¹⁵/ Cm²~ 1x10¹⁶/ Cm²It was performed at a dose amount of about. Next, after the ion implantation, a heat treatment is performed at a temperature of about 800 ° C. to 950 ° C. for about 5 minutes to 120 minutes, or a rapid heat treatment at a temperature of about 950 ° C. to 1100 ° C. for about 5 seconds to 60 seconds. The activated impurities are activated and diffused to the well region 103 of the semiconductor substrate 101, whereby the activated gate electrode 111, source region 110, and drain region 110 are formed.
[0055]
  Next, as shown in FIG. 3A, a refractory metal silicide film 112 is selectively formed on the source region 110, the drain region 110 and the gate electrode 110 by a known salicide process, and then hot phosphoric acid is used. Thus, most of the silicon nitride film of the gate electrode sidewall insulating film 107 is removed leaving a part of the silicon nitride film 107 ′ at the bottom. Although not shown, a thin silicon oxide film of the gate electrode sidewall insulating film 107 is formed to a thickness of 3 to 10 nm on the sidewall portion of the gate electrode 111 and the surface of the well region 103. Yes. For this reason, even if the etching is performed until the portion 107 ′ of the silicon nitride film to be left is completely removed, phosphoric acid does not directly contact silicon, so that surface roughness does not occur and the characteristics are deteriorated. It will not be. On the other hand, since there is no silicon oxide film on the side surface of the side wall 110a of the polycrystalline silicon film forming the stacked diffusion layer 110a of the source region 110 and the drain region 110, it is slightly etched by phosphoric acid. It is not a problem because it is not an influential area.
[0056]
  BookReference example 1Then, hot phosphoric acid was used to remove the silicon nitride film, but the present invention is not limited to this, and other wet etching or dry etching having high selectivity with respect to the refractory metal silicide film 112 and the silicon oxide film 102 is used. May be used.
[0057]
  Here, in the case of forming a titanium silicide film, the well-known salicide process is titanium deposition → first heat treatment (600 to 700 ° C.) → selective etching (removal of unreacted refractory metal) → second heat treatment. However, the step of removing the gate electrode sidewall insulating film 107 may be performed after the selective etching and before the second heat treatment. In this case, the gate electrode sidewall insulating film 107 does not exist at the time of the second high-temperature heat treatment, that is, when the refractory silicide film 112 is phase-shifted from the high-resistance crystal phase to the low-resistance crystal phase. Therefore, the stress at the phase transition can be relaxed. Therefore, the refractory metal silicide film 112 can be formed with good controllability even on the fine gate electrode 111 where it is difficult to form the refractory metal silicide film 112.
[0058]
  Next, as shown in FIG. 3B, an interlayer insulating film 114 is deposited. As a result, a cavity 113 is formed in a recess between the stacked diffusion layer 110 a of the source / drain region 110 and the gate electrode 111. The cavity 113 has a very large aspect ratio of 50 nm in width and 250 nm in depth. Therefore, the cavity 113 cannot be embedded by a plasma CVD method, which is a normal method for depositing the interlayer insulating film 114. Here, by forming the interlayer insulating film 114 at a pressure of 100 Pa or more with monosilane and oxygen by a method having a step coverage lower than that of the normal plasma CVD method, for example, atmospheric pressure CVD method or plasma CVD method, The cavity 113 can be obtained stably. Although not shown, the interlayer insulating film may be deposited by a method having a good step coverage after the interlayer insulating film is deposited by the above-described method having a poor step coverage for about 50 nm to 300 nm. In that case, there is an advantage that a step on the surface of the interlayer insulating film 114 can be reduced while the cavity 113 is formed with good controllability.
[0059]
  Thereafter, a contact hole 115 is formed at a desired position of the interlayer insulating film 114. Although not shown, the upper wiring is formed by a well-known method,Reference example 1This completes the semiconductor device.
[0060]
  As above, the bookReference example 1According to this manufacturing method, the cavity 113 can be formed with good controllability between the gate electrode 111 and the stacked diffusion layer 110a which is a conductor of the source / drain region 110 without using a special process.
[0061]
  (Reference example 2)
  BookReference example 2The semiconductor deviceReference example 1Similarly to the above, by forming a cavity between the gate electrode and the stacked diffusion layers of the source and drain regions, the capacitance combined with both is remarkably reduced. In addition to this, a structure in which the electrical isolation between the gate electrode and the source / drain region is improved, and a structure in which a cavity is easily formed between the gate electrode and the stacked diffusion layer of the source / drain region. Is to provide.
[0062]
  BookReference example 2The semiconductor device will be described with reference to FIGS. Figure 4 shows the bookReference example 22 shows a cross section of the semiconductor device taken perpendicularly to the longitudinal direction of the gate electrode 211. 5-7 show the bookReference example 2The procedure for producing the semiconductor device will be described.
[0063]
  First, using FIG.Reference example 2The configuration of the semiconductor device will be described.
[0064]
  BookReference example 2This semiconductor device is a MIS type semiconductor element formed on the active region in a semiconductor substrate 201 roughly divided into an element isolation region 202 and an active region. The semiconductor device includes an element isolation region 202, a well region 203, a gate insulating film 204, a source region 210, a drain region 210, and a gate electrode 211.
[0065]
  The source region 210 and the drain region 210 are adjacent to the gate electrode 211. The stacked diffusion layer 210 a, which is the most part of each of the source region 210 and the drain region 210, is located above the interface between the gate insulating film 204 and the well region 203. The stacked diffusion layer 210a is an example of a conductor. Between the stacked diffusion layer 210a and the gate electrode 211, there are a cavity 212, a gate electrode sidewall insulating film 208 and an insulating film 207 'as insulators. The cavity 212 is between the gate electrode 211 and the gate electrode sidewall insulating film 208, and the insulating film 207 ′ is disposed under the cavity 207 ′ and the gate electrode sidewall insulating film 208. The gate electrode sidewall insulating film 208 protrudes above the gate electrode 211 and the source / drain regions 210. The area where the cavity 212 is formed is shown in FIG.Reference example 1Similarly to the semiconductor device of FIG. 2, the gate electrode 211 and the source / drain region 210 are opposed to each other, and thus are not shown here.
[0066]
  According to the above configuration, the presence of the cavity 212 can reduce the capacitance between the gate electrode 211 and the source / drain region 210. Therefore, the operation speed of the semiconductor device can be improved and the power consumption can be reduced. Also,Reference example 1Unlike the gate electrode 211 and the stacked diffusion layer 210a of the source / drain region 210, the gate electrode sidewall insulating film 208 exists, so that the gate electrode 211 and the source / drain region 210 can be reliably insulated. . Further, since the gate electrode sidewall insulating film 208 protrudes above the gate electrode 211 and the source / drain regions 210, the cavity 212 is easily formed when the interlayer insulating film 214 is deposited.
[0067]
  The gate electrode sidewall insulating film 208 and the insulating film 207 ′ may be any insulating film, but thisReference example 2Then, the gate electrode sidewall insulating film 208 is a silicon nitride film, and the insulating film 207 'is a silicon oxide film. In this case, the element isolation region 202 and the silicon oxide film 207 are silicon oxide films. Since the silicon nitride film 208 is formed on these, the element isolation region 202 and the silicon oxide film 207 are formed when cleaning with hydrofluoric acid or the like. The silicon oxide film 207 is not etched to reduce the film thickness. Therefore, characteristic deterioration such as a short circuit between elements (between the source region 210 and the drain region 210) can be prevented. Since the silicon nitride film 208 on the element isolation region 202 functions as an etching stopper when forming the contact hole 215, the silicon oxide film 207 in the element isolation region 202 penetrates into the well region 203 during contact etching. It will not cause deterioration of characteristics.
[0068]
  A refractory metal silicide film 213 is formed on the gate electrode 211 and the source / drain regions 210, an interlayer insulating film 214 is formed, and a contact hole 215 is formed at a desired position of the interlayer insulating film 214. Yes. The upper wiring is omitted because it is the same as a general transistor.
[0069]
  Then bookReference example 2A procedure for forming the semiconductor device will be described with reference to FIGS.
[0070]
  First, as shown in FIG. 5A, an element isolation region 202 is provided in a semiconductor substrate 201 by a well-known method, and then a well region 203 is formed in the semiconductor substrate 201. Next, a gate insulating film 204, a polycrystalline silicon film 205 to be a gate electrode, and a silicon oxide film 206 are sequentially formed on the semiconductor substrate 201. Next, after patterning the silicon oxide film 206 by a known lithography and etching technique, the polycrystalline silicon film 205 is patterned using the silicon oxide film 206 as a mask to form a gate electrode region 205. Although not shown, a silicon oxide film having a thickness of 2 to 10 nm may be formed on the side wall of the gate electrode region 205 and the surface of the well region 203 by thermal oxidation.
[0071]
  Next, as shown in FIG. 5B, a silicon oxide film 207 and a silicon nitride film 208 are deposited to a thickness of 10 to 30 nm and 20 to 50 nm, respectively, by a normal CVD method.
[0072]
  Next, as shown in FIG. 5C, a silicon oxide film as an example of the first gate electrode sidewall insulating film while leaving the silicon nitride film 208 on the element isolation region 202 by a known lithography and etching technique. A gate electrode sidewall insulating film composed of 207 and a silicon nitride film 208 as an example of the second gate electrode sidewall insulating film is formed.
[0073]
  Next, as shown in FIG. 6A, after the polycrystalline silicon film is deposited on the entire surface by the LPCVD method, anisotropic etching back is performed until the deposited polycrystalline silicon film above the gate electrode region 205 disappears. As a result, a sidewall 209 of a polycrystalline silicon film is formed. At this time, the polycrystalline silicon film 209 was deposited by the same method described in the conventional example in which a natural oxide film does not grow on the interface with the semiconductor substrate 2201.
[0074]
  Next, the silicon oxide film 206 (see FIGS. 5C and 6A) on the gate electrode region 205 is removed. At this time, the silicon oxide film 207 of the gate electrode side wall insulating film is also removed to the vicinity of the upper portion of the gate electrode 205 at the same time. While the silicon oxide film 206 may be removed, a recess that becomes a cavity may be formed. However, when impurity ions are implanted into the source, drain region, and gate electrode region 205, the impurity ions implanted into the recess region are wells. Since there is a high risk that the junction depth of the source and drain regions will be deepened by implantation up to the deep region of the region 203, it is desirable that the formation of the recess be performed after the impurity ion implantation is completed.
[0075]
  Then bookReference example 2Although not shown in the figure, as described with reference to FIG. 14 in the conventional example, the source region and the drain region are directly connected by the sidewall 209 of the polycrystalline silicon film formed over the entire periphery of the gate electrode region 205. In order to prevent short-circuit, the source and drain regions are separated by removing the unnecessary side walls 209 at both ends in the longitudinal direction of the gate electrode region 205.
[0076]
  Next, a portion that becomes the gate electrode 211, the source region 210, and the drain region 210 illustrated in FIG. 6B, that is, the gate electrode region 205 and the sidefalls 209 and 209 illustrated in FIG. The impurity to be formed is simultaneously introduced by ion implantation, and then a desired heat treatment is performed. Thereby, the gate electrode 211, the source region 210, and the drain region 210 are formed, respectively. The ion implantation conditions and heat treatment conditions at this time are as follows:Reference example 1Since it is the same as the conditions described in, it is omitted here.
[0077]
  Next, as shown in FIG. 6C, a part of the silicon oxide film 207 on the side wall portion of the gate electrode 211 is removed to form a hollow, that is, a cavity region that will later become a cavity. At this time, the silicon oxide film 207 ′ remains below the depression and the silicon nitride film 208.
[0078]
  Next, as shown in FIG. 7A, a refractory metal silicide film 213 is selectively formed on the source region 210, the drain region 210, and the gate electrode 211 by a known salicide process. Here, in the known salicide process, a refractory metal film is generally deposited by physical sputtering, but the step coverage is very poor, so that the refractory metal silicide film is not formed on the sidewall of the gate electrode 211. However, if the CVD method is used, a refractory metal silicide film can be formed also on the side wall of the gate electrode 211. For example, in the case of titanium, a refractory metal silicide film can be formed on the side wall of the gate electrode 211 by thermal CVD using titanium tetrachloride and hydrogen. Thus, when the refractory metal silicide film 213 is formed also on the side wall of the gate electrode 211, the resistance of the gate electrode 211 can be reduced. Further, it is possible to obtain a refractory metal silicide film that hardly aggregates even when the gate length is reduced.
[0079]
  Next, as shown in FIG. 7B, an interlayer insulating film 214 is deposited. As a result, a cavity 212 is formed in a recess between the gate electrode 211 and the gate electrode sidewall insulating film 208. The cavity 212 is formed because the recess has a very large aspect ratio of 10 to 30 nm in width and 250 nm in depth, and cannot be filled by the plasma CVD method for depositing a normal interlayer insulating film 214. here,Reference example 1Similarly, by forming the interlayer insulating film 214 at a pressure of 100 Pa or more with monosilane and oxygen by a method having poor step coverage than the normal plasma CVD method, for example, atmospheric pressure CVD method or plasma CVD method, The cavity 212 can be obtained more stably. Although not shown, the insulating film with poor step coverage may be deposited after the above-described insulating film with poor step coverage is deposited by about 50 nm to 300 nm. In that case, there is an advantage that a step on the surface of the interlayer insulating film 215 can be reduced while the cavity 212 is formed with good controllability.
[0080]
  Next, a contact hole 215 is formed at a desired position of the interlayer insulating film 214. Although not shown, the upper wiring is formed by a well-known method,Reference example 2This completes the semiconductor device.
[0081]
  BookReference example 2In the semiconductor device ofReference example 1Compared with this semiconductor device, the silicon nitride film 208 protrudes above the stacked diffusion layer 210a of the gate electrode 211 and the source / drain regions 210, that is, the interlayer insulating film 214 is difficult to be deposited in the depression. Therefore, the cavity 212 can be formed with good controllability. Further, since the silicon nitride film 208 protrudes above the gate electrode 211 and the stacked diffusion layer 210 a of the source / drain region 210, it is between the gate electrode 211 and the stacked diffusion layer 210 a of the source / drain region 210. The effective distance is increased and the insulation between the gate electrode 211 and the source / drain region 210 is improved.
[0082]
  As above, the bookReference example 2Then, the cavity 212 can be formed with good controllability in the recess between the gate electrode 211 and the second gate electrode sidewall insulating film 208 without using a special process.
[0083]
  (Reference example 3)
  Book shown in FIG.Reference example 3This semiconductor device uses an SOI (Silicon On Insulator) substrate,Reference example 2Unlike other semiconductor devices, other points areReference example 2It is the same. Therefore, in FIG. 8, shown in FIG.Reference example 2The same reference numerals are assigned to the same components, and detailed description thereof is omitted.
[0084]
  As shown in FIG. 8, a buried silicon oxide film 220 is formed between the semiconductor substrate 201 and the element isolation region 202 and well region 203 (body). The junction depth of the source / drain region 210 is made thicker than the thickness of the well region 203. Therefore,Reference example 2In addition to the effects of the semiconductor device, the capacity of the junction can be reduced. Further, the presence of the buried silicon oxide film 220 can reduce the leakage current of the semiconductor element.
[0085]
  In a normal SOI substrate, although not shown, a refractory metal silicide film is formed directly on the body. For this reason, when the semiconductor element is miniaturized and the thickness of the body becomes thin, the refractory metal silicide film consumes all of the silicon in the body and reaches the buried silicon oxide film, causing a defect. Contrary to this, the bookReference example 3In this semiconductor device, since the refractory metal silicide film 213 is formed on the stacked diffusion layer 210 a in the source / drain region 210, the refractory metal silicide film 213 does not reach the buried silicon oxide film 220. Therefore, defects can be prevented.
[0086]
  BookReference example 3In this semiconductor device, the case where it is formed on a fully depleted SOI substrate has been described. However, the present invention is not limited to this, and it may be formed on a partially depleted SOI substrate. Also on the SOI substrateReference example 2Although the case where the semiconductor device is formed is described, since the same effect can be obtained, the semiconductor device is formed on the SOI substrate.Reference example 1The semiconductor device may be formed.
[0087]
  (Embodiment 1)
  less than,Embodiment 1A procedure for manufacturing the semiconductor device will be described with reference to FIGS.
[0088]
  First, as shown in FIG. 9A, an element isolation region 302 is provided in a semiconductor substrate 301 by a well-known method, and then a well region 303 is formed in the semiconductor substrate 301. Next, a gate insulating film 304, a polycrystalline silicon film 305 to be a gate electrode, and a silicon oxide film 306 as an example of an insulating film are sequentially formed. Here, the silicon oxide film 306 was deposited at a temperature of 400 ° C. by a CVD method. The deposition temperature is preferably 400 ° C., but may be 700 ° C. or less. Next, after patterning the silicon oxide film 306 by a known lithography and etching technique, the polycrystalline silicon film 305 is patterned using the silicon oxide film 306 as a mask to form a gate electrode region 305. Next, heat treatment at 700 ° C. to 900 ° C. is performed to reduce the width of the silicon oxide film 306 that is an insulating film by about 10 to 30 nm on one side due to film shrinkage. This is because the film density of the silicon oxide film 306 formed at a low temperature of 400 ° C. is small, and therefore, a phenomenon that the film shrinks when heat-treated at a high temperature of 700 ° C. to 900 ° C. is used. If the heat treatment temperature for shrinking the silicon oxide film 306 is 700 ° C. or less, it takes time to shrink the silicon oxide film 306 to a desired width, resulting in a decrease in throughput. On the other hand, when the temperature is 900 ° C. or higher, the depth of the well region 303 is increased or the surface concentration of the well region 303 is decreased, and the well region 303 having a desired concentration and depth cannot be obtained. For this reason, heat processing temperature is performed at 700 to 900 degreeC.
[0089]
  Although not shown, a silicon oxide film having a thickness of 2 to 10 nm may be formed on the surfaces of the gate electrode region 305 and the well region 303 made of a polycrystalline silicon film by thermal oxidation. Further, this thermal oxidation treatment may be combined with a heat treatment for reducing the width of the silicon oxide film 306.
[0090]
  Next, as shown in FIG. 9B, a silicon oxide film 307 and a silicon nitride film 308, which is an example of an insulator, are sequentially deposited by a normal CVD method to about 10 to 30 nm and 20 to 50 nm, respectively. To do.
[0091]
  Next, as shown in FIG. 9C, silicon oxide as an example of the first gate electrode side wall insulating film is left while the silicon nitride film 308 is left on the element isolation region 302 by a known lithography and etching technique. A gate electrode sidewall insulating film including a film 307 and a silicon nitride film 308 as an example of a second gate electrode sidewall insulating film is formed.
[0092]
  Next, as shown in FIG. 10A, after the polycrystalline silicon film is deposited on the entire surface by LPCVD, anisotropic etching back is performed until the portion of the polycrystalline silicon film above the gate electrode region 305 disappears. As a result, sidewalls 309 of the polycrystalline silicon film are formed. At this time, the polycrystalline silicon film was deposited by the same method described in the conventional example in which a natural oxide film does not grow at the interface with the semiconductor substrate 301.
[0093]
  Next, the silicon oxide film 306 (see FIG. 9C) is removed as shown in FIG. At this time, the silicon oxide film 307 as the first gate electrode sidewall insulating film is also removed to the vicinity of the upper portion of the gate electrode region 305 at the same time. While the silicon oxide film 306 is removed, a hollow that becomes a cavity may be formed at the same time. However, when impurity ions are implanted into the source, drain region, and gate electrode region, the impurity ions implanted into the hollow region are wells. Since there is a high risk that the junction depth of the source and drain will be deepened by implantation up to the deep region of the region 303, it is desirable that the formation of the recess be performed after the impurity ion implantation is completed.
[0094]
  Then bookEmbodiment 1Although not shown, the source and drain are directly shorted by the side wall 309 of the polycrystalline silicon film formed over the entire periphery of the gate electrode region 305 as described with reference to FIG. 14 in the conventional example. In order to prevent this, the side wall 309 of the unnecessary region at both ends in the longitudinal direction of the gate electrode region 305 is removed to separate the source and drain regions.
[0095]
  Next, an impurity which becomes a donor or an acceptor is simultaneously introduced into the gate electrode region 305 and the sidewall 309 shown in FIG. 10A by ion implantation, and then a desired heat treatment is performed. Thereby, the gate electrode 311 and the source / drain regions 310 are formed. The ion implantation conditions and heat treatment conditions at this time are as follows:Reference example 1Since the conditions are the same as those described in 2 and 2, they are omitted here.
[0096]
  Next, as shown in FIG. 10C, a part of the silicon oxide film 307 that is in contact with the side surface of the gate electrode 311 is removed to form a cavity region, that is, a recess that will later become a cavity. At this time, the silicon oxide film 307 ′ remains under the depression and the silicon nitride film 308. Further, due to the film shrinkage of the silicon oxide film 306, the width of the silicon oxide film 306 is smaller than the width of the gate electrode 311. Therefore, the upper portion of the silicon nitride film 308 is bent toward the gate electrode 311. ing. Therefore, the distance between the part of the silicon nitride film 308 protruding upward from the gate electrode 311 and the extended surface of the side surface of the gate electrode 311 is such that the lower part of the silicon nitride film 308 and the gate electrode 311 It is smaller than the distance between the sides.
[0097]
  Next, as shown in FIG. 11A, a refractory metal silicide film 313 is selectively formed on the source region 310, the drain region 310, and the gate electrode 311 by a well-known salicide process. here,Reference example 2As described above, a refractory metal silicide film may be formed on the side wall of the gate electrode 311 by using the CVD method.
[0098]
  Next, as shown in FIG. 11B, an interlayer insulating film 314 is deposited. As a result, a cavity 312 is formed in the recess between the gate electrode 311 and the silicon nitride film 308 as the second gate electrode sidewall insulating film. BookEmbodiment 1ThenReference example 2In contrast, the silicon nitride film 308 as the second gate electrode side wall insulating film protrudes in the direction of the gate electrode 311 at the entrance portion at the upper part of the depression to serve as a cap, and the interlayer insulating film 314 is deposited. It has a difficult shape. Therefore, the cavity 312 can be formed with good controllability. here,Reference example 1As in (2) and (2), by forming the interlayer insulating film 314 with monosilane and oxygen at a pressure of 100 Pa or higher by a method having a step coverage lower than that of the normal plasma CVD method, for example, atmospheric pressure CVD method or plasma CVD method. The cavity 312 can be obtained more stably. Although not shown, the insulating film with poor step coverage may be deposited after the above-described insulating film with poor step coverage is deposited by about 50 nm to 300 nm. In that case, there is an advantage that the step of the interlayer insulating film 314 can be reduced while the cavity 312 is formed with good controllability.
[0099]
  Thereafter, contact holes 315 are formed at desired positions of the interlayer insulating film 314. Although not shown, the upper wiring is formed by a well-known method,Embodiment 1This completes the semiconductor device.
[0100]
  As above, the bookEmbodiment 1Then, the cavity 312 can be formed with good controllability in the recess between the gate electrode 311 and the silicon nitride film 308 without using a special process.
[0101]
  the aboveReference example 24 to 4, the cavities 212 and 312 are provided between the gate electrodes 211 and 311 and the silicon nitride films 208 and 308 as insulators. The insulators are in contact with the side walls of the gate electrodes and stacked with the insulators. A cavity may be provided between the diffusion layer.
[0102]
【The invention's effect】
  As is apparent from the above, according to the semiconductor device of the present invention, a cavity having a small relative dielectric constant of 1 is provided between the stacked conductors that are part of the source region and the drain region and the gate electrode. Therefore, the capacity between the stacked conductor and the gate electrode can be reduced, and the capacity of the source and drain regions and the gate electrode can be reduced. Therefore, a high-speed semiconductor device can be obtained.
[0103]
  In addition, according to the method for manufacturing a semiconductor device of the present invention, without using a special process device, using a generally widely used process device, between the gate electrode and the stacked conductors, Since the cavity is formed, a capital investment of a new process apparatus is unnecessary, and a semiconductor device having a cavity can be manufactured easily and inexpensively.
[Brief description of the drawings]
FIGS. 1 (a) and 1 (b) show the present invention.Reference example 1It is the top view and sectional drawing of a semiconductor device.
2 (a), (b), and (c) are diagrams of the present invention.Reference example 1It is a figure explaining the procedure which creates this semiconductor device.
FIGS. 3 (a) and 3 (b) show the present invention.Reference example 1It is a figure explaining the procedure which creates this semiconductor device.
FIG. 4 of the present inventionReference example 2It is sectional drawing of this semiconductor device.
FIGS. 5 (a), 5 (b), and 5 (c) show the present invention.Reference example 2It is a figure explaining the procedure which creates this semiconductor device.
6 (a), (b), and (c) are diagrams of the present invention.Reference example 2It is a figure explaining the procedure which creates this semiconductor device.
7 (a) and 7 (b) are views of the present invention.Reference example 2It is a figure explaining the procedure which creates this semiconductor device.
[Fig. 8] of the present inventionReference example 3It is sectional drawing of this semiconductor device.
9 (a), (b) and (c) are diagrams of the present invention.Embodiment 1It is a figure explaining the procedure which creates this semiconductor device.
FIGS. 10 (a), (b), and (c) show the present invention.Embodiment 1It is a figure explaining the procedure which creates this semiconductor device.
FIGS. 11 (a) and 11 (b) show the present invention.Embodiment 1It is a figure explaining the procedure which creates this semiconductor device.
FIGS. 12A, 12B, and 12C are views for explaining a procedure for producing a conventional semiconductor device. FIGS.
FIGS. 13A and 13B are diagrams illustrating a procedure for manufacturing a conventional semiconductor device.
FIGS. 14A and 14B are views for explaining a procedure for producing a conventional semiconductor device. FIGS.
[Explanation of symbols]
101, 201, 301 Silicon substrate
102, 106, 202, 206, 207, 302, 306, 307 Silicon oxide film
103, 203, 303 well region
104, 204, 304 Gate insulating film
105, 109, 205, 209, 305, 309 Polycrystalline silicon film
107, 208, 308 Silicon nitride film
110, 210, 310 Source region, drain region
110a, 210a, 310a Stacked diffusion layer
111, 211, 311 Gate electrode
112, 213, 313 Refractory metal silicide film
113, 212, 312 cavity
114, 214, 314 Interlayer insulating film
115, 215, 315 Contact hole
220 buried silicon oxide film

Claims (6)

A semiconductor substrate, a gate insulating film provided on the active region of the semiconductor substrate, a gate electrode provided on the gate insulating film, and a source region and a drain region located on both sides of the gate electrode, In each of the source region and the drain region, in the semiconductor device made of a conductor stacked above the interface between the active region and the gate insulating film,
An insulator is provided between the conductor and the gate electrode,
A part of the insulator protrudes upward from the gate electrode,
A cavity is formed between the other part of the insulator and the gate electrode,
The distance between the part of the insulator protruding upward from the gate electrode and the extended surface of the side surface of the gate electrode is the distance between the other part of the insulator and the side surface of the gate electrode. wherein a smaller than the distance between. The semiconductor device according to claim 1,
A part of the insulator protrudes upward from the conductor . The semiconductor device according to claim 1 or 2 ,
A semiconductor device, wherein a refractory metal silicide film is provided on a side wall of the gate electrode facing the cavity . Sequentially depositing a gate insulating film, a gate electrode, and an insulating film on a semiconductor substrate;
Patterning the insulating film and the gate electrode;
Forming a gate electrode sidewall insulating film in contact with the gate electrode sidewall;
Depositing a conductive film on the semiconductor substrate;
Etching until the conductive film on the gate electrode disappears to form a stacked conductor in contact with the gate electrode sidewall insulating film; and
Forming a cavity region by etching a part of the gate electrode side wall insulating film,
And a step of depositing an interlayer insulating film under conditions such that the cavity region becomes a cavity ,
The step of forming the gate electrode sidewall insulating film is a step of sequentially forming a first gate electrode sidewall insulating film and a second gate electrode sidewall insulating film,
The step of forming the cavity region is a step of etching either the first gate electrode sidewall insulating film or the second gate electrode sidewall insulating film,
After the step of patterning the insulating film and the gate electrode, and before the step of sequentially forming the first gate electrode sidewall insulating film and the second gate electrode sidewall insulating film, the width of the insulating film is the method of manufacturing a semiconductor device characterized by comprising the step of smaller than the width of the gate electrode. In the manufacturing method of the semiconductor device according to claim 4 ,
The first gate electrode sidewall insulating film is a silicon oxide film;
The second gate electrode sidewall insulating film is a silicon nitride film;
The method of manufacturing a semiconductor device, wherein the step of forming the cavity region is a step of etching the silicon oxide film . In the manufacturing method of the semiconductor device according to claim 4 ,
The method of manufacturing a semiconductor device, wherein the step of making the width of the insulating film smaller than the width of the gate electrode is a step of heat-treating the insulating film at 700 ° C. to 900 ° C.

Images