JPH07193233A - Manufacture of transistor having no gate sidewall - Google Patents

Abstract

PURPOSE:To reduce parasitic capacity between a gate and the source.drain of a MOS transistor. CONSTITUTION:After forming the source.drain 30 having a gate electrode 10 of a MOS transistor provided with a sidewall Si3N4 film as a mask by ion implantation, a mounting part is made on the source drain by selective epitaxial growth. Later the sidewall Si3N4 film is removed by etching so as to pile up oxide films 70 by low temperature low pressure CVD of low step coverage so that the part having a removed sidewall becomes vacuum. Thereby, the parasitic capacity is reduced than in case of being blocked with oxide films.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to a method for manufacturing a transistor without a gate sidewall.

[0002]

2. Description of the Related Art A conventional MOS transistor is normally shown in FIG.
As described above, the SiO ₂ or Si ₃ N ₄ 20 formed as the side wall of the gate 10 was left as it was, and a SiO ₂ film (not shown) having a good flatness was formed thereon.

[0003]

In the method of leaving the side wall in FIG. 6, there is a parasitic capacitance C _fr between the gate and the source / drain in the path as shown in the figure by the dielectric constant of SiO ₂ or Si ₃ N ₄ . There is a problem that the switching speed of the transistor is reduced due to this parasitic capacitance.

[0004]

The means proposed by the present invention for solving the above problems are the following three. Forming a gate electrode via a gate insulating film, forming a source and drain regions using the gate electrode as a mask, a step of forming a Si ₃ N ₄ sidewall or SiO ₂ sidewalls to the gate side, the Si ₃ N ₄ sidewall or Si
A step of selectively epitaxially growing a Si film on the source / drain regions outside the O ₂ side wall; and Si ₃ N ₄
It has a step of selectively etching only the film or the side wall of SiO ₂ and a step of growing the SiO ₂ film on the entire surface of the substrate by low temperature and low pressure CVD which has poor step coverage.

A step of forming a gate electrode via a gate insulating film, a step of forming source / drain regions using the gate electrode as a mask, a step of forming Si ₃ N ₄ side walls on the side surface of the gate, and the step of forming the Si ₃ N layer. ₄ outside source of sidewall
Forming a SiO ₂ sidewall on the drain region;
The method has a step of etching the i ₃ N ₄ film and a step of growing the SiO ₂ film on the entire surface of the substrate by low temperature and low pressure CVD which has poor step coverage.

[0006] A step of forming a gate electrode via a gate insulating film, a step of forming a source / drain region using the gate electrode as a mask, a step of forming a SiO ₂ side wall on a side surface of the gate, and an outside of the SiO ₂ side wall. Forming Si ₃ N ₄ sidewalls in the source / drain regions of
It has a step of etching the O ₂ side wall and a step of growing a SiO ₂ film on the entire surface of the substrate by low temperature and low pressure CVD which has poor step coverage.

[0007]

In the present invention, the side surface of the gate electrode is evacuated to reduce the parasitic capacitance between the gate and the source / drain, thereby improving the switching speed. In particular, the source / drain raised type transistor has a large parasitic capacitance between the raised portion and the gate electrode, but this method can significantly reduce the parasitic capacitance.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an embodiment of the present invention. The source / drain portion 30 has a raised structure, and a gap (vacuum) 40 exists between the raised portion and the gate electrode 10. By making a gap on the side surface of the gate electrode in this way,
The parasitic capacitance between the gate and the source / drain is reduced. The manufacturing process of this transistor will be described below (see FIG. 2). A gate poly is formed on the gate oxide film 5 on the Si substrate 1.
The Si electrode 10 is formed. Growing the Si ₃ N ₄ film 50 on the entire surface of the substrate by anisotropic etching, Si ₃ other than the gate side wall portion
Remove the N ₄ film. Ion implantation is performed on the entire surface of the substrate to form the source / drain regions 30. The gate oxide film on the source / drain is removed by etching. By the selective epitaxial method, the epitaxial Si film 60 is grown only on the exposed source / drain of Si. The Si ₃ N ₄ side wall is removed by etching. An oxide film 7 is formed on the entire surface by the CVD method, which has poor step coverage.
Grow 0.

Through the above steps, the vacuum portion 40 is formed on the side surface of the gate electrode as shown in FIG. When the CVD oxide film is grown in the step of, the oxide film actually grows to some extent on the side surface of the gate electrode as shown in FIG.
By growing under conditions of low temperature and low pressure, it is possible to minimize the growth on the side surface, especially near the bottom. Since the contribution to the capacitance C _fr between the gate and the source / drain is greatest in the vicinity of the gate oxide film shown by the arrow in the figure, if the oxide film in this portion is small, a large capacitance reduction effect can be obtained. The growth conditions are, for example, 430 ° C., 0.
52 Torr (J. Vac. Sci. Tech. B1
Conditions such as (1), 1983, p54-61) are good.

FIG. 4 shows another embodiment of the present invention. The source / drain is not raised and has a normal structure, but a vacuum portion exists on the side surface of the gate electrode. By thus forming a vacuum portion on the side surface of the gate electrode, the parasitic capacitance between the gate and the source / drain is reduced as in the first embodiment. The manufacturing process of this transistor will be described below (see FIG. 5). A gate electrode 10 is formed on the gate oxide film 5. A Si ₃ N ₄ film 50 is grown on the entire surface of the substrate. By anisotropic etching, Si ₃ except for the side wall of the gate
The N ₄ film 50 is removed.

Ions are implanted on the entire surface of the substrate to
The drain region 30 is formed. A SiO ₂ film 80 is grown on the entire surface of the substrate. By anisotropic etching, SiO other than the side wall of the gate is formed.
₂ Remove the film. The Si ₃ N ₄ side wall is removed by etching. An oxide film 7 is formed on the entire surface by the CVD method, which has poor step coverage.
Grow 0.

Through the above steps, the vacuum portion 40 is formed on the side surface of the gate electrode as shown in FIG. By performing the growth under the conditions of low temperature and low pressure as in the first embodiment in the process of (1), it is possible to minimize the growth on the side surface, especially near the bottom.

Further, in this step, Si ₃ N ₄ can be changed to SiO ₂ and SiO ₂ can be changed to Si ₃ N ₄ .

[0014]

As described above, in the present invention, the gate-source-drain capacitance can be reduced to 1/4 at the maximum with respect to the side wall of the oxide film by evacuating the side wall of the gate.
In particular, the source / drain raised type transistor has a large parasitic capacitance between the raised portion and the gate electrode, but this method can significantly reduce the parasitic capacitance.

[0015]

[Brief description of drawings]

FIG. 1 is a diagram showing a structure of an element formed by the method of the present invention.

FIG. 2 is a diagram showing a method for manufacturing the device of FIG.

FIG. 3 is an enlarged view of a gate side wall portion.

FIG. 4 is a diagram of a device structure according to another embodiment of the present invention.

FIG. 5 is a diagram showing a method of manufacturing the device of FIG.

FIG. 6 is a diagram of a device structure of a conventional transistor.

[Explanation of symbols]

10 gate electrode 30 source / drain 40 vacuum 50 Si ₃ N ₄ film 60 epitaxial Si film 70 oxide film

Claims (3)

[Claims] 1. A step of forming a gate electrode via a gate insulating film, a step of forming source / drain regions by using the gate electrode as a mask, and a step of forming Si ₃ N ₄ side walls or SiO ₂ side walls on the side surface of the gate. And the above-mentioned Si ₃ N
₄ step of selectively epitaxially growing a Si film on the source / drain regions outside the side wall or SiO ₂ side wall, step of selectively etching only the Si ₃ N ₄ film or SiO ₂ side wall, and step coverage is poor. A method of manufacturing a transistor without a gate sidewall, comprising a step of growing an SiO ₂ film on the entire surface of a substrate by low temperature and low pressure CVD. 2. A step of forming a gate electrode via a gate insulating film, a step of forming source / drain regions by using the gate electrode as a mask, a step of forming Si ₃ N ₄ side walls on a side surface of the gate, A step of forming SiO ₂ sidewalls on the source / drain regions outside the ₃ N ₄ sidewalls, a step of etching the Si ₃ N ₄ film, and a SiO ₂ film on the entire surface of the substrate by low temperature and low pressure CVD with poor step coverage. A method of manufacturing a gate sidewallless transistor having a step of growing. 3. A step of forming a gate electrode via a gate insulating film, a step of forming source / drain regions by using the gate electrode as a mask, a step of forming a SiO ₂ side wall on a side surface of the gate, and the SiO ₂ side wall. Forming Si ₃ N ₄ side walls on the source / drain regions outside the substrate,
A process for etching an iO ₂ side wall and a method for manufacturing a transistor without a bad wall having step coverage.