JPH07193233A - Manufacture of transistor having no gate sidewall - Google Patents
Manufacture of transistor having no gate sidewallInfo
- Publication number
- JPH07193233A JPH07193233A JP33020293A JP33020293A JPH07193233A JP H07193233 A JPH07193233 A JP H07193233A JP 33020293 A JP33020293 A JP 33020293A JP 33020293 A JP33020293 A JP 33020293A JP H07193233 A JPH07193233 A JP H07193233A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- forming
- source
- sio
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明はゲート側壁なしトランジ
スタの製造方法に関する。FIELD OF THE INVENTION The present invention relates to a method for manufacturing a transistor without a gate sidewall.
【0002】[0002]
【従来の技術】従来のMOSトランジスタでは通常図6
のようにゲート10の側壁として形成されるSiO2 も
しくはSi3 N4 20はそのまま残されて、その上に平
坦性の良いSiO2 膜(図示せず)が形成されていた。2. Description of the Related Art A conventional MOS transistor is normally shown in FIG.
As described above, the SiO 2 or Si 3 N 4 20 formed as the side wall of the gate 10 was left as it was, and a SiO 2 film (not shown) having a good flatness was formed thereon.
【0003】[0003]
【発明が解決しようとする課題】図6の側壁を残す方式
ではSiO2 やSi3 N4 の誘電率の分だけ図のような
経路でゲートとソース・ドレイン間に寄生容量Cfrが存
在し、この寄生容量によってトランジスタのスイッチン
グ速度が低下するという問題があった。In the method of leaving the side wall in FIG. 6, there is a parasitic capacitance C fr between the gate and the source / drain in the path as shown in the figure by the dielectric constant of SiO 2 or Si 3 N 4 . There is a problem that the switching speed of the transistor is reduced due to this parasitic capacitance.
【0004】[0004]
【課題を解決するための手段】上記の問題点を解決する
ために本発明が提案する手段は、次の三つである。ゲー
ト絶縁膜を介してゲート電極を形成する工程と、ゲート
電極をマスクとしてソース・ドレイン領域を形成する工
程と、ゲート側面にSi3 N4 側壁もしくはSiO2 側
壁を形成する工程と、前記Si3 N4 側壁もしくはSi
O2 側壁の外側のソース・ドレイン領域にSi膜を選択
的にエピタキシャル成長させる工程と、前記Si3 N4
膜もしくはSiO2 側壁のみを選択的にエッチングする
工程と、段差被覆性の悪い低温低圧のCVDによって基
板全面にSiO2 膜を成長させる工程を有する。The means proposed by the present invention for solving the above problems are the following three. Forming a gate electrode via a gate insulating film, forming a source and drain regions using the gate electrode as a mask, a step of forming a Si 3 N 4 sidewall or SiO 2 sidewalls to the gate side, the Si 3 N 4 sidewall or Si
A step of selectively epitaxially growing a Si film on the source / drain regions outside the O 2 side wall; and Si 3 N 4
It has a step of selectively etching only the film or the side wall of SiO 2 and a step of growing the SiO 2 film on the entire surface of the substrate by low temperature and low pressure CVD which has poor step coverage.
【0005】ゲート絶縁膜を介してゲート電極を形成す
る工程と、ゲート電極をマスクとしてソース・ドレイン
領域を形成する工程と、ゲート側面にSi3 N4 側壁を
形成する工程と、前記Si3 N4 側壁の外側のソース・
ドレイン領域にSiO2 側壁を形成する工程と、前記S
i3 N4 膜をエッチングする工程と、段差被覆性の悪い
低温低圧のCVDによって基板全面にSiO2 膜を成長
させる工程を有する。A step of forming a gate electrode via a gate insulating film, a step of forming source / drain regions using the gate electrode as a mask, a step of forming Si 3 N 4 side walls on the side surface of the gate, and the step of forming the Si 3 N layer. 4 outside source of sidewall
Forming a SiO 2 sidewall on the drain region;
The method has a step of etching the i 3 N 4 film and a step of growing the SiO 2 film on the entire surface of the substrate by low temperature and low pressure CVD which has poor step coverage.
【0006】ゲート絶縁膜を介してゲート電極を形成す
る工程と、ゲート電極をマスクとしてソース・ドレイン
領域を形成する工程と、ゲート側面にSiO2 側壁を形
成する工程と、前記SiO2 側壁の外側のソース・ドレ
イン領域にSi3 N4 側壁を形成する工程と、前記Si
O2 側壁をエッチングする工程と、段差被覆性の悪い低
温低圧のCVDによって基板全面にSiO2 膜を成長さ
せる工程を有する。[0006] A step of forming a gate electrode via a gate insulating film, a step of forming a source / drain region using the gate electrode as a mask, a step of forming a SiO 2 side wall on a side surface of the gate, and an outside of the SiO 2 side wall. Forming Si 3 N 4 sidewalls in the source / drain regions of
It has a step of etching the O 2 side wall and a step of growing a SiO 2 film on the entire surface of the substrate by low temperature and low pressure CVD which has poor step coverage.
【0007】[0007]
【作用】本発明ではゲート電極の側面を真空にすること
でゲートとソース・ドレインの間の寄生容量を低減で
き、スイッチング速度が向上する。特に、ソース・ドレ
インせり上げ型のトランジスタではせり上げ部とゲート
電極との間に大きな寄生容量がついていたが、本方式で
は、寄生容量を大幅に低減できる。In the present invention, the side surface of the gate electrode is evacuated to reduce the parasitic capacitance between the gate and the source / drain, thereby improving the switching speed. In particular, the source / drain raised type transistor has a large parasitic capacitance between the raised portion and the gate electrode, but this method can significantly reduce the parasitic capacitance.
【0008】[0008]
【実施例】図1は本発明の一実施例である。ソース・ド
レイン部30はせり上げ構造となっており、このせり上
げ部とゲート電極10の間に間隙(真空)40が存在す
る。このようにゲート電極の側面に間隙を作ることで、
ゲートとソース・ドレイン間の寄生容量の低減してい
る。このトランジスタの製造工程について以下に説明す
る(図2参照)。 Si基板1上のゲート酸化膜5上に、ゲートpoly
Si電極10を形成する。 基板全面にSi3 N4 膜50を成長させる、 異方性エッチングにより、ゲート側壁部以外のSi3
N4 膜を取り除く。 基板全面にイオン注入を行い、ソース・ドレイン領域
30を形成する。 エッチングによりソース・ドレイン上のゲート酸化膜
を取り除く。 選択エピタキシャル法により、Siの露出しているソ
ース・ドレイン上だけにエピタキシャルSi膜60を成
長させる。 Si3 N4 側壁をエッチングにより取り除く。 段差被覆性の悪いCVD法によって、全面に酸化膜7
0を成長させる。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an embodiment of the present invention. The source / drain portion 30 has a raised structure, and a gap (vacuum) 40 exists between the raised portion and the gate electrode 10. By making a gap on the side surface of the gate electrode in this way,
The parasitic capacitance between the gate and the source / drain is reduced. The manufacturing process of this transistor will be described below (see FIG. 2). A gate poly is formed on the gate oxide film 5 on the Si substrate 1.
The Si electrode 10 is formed. Growing the Si 3 N 4 film 50 on the entire surface of the substrate by anisotropic etching, Si 3 other than the gate side wall portion
Remove the N 4 film. Ion implantation is performed on the entire surface of the substrate to form the source / drain regions 30. The gate oxide film on the source / drain is removed by etching. By the selective epitaxial method, the epitaxial Si film 60 is grown only on the exposed source / drain of Si. The Si 3 N 4 side wall is removed by etching. An oxide film 7 is formed on the entire surface by the CVD method, which has poor step coverage.
Grow 0.
【0009】以上の工程によって図1のようにゲート電
極の側面に真空の部分40が形成される。の工程での
CVD酸化膜を成長させるときに、実際には図3のよう
にゲート電極の側面にもある程度酸化膜が成長するが、
低温・低圧の条件で成長させることにより、側面、特に
底の付近の成長を最小限にとどめることができる。ゲー
トとソース・ドレイン間の容量Cfrに対する寄与は図中
で矢印で示したゲート酸化膜付近が最も大きいため、こ
の部分の酸化膜が小さければ、大きな容量低減の効果が
得られる。この成長条件としては例えば430℃、0.
52Torr(J.Vac.Sci.Tech.B1
(1),1983,p54−61)などの条件がよい。Through the above steps, the vacuum portion 40 is formed on the side surface of the gate electrode as shown in FIG. When the CVD oxide film is grown in the step of, the oxide film actually grows to some extent on the side surface of the gate electrode as shown in FIG.
By growing under conditions of low temperature and low pressure, it is possible to minimize the growth on the side surface, especially near the bottom. Since the contribution to the capacitance C fr between the gate and the source / drain is greatest in the vicinity of the gate oxide film shown by the arrow in the figure, if the oxide film in this portion is small, a large capacitance reduction effect can be obtained. The growth conditions are, for example, 430 ° C., 0.
52 Torr (J. Vac. Sci. Tech. B1
Conditions such as (1), 1983, p54-61) are good.
【0010】図4は本発明の他の実施例である。ソース
・ドレインはせり上げず、通常の構造となっているがゲ
ート電極の側面に真空の部分が存在する。このようにゲ
ート電極の側面に真空の部分を作ることで、第1の実施
例と同じくゲートとソース・ドレイン間の寄生容量を低
減している。このトランジスタの製造工程について以下
に説明する(図5参照)。 ゲート酸化膜5上にゲート電極10を形成する。 基板全面にSi3 N4 膜50を成長させる。 異方性エッチングにより、ゲート側壁部以外のSi3
N4 膜50を取り除く。FIG. 4 shows another embodiment of the present invention. The source / drain is not raised and has a normal structure, but a vacuum portion exists on the side surface of the gate electrode. By thus forming a vacuum portion on the side surface of the gate electrode, the parasitic capacitance between the gate and the source / drain is reduced as in the first embodiment. The manufacturing process of this transistor will be described below (see FIG. 5). A gate electrode 10 is formed on the gate oxide film 5. A Si 3 N 4 film 50 is grown on the entire surface of the substrate. By anisotropic etching, Si 3 except for the side wall of the gate
The N 4 film 50 is removed.
【0011】基板全面にイオン注入を行い、ソース・
ドレイン領域30を形成する。 基板全面にSiO2 膜80を成長させる。 異方性エッチングにより、ゲート側壁部以外のSiO
2 膜を取り除く。 Si3 N4 側壁をエッチングにより取り除く。 段差被覆性の悪いCVD法によって、全面に酸化膜7
0を成長させる。Ions are implanted on the entire surface of the substrate to
The drain region 30 is formed. A SiO 2 film 80 is grown on the entire surface of the substrate. By anisotropic etching, SiO other than the side wall of the gate is formed.
2 Remove the film. The Si 3 N 4 side wall is removed by etching. An oxide film 7 is formed on the entire surface by the CVD method, which has poor step coverage.
Grow 0.
【0012】以上の工程によって図4のようにゲート電
極の側面に真空の部分40が形成される。の工程で第
1の実施例と同じく低温・低圧の条件で成長させること
により、側面、特に底の付近の成長を最小限にとどめる
ことができる。Through the above steps, the vacuum portion 40 is formed on the side surface of the gate electrode as shown in FIG. By performing the growth under the conditions of low temperature and low pressure as in the first embodiment in the process of (1), it is possible to minimize the growth on the side surface, especially near the bottom.
【0013】また、この工程ではとのSi3 N4 を
SiO2 に、とのSiO2 をSi3 N4 にすること
もできる。Further, in this step, Si 3 N 4 can be changed to SiO 2 and SiO 2 can be changed to Si 3 N 4 .
【0014】[0014]
【発明の効果】以上説明したように、本発明ではゲート
側壁を真空にすることで、酸化膜の側壁に対してゲート
−ソース・ドレイン間容量を最大1/4に低減できる。
特に、ソース・ドレインせり上げ型のトランジスタでは
せり上げ部とゲート電極との間に大きな寄生容量がつい
ていたが、本方式では、寄生容量を大幅に低減できる。As described above, in the present invention, the gate-source-drain capacitance can be reduced to 1/4 at the maximum with respect to the side wall of the oxide film by evacuating the side wall of the gate.
In particular, the source / drain raised type transistor has a large parasitic capacitance between the raised portion and the gate electrode, but this method can significantly reduce the parasitic capacitance.
【0015】[0015]
【図1】本発明の方法で形成する素子の構造を示す図で
ある。FIG. 1 is a diagram showing a structure of an element formed by the method of the present invention.
【図2】図1の素子の製造方法を示す図である。FIG. 2 is a diagram showing a method for manufacturing the device of FIG.
【図3】ゲート側壁部の拡大図である。FIG. 3 is an enlarged view of a gate side wall portion.
【図4】本発明の他の実施例の素子構造の図である。FIG. 4 is a diagram of a device structure according to another embodiment of the present invention.
【図5】図4の素子の製造方法を示す図である。FIG. 5 is a diagram showing a method of manufacturing the device of FIG.
【図6】従来のトランジスタの素子構造の図である。FIG. 6 is a diagram of a device structure of a conventional transistor.
10 ゲート電極 30 ソース・ドレイン 40 真空 50 Si3 N4 膜 60 エピタキシャルSi膜 70 酸化膜10 gate electrode 30 source / drain 40 vacuum 50 Si 3 N 4 film 60 epitaxial Si film 70 oxide film
Claims (3)
する工程と、ゲート電極をマスクとしてソース・ドレイ
ン領域を形成する工程と、ゲート側面にSi3 N4 側壁
もしくはSiO2 側壁を形成する工程と、前記Si3 N
4 側壁もしくはSiO2 側壁の外側のソース・ドレイン
領域にSi膜を選択的にエピタキシャル成長させる工程
と、前記Si3 N4 膜もしくはSiO2 側壁のみを選択
的にエッチングする工程と、段差被覆性の悪い低温低圧
のCVDによって基板全面にSiO2 膜を成長させる工
程を有するゲート側壁なしトランジスタの製造方法。1. A step of forming a gate electrode via a gate insulating film, a step of forming source / drain regions by using the gate electrode as a mask, and a step of forming Si 3 N 4 side walls or SiO 2 side walls on the side surface of the gate. And the above-mentioned Si 3 N
4 step of selectively epitaxially growing a Si film on the source / drain regions outside the side wall or SiO 2 side wall, step of selectively etching only the Si 3 N 4 film or SiO 2 side wall, and step coverage is poor. A method of manufacturing a transistor without a gate sidewall, comprising a step of growing an SiO 2 film on the entire surface of a substrate by low temperature and low pressure CVD.
する工程と、ゲート電極をマスクとしてソース・ドレイ
ン領域を形成する工程と、ゲート側面にSi3 N4 側壁
を形成する工程と、前記Si3 N4 側壁の外側のソース
・ドレイン領域にSiO2 側壁を形成する工程と、前記
Si3 N4 膜をエッチングする工程と、段差被覆性の悪
い低温低圧のCVDによって基板全面にSiO2 膜を成
長させる工程を有するゲート側壁なしトランジスタの製
造方法。2. A step of forming a gate electrode via a gate insulating film, a step of forming source / drain regions by using the gate electrode as a mask, a step of forming Si 3 N 4 side walls on a side surface of the gate, A step of forming SiO 2 sidewalls on the source / drain regions outside the 3 N 4 sidewalls, a step of etching the Si 3 N 4 film, and a SiO 2 film on the entire surface of the substrate by low temperature and low pressure CVD with poor step coverage. A method of manufacturing a gate sidewallless transistor having a step of growing.
する工程と、ゲート電極をマスクとしてソース・ドレイ
ン領域を形成する工程と、ゲート側面にSiO2 側壁を
形成する工程と、前記SiO2 側壁の外側のソース・ド
レイン領域にSi3 N4 側壁を形成する工程と、前記S
iO2 側壁をエッチングする工程と、段差被覆性の悪壁
なしトランジスタの製造方法。3. A step of forming a gate electrode via a gate insulating film, a step of forming source / drain regions by using the gate electrode as a mask, a step of forming a SiO 2 side wall on a side surface of the gate, and the SiO 2 side wall. Forming Si 3 N 4 side walls on the source / drain regions outside the substrate,
A process for etching an iO 2 side wall and a method for manufacturing a transistor without a bad wall having step coverage.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP33020293A JPH07193233A (en) | 1993-12-27 | 1993-12-27 | Manufacture of transistor having no gate sidewall |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP33020293A JPH07193233A (en) | 1993-12-27 | 1993-12-27 | Manufacture of transistor having no gate sidewall |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH07193233A true JPH07193233A (en) | 1995-07-28 |
Family
ID=18229985
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP33020293A Pending JPH07193233A (en) | 1993-12-27 | 1993-12-27 | Manufacture of transistor having no gate sidewall |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH07193233A (en) |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6051861A (en) * | 1996-03-07 | 2000-04-18 | Nec Corporation | Semiconductor device with reduced fringe capacitance and short channel effect |
US6127711A (en) * | 1997-06-23 | 2000-10-03 | Nec Corporation | Semiconductor device having plural air gaps for decreasing parasitic capacitance |
US6545317B2 (en) * | 2000-06-30 | 2003-04-08 | Kabushiki Kaisha Toshiba | Semiconductor device having a gate electrode with a sidewall insulating film and manufacturing method thereof |
JP2004273508A (en) * | 2003-03-05 | 2004-09-30 | Sharp Corp | Semiconductor device and its manufacturing method |
JP2007234961A (en) * | 2006-03-02 | 2007-09-13 | Fujitsu Ltd | Method for manufacturing semiconductor device |
DE102006049158A1 (en) * | 2006-09-08 | 2008-04-03 | Qimonda Ag | Transistor, memory cell array and method of manufacturing a transistor |
US7579231B2 (en) | 1999-01-29 | 2009-08-25 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
US11038038B2 (en) | 2019-08-13 | 2021-06-15 | Micron Technology, Inc. | Transistors and methods of forming transistors |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01122173A (en) * | 1987-11-05 | 1989-05-15 | Nec Corp | Field-effect transistor |
JPH02165655A (en) * | 1988-12-20 | 1990-06-26 | Fujitsu Ltd | Manufacture of semiconductor device |
JPH0370160A (en) * | 1989-08-09 | 1991-03-26 | Fujitsu Ltd | Manufacture of semiconductor device |
-
1993
- 1993-12-27 JP JP33020293A patent/JPH07193233A/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01122173A (en) * | 1987-11-05 | 1989-05-15 | Nec Corp | Field-effect transistor |
JPH02165655A (en) * | 1988-12-20 | 1990-06-26 | Fujitsu Ltd | Manufacture of semiconductor device |
JPH0370160A (en) * | 1989-08-09 | 1991-03-26 | Fujitsu Ltd | Manufacture of semiconductor device |
Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6051861A (en) * | 1996-03-07 | 2000-04-18 | Nec Corporation | Semiconductor device with reduced fringe capacitance and short channel effect |
US6124176A (en) * | 1996-03-07 | 2000-09-26 | Nec Corporation | Method of producing a semiconductor device with reduced fringe capacitance and short channel effect |
US6127711A (en) * | 1997-06-23 | 2000-10-03 | Nec Corporation | Semiconductor device having plural air gaps for decreasing parasitic capacitance |
US7579231B2 (en) | 1999-01-29 | 2009-08-25 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
US6545317B2 (en) * | 2000-06-30 | 2003-04-08 | Kabushiki Kaisha Toshiba | Semiconductor device having a gate electrode with a sidewall insulating film and manufacturing method thereof |
US6927459B2 (en) | 2000-06-30 | 2005-08-09 | Kabushiki Kaisha Toshiba | Semiconductor device having a gate electrode with a sidewall insulating film and manufacturing method thereof |
JP2004273508A (en) * | 2003-03-05 | 2004-09-30 | Sharp Corp | Semiconductor device and its manufacturing method |
JP2007234961A (en) * | 2006-03-02 | 2007-09-13 | Fujitsu Ltd | Method for manufacturing semiconductor device |
DE102006049158A1 (en) * | 2006-09-08 | 2008-04-03 | Qimonda Ag | Transistor, memory cell array and method of manufacturing a transistor |
DE102006049158B4 (en) * | 2006-09-08 | 2008-07-03 | Qimonda Ag | Transistor, memory cell array and method of manufacturing a transistor |
US7763514B2 (en) | 2006-09-08 | 2010-07-27 | Qimonda Ag | Method of manufacturing a transistor and memory cell array |
US11038038B2 (en) | 2019-08-13 | 2021-06-15 | Micron Technology, Inc. | Transistors and methods of forming transistors |
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Date | Code | Title | Description |
---|---|---|---|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 19970805 |