JP2002231941A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the capacitance between the source or drain and the gate electrode while reducing the resistance of the source and drain region. SOLUTION: Between the gate electrode G formed between the source and the drain (6) on a semiconductor substrate 1 via a gate insulation film and an extraction electrode section 9 formed on the source or drain (6), a space 11 is formed. Consequently, the resistance of the source and the drain region 6 can be reduced by the extraction electrode section 9 formed on the source or drain (6). The capacitance between the source or drain (6) and the gate electrode G can also be reduced by the gap 11 formed between the gate electrode G and the extraction electrode section 9.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a fine MISFET (Metal Insulatoto).
r Semiconductor Field Effect Transistor).

[0002]

2. Description of the Related Art The resistance of a source / drain region is reduced on the source / drain region of a MISFET.
A silicide layer is formed to reduce the contact resistance with the extraction electrode formed on the upper part. This silicide layer is formed on the source and drain regions including on the gate electrode by Ti
It is formed by depositing a high melting point metal such as (titanium) and performing a heat treatment to cause a silicidation reaction at a contact portion between the gate electrode, the source, and the drain region and the high melting point metal. According to such a process, a silicide layer is formed on the gate electrode, the source, and the drain region in a self-aligned manner (salicide technique). Such salicide technology is described in, for example, VLSI Symp. ,
Tech. Dig. , P. 107-108, 1999.

[0003]

However, the junction depth of the source and drain regions tends to be shallow with the miniaturization of elements. When the above-mentioned salicide technique is applied to such a shallow source / drain region to form a silicide layer, the silicide layer approaches the junction between the source and drain regions, penetrates the junction, and extends to the semiconductor substrate. Can be reached. As a result, junction leakage increases. A study on such a problem is, for example, the IEEE.
E, Electron Device, Vol. 46,
No. 7, pages 1545-1550.

On the other hand, if the silicide layer is formed thin in order to secure the distance between the junction between the source and drain regions and the silicide layer, the resistance of the source and drain regions increases, and the performance of the device is reduced.

Therefore, as a method for reducing the junction leakage while securing the thickness of the silicide layer, a thick silicon film is selectively deposited on the source and drain regions, and the silicon layer is silicided to form the source. A technique for reducing the resistance of the drain region has been studied. This technology is described in, for example, IEEE, Electron Dev.
ice Letters, Vol. 18, No. 6,
p. 251-253.

However, in the above-described method, for example, as shown in FIG. 10, the silicide layer 20 on the source / drain region 6 is formed close to the gate electrode G. Therefore, the capacitance Ca (capacity) between the gate electrode G and the source (6) or between the gate electrode G and the drain (6) increases, and the element performance decreases. In particular, since the phase between the gate electrode and the drain is electrically opposite to each other, if the capacitance between them increases, the signal transmission speed decreases, and the switching characteristics deteriorate. In addition, Sw in FIG.
It is a sidewall film made of a silicon oxide film or the like.

An object of the present invention is to reduce the capacitance between the source or drain and the gate electrode while reducing the resistance of the source and drain regions.

Another object of the present invention is to improve the characteristics of a MISFET.

The above objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0010]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

A semiconductor integrated circuit device according to the present invention comprises: (a) a source and a drain formed in a semiconductor substrate; and (b) a gate formed between the source and the drain of the semiconductor substrate via a gate insulating film. An electrode portion; and (c) an extraction electrode portion formed on the source or the drain, and (d) a gap between the extraction electrode portion and the gate electrode portion.

According to such a means, since the gap is formed between the extraction electrode and the gate electrode, the capacitance between the drain and the gate electrode or between the source and the gate electrode is reduced. be able to. Also,
Since the extraction electrode portion is formed on the source or the drain, the resistance of the source and drain regions can be reduced. In particular, if the extraction electrode is formed of a metal film such as W (tungsten), the resistance of the source and drain regions can be further reduced.

[0013]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and the repeated description thereof will be omitted.

FIG. 1 is a sectional view of a principal part of a semiconductor integrated circuit device according to an embodiment of the present invention, and FIG. 2 is a plan view of a principal part of the semiconductor integrated circuit device according to the embodiment of the present invention. . FIG. 1 corresponds to the AA cross-sectional view of FIG. It is to be noted that the detailed structure of this semiconductor integrated circuit device will be clarified by the description of the manufacturing method described later, and therefore, the characteristic portion will be described here.

As shown in FIG. 1, a semiconductor substrate 1 includes
A source / drain region 6 is formed, and a gate electrode G is formed between the source and the drain (channel region) via a gate insulating film (not shown). Also,
Plugs (lead electrodes) 9 are formed on the source and drain regions 6.
Is formed, and a gap 11 exists between the extraction electrode 9 and the gate electrode G. Further, as shown in FIG. 2, the extraction electrode 9 is formed on the source / drain region 6 in a linear shape (stripe shape). P1 and P2 on the extraction electrode 9 and the gate electrode G indicate connection portions with the first layer wiring (not shown).

Next, a method of manufacturing the semiconductor integrated circuit device shown in FIGS. 1 and 2 will be described.

First, as shown in FIG.
After a p-type impurity (boron) and an n-type impurity (for example, phosphorus) are ion-implanted into a semiconductor substrate (hereinafter simply referred to as a substrate) 1 made of p-type single crystal silicon having a specific resistance of about Ωcm, the semiconductor substrate is heated to about By diffusing the impurities by heat treatment, a p-type well 3 and an n-type well 4 are formed in the semiconductor substrate 1. The p-type well 3 and the n-type well 4 are separated by, for example, an element isolation groove 2 in which a silicon oxide film is embedded.

Thereafter, an n-channel MISFET is formed on the p-type well 3, and on the n-type well 4,
A p-channel MISFET is formed.
Since the ISFET is formed in the same process except that the conductivity type of the impurities used is opposite,
Here, the case of an n-channel MISFET will be described.

Next, after the surface of the semiconductor substrate 1 (p-type well 3) is wet-cleaned using a hydrofluoric acid-based cleaning solution, the surface of the p-type well 3 is formed to a thickness of about 6 nm by thermal oxidation at about 800.degree. A clean gate oxide film (not shown) is formed.

Next, as shown in FIG. 4, a low-resistance polycrystalline silicon film 5a doped with phosphorus (P) and having a thickness of about 50 nm is deposited on the gate oxide film by the CVD method. A W film 5b having a thickness of about 50 nm is deposited by a sputtering method, and a silicon oxide film S1 having a thickness of about 75 nm is further deposited thereon. Next, a heat treatment at about 800 ° C. is performed in an inert gas atmosphere such as nitrogen for the purpose of relaxing the stress of the W film 5b. The polycrystalline silicon film 5a and the W film 5b
Between them, a WN film (not shown) having a thickness of about 10 nm may be formed.

Next, as shown in FIG. 5, using a photoresist film (not shown) as a mask, the silicon oxide films S1 and W
The film 5b and the polycrystalline silicon film 5a are dry-etched. As a result, the polysilicon film 5a and the W film 5b
Is formed. Next, an n ⁺ -type semiconductor region (source and drain regions) 6 is formed by ion-implanting an n-type impurity (arsenic) into the p-type well 3.

Next, as shown in FIG. 6, a silicon nitride film 7 having a thickness of about 25 nm is deposited on the semiconductor substrate 1, and a silicon oxide film S2 having a thickness of about 300 nm is formed on the silicon nitride film 7. accumulate.

Next, as shown in FIG. 7, the silicon oxide film S2 is polished by CMP (Chemical Mechanical Polishing) until the surface of the silicon nitride film 7 above the gate electrode G is exposed. Next, the exposed silicon nitride film 7 is removed by etching.

Next, as shown in FIG. 8, the silicon oxide film S2 and the silicon nitride film 7 on the n ⁺ type semiconductor region 6 are removed by dry etching using a photoresist film (not shown) as a mask. , A contact hole C is formed on the n ⁺ type semiconductor region 6.

Next, after a W film is deposited on the silicon oxide films S1 and S2 including the inside of the contact hole C by a CVD method, the W film on the silicon oxide films S1 and S2 is
The plug 9 (lead electrode) is formed by polishing by the MP method and leaving the W film only inside the contact hole C. Note that a thin WN film may be formed below the W film by a CVD method, and the plug 9 may be formed of two layers of the WN film and the W film.

As described above, according to the present embodiment, since the plug 9 is formed using the metal film such as the W film, the resistance of the source / drain region 6 can be reduced. Further, as is apparent from FIG. 2, the plug 9 is formed linearly over substantially the entire area of the source / drain region 6, so that the resistance of the source / drain region 6 can be reduced.

Next, as shown in FIG. 9, the silicon oxide films S1 and S2 are etched with hydrofluoric acid. The silicon oxide film is easily etched by hydrofluoric acid, while the silicon nitride film is hard to be etched by hydrofluoric acid. Therefore, the etching can be easily stopped on the surface of the silicon nitride film 7. In particular, the silicon oxide film S1,
When a PSG (Phosphor Silicate Glass) film is used for S2, the etching selectivity with respect to the silicon nitride film can be increased. Further, this silicon oxide film S1,
When a PSG film is used for S2, the selectivity with respect to the silicon oxide film deposited by the CVD method can be increased, so that the PSG film is etched without receding the surface of the silicon oxide film in the element isolation trench 2. can do.

In this etching, since the silicon oxide film S2 (about 50 nm in width) between the gate electrode G and the plug 9 is also removed, the width between the gate electrode G (silicon nitride film 7) and the plug 9 is reduced. A gap 11 of about 50 nm is generated.

Next, a silicon oxide film 10 is deposited on the semiconductor substrate 1 by the CVD method, and the surface thereof is polished and flattened by the CMP method, whereby the semiconductor integrated circuit device shown in FIGS. 1 and 2 is formed. .

Here, as shown in FIG.
The silicon oxide film 10 is deposited in the space 11 between the (silicon nitride film 7) and the plug 9 under conditions that the silicon oxide film 10 is not buried. For example, when the silicon oxide film 10 is deposited by the CVD method,
When the aspect ratio (the ratio of the width of the gap to the depth thereof) is 2 or more, the silicon oxide film 10 is not embedded. Further, in the plasma CVD method, the silicon oxide film 10 is not buried even if the aspect ratio is about 1 because the film forming temperature is low. As a result, a gap 11 remains between the gate electrode G and the plug 9.

The dielectric constant ε of the silicon oxide film is about 4
In the case of air, ε is about 1. Therefore, by forming the gap 11, the capacitance between the gate electrode G and the source or drain (6) can be reduced.

In particular, the capacitance between the gate electrode and the drain, which are electrically in opposite phases, can be reduced, the signal transmission speed can be increased, and the switching characteristics can be improved.

As described above, according to the present embodiment, the plug 9 is formed using a metal film such as a W film, and the plug 9 is formed in a straight line over substantially the entire region of the source / drain region 6. As a result, the resistance of the source / drain region 6 can be reduced.

Further, since the resistance of the source / drain region 6 can be reduced without using the salicide technique, the problem of junction leakage can be solved.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment and can be variously modified without departing from the gist of the invention. Needless to say,

In particular, in the above-described embodiment, an n-channel MISFET has been described as an example.
It is also possible to apply to ISFET. Further, the present invention can be applied to a CMOS (Complementary MOS) device having an n-channel MISFET and a p-channel MISFET.

[0037]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

Since the space is provided between the extraction electrode portion and the gate electrode portion, the capacitance between the drain and the gate electrode or between the source and the gate electrode can be reduced. Further, since the extraction electrode portion is formed on the source or the drain, the resistance of the source and drain regions can be reduced. In particular, this extraction electrode
When formed of a metal film such as W, the resistance of the source and drain regions can be further reduced.

[Brief description of the drawings]

FIG. 1 is a sectional view of a main part of a substrate showing a semiconductor integrated circuit device according to an embodiment of the present invention;

FIG. 2 is a plan view of a main part of a substrate showing the semiconductor integrated circuit device according to the embodiment of the present invention;

FIG. 3 is a fragmentary cross-sectional view of the substrate showing the method for manufacturing the semiconductor integrated circuit device according to the embodiment of the present invention;

FIG. 4 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the embodiment of the present invention;

FIG. 5 is a fragmentary cross-sectional view of the substrate showing the method for manufacturing the semiconductor integrated circuit device according to the embodiment of the present invention;

FIG. 6 is a fragmentary cross-sectional view of the substrate showing the method for manufacturing the semiconductor integrated circuit device according to the embodiment of the present invention;

FIG. 7 is a fragmentary cross-sectional view of the substrate showing the method for manufacturing the semiconductor integrated circuit device according to the embodiment of the present invention;

FIG. 8 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the embodiment of the present invention;

FIG. 9 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the embodiment of the present invention;

FIG. 10 is a diagram for explaining a problem of the present invention.

[Explanation of symbols]

Reference Signs List 1 semiconductor substrate 2 element isolation groove 3 p-type well 4 n-type well 5a polycrystalline silicon film 5b W film 6 n ⁺ type semiconductor region (source / drain region) 7 silicon nitride film 9 plug (lead electrode) 10 silicon oxide film 11 Void 20 Silicide layer C Contact hole Ca Capacitance G Gate electrode P1, P2 Connection S1 Silicon oxide film S2 Silicon oxide film Sw Sidewall film

Continued on the front page F term (reference) 5F140 AA10 AA11 AB03 BA01 BE02 BE07 BF04 BF11 BF17 BF20 BF21 BF27 BG09 BG13 BG14 BG17 BG20 BG28 BG30 BG33 BG38 BG54 BJ01 BJ07 BJ10 BJ11 BJ17 CC13 CB13

Claims (1)

[Claims] (A) a source and a drain formed in a semiconductor substrate; (b) a gate electrode portion formed between a source and a drain of the semiconductor substrate via a gate insulating film; A lead electrode portion formed on the source or the drain, and (d) a gap is provided between the lead electrode portion and the gate electrode portion.