JP2005116592A - Field effect transistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To attain high speed and high degree of integration of an MISFET by improving gate electrode structure. <P>SOLUTION: The MIS field effect transistor of a short channel of self alignment type two-step metal gate electrode structure is constituted in such structure as described below: P-type impurity well region 2 and a trench element isolation region 3 are selectively formed on a p-type silicon substrate 1. A two-step gate electrode (Al) 8 is constituted of a narrow lower electrode 8a regulating a gate length through a gate oxide film 6 and barrier metal 7, and an upper gate electrode 8b formed more broadly than the via diameter on the p-type silicon substrate demarcated by the isolation region 3. An n-type source drain region 4 is self-aligned to the lower electrode 8a and formed on the p-type silicon substrate 1, and an n<SP>+</SP>-type source drain region 5 is self-aligned to the upper gate electrode 8b and formed on the p-type silicon substrate 1. The upper gate electrode 8b and the n<SP>+</SP>-type source drain region 5 are connected with Al wiring 14 having vertically barrier metal 13, 15 through a conduction plug 12 having barrier metal 11. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

The present invention relates to a semiconductor integrated circuit, and more particularly, to a high-speed, high-reliability, high-performance, low-power and highly-integrated short channel MIS field effect transistor. (Applicable not only to insulated gate field effect transistors but also to field effect transistors without a gate insulating film)
Conventionally, in increasing the speed of MIS field effect transistors, emphasis has been placed on miniaturization of the gate electrode length (short channel), and the lifetime is increased due to the hot carrier effect generated due to the strong electric field in the vicinity of the drain. In order to improve the deterioration of transfer conductance, it has been dealt with by forming an LDD (Lightly Doped Drain) structure. In addition, a source / drain region is formed by self-alignment with a fine gate electrode, and this source / drain region is activated by high-temperature heat treatment. Therefore, a polycrystalline silicon (polySi) gate electrode or a polycide gate electrode (source / drain) is used as the gate electrode. Since the use of a salicide to form a low-resistance region, for example, a CoSi / polySi gate electrode), it was difficult to reduce the resistance of the gate electrode. ) Due to the fact that it was difficult to effectively reduce the thickness of the gate insulating film due to the depletion layer generated by the depletion of the above), there was a drawback that the speedup was not achieved despite the short channel.
In addition, since a polycrystalline silicon film is used as the gate electrode, the etching gas permeates through the polycrystalline silicon film with poor crystallinity when etching the phosphosilicate glass (PSG) film during via formation. In addition, since the gate insulating film of the underlying thin film is etched or damaged, current leakage occurs between the gate electrode and the semiconductor substrate. Even if it has, the gate extended over the thick field insulating film (element isolation region) avoiding the formation of vias on the gate electrode immediately above the thin gate insulating film and providing connection with the wiring body Since the electrode wiring is formed, the via is formed on the gate electrode wiring and the connection with the wiring body is provided, there is a disadvantage that high integration is not achieved.
Thus, there is a demand for means capable of forming a short channel MIS field effect transistor that can be further highly integrated, can reduce the resistance of the gate electrode and can be thinned of the gate insulating film, and can achieve higher speed.

31 to 33 are conventional MIS field effect transistors, FIG. 31 is a schematic plan view (however, vias are drawn but wiring is omitted for easy understanding of the drawing), and FIG. 32 is a channel length direction. FIG. 33 is a schematic side sectional view in the channel width direction (qq arrow sectional view in FIG. 31), and uses a p-type silicon substrate. 1 shows a part of a semiconductor integrated circuit including a short-channel N-channel MIS field effect transistor formed as described above, 51 for a p-type silicon substrate, 52 for a p-type impurity well region, and 53 for element isolation region formation. Trench and buried oxide film, 54 is an n-type source / drain region, 55 is an n + -type source / drain region, 56 is a gate oxide film (SiO ₂ ), 57 is a gate electrode (PolySi), 58 is a base oxide film, 59 is a side oxide film Wall, 60 is impurity block Oxide film, 61 is a PSG film, 62 is a barrier metal, 63
Indicates a conductive plug, 64 indicates a barrier metal, 65 indicates an Al wiring, and 66 barrier metal.
In the figure, a trench element isolation region 53 in which an oxide film is embedded in a p-type silicon substrate 51 is selectively provided, and a gate oxide film (on the p-type silicon substrate 51 defined by the trench element isolation region 53 is formed. A gate electrode (polySi) 57 having a gate length of about 100 nm is provided via SiO ₂ ) 56, and the gate electrode 57 in the channel width direction is provided protruding on the trench element isolation region 53, and is formed on the side wall of the gate electrode 57. The p-type silicon substrate 51 is provided with an n-type source / drain region 54 self-aligned with the gate electrode 57 and an n + -type source / drain region 55 self-aligned with the side wall 59. , A part of the n + -type source / drain region 55 and a part of the gate electrode wiring 57 provided protruding from the trench element isolation region 53, and a part of the PSG film 61 provided on the p-type silicon substrate 51 choose MIS field effect of an N-channel LDD structure having a structure in which an Al wiring 65 having a barrier metal (64, 66) is connected to the upper and lower sides through a conductive plug 63 having a barrier metal 62 with a via hole embedded in A transistor is formed.
Therefore, by forming the LDD structure, the electric field in the vicinity of the drain region is relaxed, the deterioration of the transfer conductance over the lifetime due to the hot carrier effect is improved, and a short channel can be formed.
Si) and sidewalls are n-type source / drain regions and n
Since the high-temperature treatment is required for activating the n-type and n + -type source / drain regions in order to form the + -type source / drain regions, the resistance of the gate electrode could not be reduced, Since the polycrystalline silicon layer had to be formed by depletion of the polycrystalline silicon layer, an effective gate insulating film (the thickness of the gate insulating film and the gate electrode) However, there is a disadvantage that the high speed has not been achieved even though the short channel has been achieved due to the difficulty in reducing the thickness of the total depletion layer), and the gate electrode is located on the trench element isolation region. Since the MIS field effect transistor is formed adjacently, the degree of integration does not increase, and high integration is achieved in addition to pattern miniaturization. There was also disadvantage have.

As these improvement measures, not only the gate electrode is formed of a low resistance metal, but a laminated conductive plug is formed on a part of the gate electrode without forming a via, not only miniaturization of the gate electrode length, As other high-speed measures, there have been attempts to form a large part of the source / drain region with a low-resistance metal film, or to achieve pseudo-SOI with an easy process, but it has improved all of the above drawbacks. In the case where the gate electrode is further miniaturized, there is no improvement in the increase in the aspect ratio of the low-resistance metal gate electrode formed by the embedding method.
2001-185729 2002-353244 2003-60202

The problem to be solved by the present invention is that the hot carrier effect is improved in order to obtain a MIS field effect transistor with improved high speed as shown in the prior art.
Although a short channel is achieved by forming a DD structure, a polycrystalline silicon gate electrode (or two layers of polycrystalline silicon and refractory metal silicide) is formed in order to form the source / drain region in a self-aligned manner. Because it was difficult to reduce the resistance of the gate electrode, a depletion layer was also formed on the polycrystalline silicon gate electrode, and it was difficult to effectively reduce the thickness of the gate insulating film. For this reason, the high speed has not been achieved despite the short channel, and vias are provided on the gate electrode wiring provided extending on the trench element isolation region to connect the wiring body. Since it is formed, another MI
When the S field effect transistor is formed, the degree of integration does not increase, and in the case of the MIS field effect transistor that requires a large current, the gate electrode is widened, so that it is separated from the connection portion with the wiring body. Since the resistance of the gate electrode increases at the end of the gate electrode and only a low gate voltage can be applied, the problem is that the effective gate electrode width becomes narrow and the desired source / drain current cannot be obtained, which hinders high integration. The problem is that it is difficult to achieve higher speeds.

The above problem is a field effect transistor in which a source / drain region is provided on a semiconductor substrate or a semiconductor substrate having an insulating film on the bottom, and a gate electrode is provided on the semiconductor substrate directly or via a gate insulating film. A metal gate electrode having a structure in which a wide upper gate electrode portion is provided in self-alignment with the gate electrode portion, and an upper surface of the upper gate electrode portion and a lower surface of the lower gate electrode portion are provided flat; This is solved by the field effect transistor of the present invention.

According to the present invention, a short channel MIS field effect transistor having a self-aligned low-resistance two-stage gate electrode comprising a lower gate electrode portion that determines the channel length and an upper gate electrode portion that is wider than the via diameter is formed. can do.
Therefore, by using a dummy gate electrode, low-concentration and high-concentration source / drain regions that require high-temperature treatment to activate the impurity region can be formed in a self-aligned manner before forming the gate electrode. Since a gate electrode made of metal (Al) can be formed, it is possible to reduce the resistance of the gate electrode and effectively reduce the thickness of the gate oxide film by forming a gate electrode without a depletion layer.
Moreover, since Ta ₂ O ₅ having a high dielectric constant can be used as a gate oxide film, the gate oxide film can be made slightly thicker, and a small current leak between the gate electrode and the semiconductor substrate (or SOI substrate) can be improved. The gate capacitance can be reduced, and at the same time, the gate oxide film can be reduced in terms of SiO ₂ film.
In addition, since it is possible to provide a two-stage gate electrode formed by self-aligning a lower gate electrode portion that defines the gate length and an upper gate electrode portion wider than the via diameter, the electrical characteristics are excellent and an extra portion is provided. High integration is possible because the connection to the wiring body can be formed directly above the required gate electrode without providing the gate electrode wiring, and if the thickness of the lower gate electrode part is adjusted, further gate length can be increased. It is possible to cope with miniaturization, and it is possible to always form a favorable buried gate electrode without increasing the aspect ratio.
In addition, since a via can be formed anywhere in the upper gate electrode portion of the low-resistance two-stage metal gate electrode, a desired gate voltage can be applied, so that effective gate width reduction due to the via formation position can be prevented. it can.
Further, since the upper gate electrode portion can be formed on the low concentration source / drain region, the on-resistance during operation can be reduced, so that higher speed can be expected.
In addition, since the top surfaces of the gate electrode and the insulating film can be formed on a flat surface without a step, an extremely reliable interlayer insulating film and wiring body can be formed.
If the SOI structure is used, most of the source / drain regions can be formed of a metal layer, and the resistance of the source / drain regions can be reduced and the junction capacitance can be reduced.
In the case of using a fully depleted SOI substrate, it is possible to eliminate the depletion layer capacitance and to reduce the threshold voltage by improving the subthreshold characteristics.
That is, various field effect transistors mainly including MIS field effect transistors having a self-aligned two-stage low resistance metal gate electrode structure capable of forming a semiconductor integrated circuit with extremely high speed, high reliability, high performance, low power and high integration. Can be obtained.

According to the MIS field-effect transistor of the present invention, a self-aligned two-stage dummy gate electrode formed on a semiconductor substrate (a manufacturing method will be described in detail separately) is used to perform self-alignment, respectively, with low concentration and high concentration. After forming the source / drain region, a two-stage low-resistance metal gate electrode composed of an upper gate electrode portion and a lower gate electrode portion can be embedded in the opening formed by removing the two-stage dummy gate electrode. The difficulty of embedding due to a large aspect ratio that occurs during the uniform embedding of ultrafine gate electrodes is due to the embedding of two-stage gate electrodes (the upper gate electrode portion having a wide width and the lower gate electrode portion having an extremely narrow width). Can suppress the increase in the aspect ratio and achieve easy embedding (in the current technology, good embedding has an aspect ratio of 4
It is possible to form a high-speed MIS field effect transistor in which the channel length is determined by a fine lower gate electrode portion.
Further, the upper gate electrode portion can be formed of a metal film made of a dense crystal that does not transmit the etching gas for the insulating film in the via opening, and the upper gate electrode portion having a width wider than the via diameter is formed as the lower gate electrode. Since a via is provided in a part on the upper gate electrode portion and can be connected to the wiring body through a conductive plug in which the via is embedded, it can be formed on the field insulating film. It is possible to form a highly integrated MIS field effect transistor without forming an existing gate electrode wiring (for a connection region with a wiring body).
Furthermore, by devising the gate oxide film, the gate electrode material, the material for forming the high concentration source / drain region, the substrate structure, the substrate material, etc., various MIS field effect transistors mainly for each purpose can be obtained. It is also possible to form a field effect transistor.

Throughout the drawings, the same object is denoted by the same reference numeral. However, the oblique lines in the side cross-sectional view are described only in the main insulating film, and show the main part of the invention, so the horizontal and vertical sizes do not show accurate dimensions.
1 to 4 show a first embodiment of the MIS field effect transistor according to the present invention.
FIG. 1 is a plan view (however, vias are drawn but wiring is omitted to make the drawing easier to see), and FIG. 2 is a schematic side sectional view in the channel length direction (sectional view taken along the arrow pp).
3 is a schematic side cross-sectional view (q-q arrow cross-sectional view) in the channel width direction, and FIG. 4 is a schematic enlarged three-dimensional view of the gate electrode, which is a fine N-channel MIS formed using a p-type silicon substrate. 1 shows a part of a semiconductor integrated circuit including a field effect transistor.
P-type silicon substrate of about 10 ¹⁵ cm ⁻³ , 2 is a p-type impurity well region of about 10 ¹⁷ cm ⁻³ , 3 is a trench for forming an isolation region and buried oxide film (SiO ₂ ), 4 is 5 × 10 ¹⁷
An n-type source / drain region of about cm ⁻³ , 5 is an n + type source / drain region of about 10 ²⁰ cm ⁻³ , 6 is a gate oxide film (Ta ₂ O ₅ / SiO ₂ ) of about 6 nm, and 7 is about 6 nm. Barrier metal (TiN), 8 is a two-stage gate electrode (Al), 8a is a lower gate electrode (
The gate length is specified, the gate length is about 40 nm including the barrier metal, and 8b is the upper gate electrode part (the upper surface is flat and formed to have a width slightly wider than the via diameter, and a via is provided on a part thereof. 9 is about 200 nm insulating film (SiO ₂ ), 10 is 400
About 12 nm phosphosilicate glass (PSG) film, 11 is about 20 nm barrier metal (TiN), 12 is conductive plug (W), 13 is about 50 nm barrier metal (TiN), 14 is about 500 nm Al
Wiring (including several percent of Cu), 15 indicates a barrier metal (TiN) of about 50 nm.
In the figure, a p-type impurity well region 2 for controlling a threshold voltage and a trench element isolation region 3 in which an oxide film is buried are selectively provided in a p-type silicon substrate 1.
A thin lower gate for determining the gate length via a gate oxide film (Ta ₂ O ₅ / SiO ₂ ) 6 and a barrier metal (TiN) 7 on a p-type silicon substrate 1 defined by the trench element isolation region 3 A self-aligned two-stage gate electrode (Al) 8 comprising an electrode portion 8a and an upper gate electrode portion 8b formed wider than the via diameter is provided. The p-type silicon substrate 1 has a lower gate electrode portion 8a. The n-type source / drain region 4 is self-aligned and the n + -type source / drain region 5 is provided in self-alignment with the upper gate electrode portion 8b, and the insulating film 9 (SiO ₂₎ is embedded in the two-stage gate electrode 8 flatly. ) And an interlayer insulating film (PSG film) 10 laminated on the insulating film 9, and a via opening the insulating film 9 and the PSG film 10 is formed in a part of the n + type source / drain region 5. Provided via this barrier metal (TiN) 11 A conductive plug (W) 12 embedded in a flat manner is provided, and an Al wiring 14 having barrier metal (TiN, 13, 15) is connected to the conductive plug 12 on the top and bottom, and the flat upper portion of the upper surface of the two-stage gate electrode 8 is connected. Part of the gate electrode portion 8b
Vias are provided to open the PSG film 10 (wider than the width of the lower gate electrode portion 8a),
Conductive plug (W) in which this via is embedded flat via barrier metal (TiN) 11
12 and Al having barrier metal (TiN, 13, 15) above and below the conductive plug 12
An ultrafine N-channel MIS field effect transistor having a structure to which the wiring 14 is connected is formed.
Therefore, although a manufacturing method will be described separately, a dummy gate electrode can be used to form a low-concentration and high-concentration source / drain region that requires high-temperature treatment for activating the impurity region in a self-aligned manner before forming the gate electrode. Low resistance metal (Al
Therefore, it is possible to reduce the resistance of the gate electrode and effectively reduce the thickness of the gate oxide film by forming the gate electrode without a depletion layer.
In addition, since Ta ₂ O ₅ with a high dielectric constant can be used as the gate oxide film, the gate oxide film can be made slightly thicker, improving the minute current leakage between the gate electrode and the semiconductor substrate and reducing the gate capacitance. At the same time, the gate oxide film can be made thinner in terms of SiO ₂ film.
In addition, the lower gate electrode part that defines the gate length and the upper gate electrode part wider than the via diameter (the contact resistance increases as it gets smaller and the gate length cannot be made finer) are self-aligned. Since the two-stage gate electrode formed in this manner is provided, high integration can be achieved by having excellent electrical characteristics and forming a connection with a wiring body directly above the required gate electrode without providing a gate electrode wiring. Is possible,
It is possible to cope with further miniaturization of the gate length, without increasing the aspect ratio (ratio in the depth direction to the horizontal direction) (by adjusting the gate length and thickness of the lower gate electrode part, As the gate length becomes finer, the thickness of the lower gate electrode portion becomes thinner than that of the upper gate electrode portion). It is possible to always form a favorable buried gate electrode.
Further, since a via can be formed anywhere in the upper gate electrode portion of the two-stage metal gate electrode having a low resistance, a desired gate voltage can be applied, so that effective gate width reduction due to the via formation position is prevented. You can also
Further, since the upper gate electrode portion can be formed on the low concentration source / drain region, the on-resistance during operation can be reduced, so that higher speed can be expected.
In addition, since the top surfaces of the gate electrode and the insulating film can be formed on a flat surface without a step, an extremely reliable interlayer insulating film and wiring body can be formed.
As a result, it is possible to obtain a MIS field effect transistor having a self-aligned two-stage low-resistance metal gate electrode structure having high speed, high reliability, high performance, low power and high integration.

A method of manufacturing the MIS field effect transistor in the first embodiment will be described with reference to FIG.
This will be described with reference to FIGS. However, here, only the manufacturing method relating to the formation of the MIS field effect transistor of the present invention is described, and the description of the manufacturing method relating to the formation of various elements (other transistors, resistors, capacitors, etc.) mounted on a general semiconductor integrated circuit. Is omitted.
FIG.
Using normal photolithography technology, a p-type silicon substrate 1 is anisotropically dry etched by about 1 μm using a resist (not shown) as a mask layer to form a trench for forming an element isolation region. Next, the resist (not shown) is removed. Next, an oxide film (SiO ₂ ) is grown by chemical vapor deposition, and chemical mechanical polishing (Che−
A mechanical device polishing (hereinafter abbreviated as “CMP”) is performed to fill the surface and form a trench element isolation region 3. Next, an oxide film (SiO ₂ ) 28 of about 10 nm is grown. Next, boron is ion-implanted into the p-type silicon substrate 1 using a normal photolithography technique, using the trench element isolation region 3 in which a resist (not shown) and an oxide film (SiO ₂ ) are embedded as a mask layer. . Next, the resist (not shown) is removed. Next, heat treatment is performed at a high temperature, the p-type impurity well region 2 is formed, and the threshold voltage is controlled.
FIG.
Next, a polycrystalline silicon film (PolySi) 29 of about 100 nm is grown by chemical vapor deposition. Next, a tungsten film 30 of about 100 nm is grown by sputtering. Next, using a normal photolithography technique, the tungsten film 30 is anisotropically dry etched using a resist (not shown) as a mask layer to form a first trench. Next, the resist (not shown) is removed.
FIG.
Next, a nitride film (Si3N4) 31 of about 40 nm is grown by chemical vapor deposition. Next, the nitride film (Si ₃ N ₄ ) 31 is anisotropically dry-etched to leave the nitride film 31 only on the side walls of the first trench. Next, using the tungsten film 30 and the nitride film 31 as a mask layer, the polycrystalline silicon film (PolySi) 29 is anisotropically dry-etched to form a second trench.
FIG.
Next, a nitride film (Si ₃ N ₄ ) 32 of about 80 nm is grown by chemical vapor deposition. Next, chemical mechanical polishing (CMP) is performed, and a nitride film (Si ₃ N ₄ ) 32 is formed in the first and second trenches.
Embed flat. This nitride film (31, 32) becomes a dummy gate electrode. (Here, the same film is used to form the dummy gate electrode, but in consideration of the masking characteristics of ion implantation, different films may be embedded in the first and second trenches.)
FIG.
Next, the tungsten film 30 is anisotropically dry etched using the nitride films (31, 32) as a mask layer. Next, the polycrystalline silicon film (PolySi) 29 is isotropically dry-etched. Next, using normal photolithography technology, arsenic is ion-implanted using a resist (not shown) and nitride films (31, 32) as a mask layer to define an n + type source / drain region. Next, phosphorus is ion-implanted using the resist (not shown) and the nitride film 32 as a mask layer to define an n-type source / drain region. Next, the resist (not shown) is removed. (Here, the wavy line represents the phosphorus ion implantation region, and the double wavy line represents the arsenic ion implantation region.)
FIG.
Next, the oxide film 28 is isotropically dry etched. Then by chemical vapor deposition,
An oxide film (SiO ₂ ) 9 of about 200 nm is grown. Then, chemical mechanical polishing (CMP) is performed to embed it flat. Next, heat treatment (about 800 ° C.) is performed to activate the n-type and n + -type source / drain regions (4, 5) and control the diffusion layer.
FIG.
Next, the nitride films (31, 32) which are dummy gate electrodes are subjected to anisotropic dry etching. Next, anisotropic dry etching is performed on the oxide film 28. Next, the gate oxide film 6 (Ta
₂ O ₅ / SiO ₂ ). Next, the barrier metal is 6 nm by continuous sputtering.
About 8 nm of Al 8 is grown as a gate electrode with a low resistance of TiN and a low resistance. Then, chemical mechanical polishing (CMP) is performed to fill the first and second trenches flatly.
FIG.
Next, a phosphosilicate glass (PSG) film 10 of about 400 nm is grown by chemical vapor deposition. Next, using an ordinary photolithography technique, the PSG film 10 is selectively dry etched anisotropically using a resist (not shown) as a mask layer to open a via. Next, the resist (not shown) is removed. Next, TiN11 serving as a barrier metal is grown by sputtering. Next, tungsten film 12 is formed by chemical vapor deposition.
To grow. Then, the conductive plug (W) 12 is formed by embedding in the via by chemical mechanical polishing (CMP).
FIG.
Next, TiN13 to be a barrier metal is grown to about 50 nm by sputtering. Next, Al (containing several percent of Cu) 14 to be a wiring is grown to about 500 nm by sputtering.
Next, TiN15 to be a barrier metal is grown to about 50 nm by sputtering. Next, using normal photolithography technology, using a resist (not shown) as a mask layer, barrier metal (TiN), Al (including several percent of Cu), and barrier metal (TiN)
Al wiring 14 with barrier metal (13, 15) on top and bottom by anisotropic dry etching
Form. Next, the resist (not shown) is removed, and a self-aligned two-stage low melting point metal gate type MIS field effect transistor according to the first manufacturing method of the present invention is completed.

5 to 7 show a second embodiment of the MIS field effect transistor according to the present invention.
FIG. 5 is a plan view (however, vias are drawn but wiring is omitted to make the drawing easier to see), FIG. 6 is a schematic side sectional view in the channel length direction (cross-sectional view taken along the pp arrow),
FIG. 7 is a schematic side cross-sectional view (q-q cross-sectional view) in the channel width direction, which is a part of a semiconductor integrated circuit including a fine N-channel MIS field effect transistor formed using a p-type silicon substrate. 1 to 15 are the same as in FIG. 2, 16 is a side wall (SiO ₂ ), 17 is a barrier metal / etching stopper film (TiN), and 18 is an insulating film (SiO ₂ ).
In the figure, the edge of the trench isolation region 3 and the lower gate electrode portion 8a.
The edges (including the barrier metal 7) are formed to coincide with each other (the lower gate electrode portion 8a does not extend to the element isolation region), and the lower gate electrode portion 8a (including the barrier metal 7). A barrier metal / etching stopper film 17 is formed on the bottom of the gate electrode 8a (barrier metal 7).
And the side wall (SiO ₂ ) is formed on the side wall of the lower gate electrode portion 8a (including the barrier metal 7) and the upper gate electrode portion 8b. An MIS having an N-channel LDD structure having the same structure as that of the first embodiment except that an insulating film 18 is formed around (including the barrier metal 7).
A field effect transistor is formed.
Also in this embodiment, the same effect as in the first embodiment can be obtained, and even when the gate length is further miniaturized, it is possible to easily embed the lower electrode portion. (Because no gate insulating film is provided on the side wall of the lower electrode part, an increase in aspect ratio can be prevented.)

As for the method of manufacturing the MIS field effect transistor in the second embodiment, FIG.
A description will be given with reference to FIGS.
FIG.
A gate oxide film 6 (Ta ₂ O ₅ / SiO ₂ ) of about 6 nm is grown on a p-type silicon substrate 1. Next, a barrier metal / etching stopper film (TiN) 17 of about 10 nm is grown. Next, a polycrystalline silicon film (PolySi) 29 of about 100 nm is grown. Next, using a normal photolithography technique, a polycrystalline silicon film 29, TiN17, a gate oxide film 6 (Ta ₂ O ₅ / SiO ₂ ), and p-type silicon are selectively formed using a resist (not shown) as a mask layer. The substrate 1 (about 1 μm) is sequentially subjected to anisotropic dry etching to form a trench for forming an element isolation region. Next, the resist (not shown) is removed.
Next, an oxide film (SiO ₂ ) is grown by chemical vapor deposition, and chemical mechanical polishing (CMP)
The trench element isolation region 3 is formed by embedding it flatly. Next, boron is ion-implanted into the p-type silicon substrate 1 using the trench element isolation region 3 in which a resist (not shown) and an oxide film (SiO 2) are embedded using a normal photolithography technique. Next, the resist (not shown) is removed. Next, heat treatment is performed at a high temperature, the p-type impurity well region 2 is formed, and the threshold voltage is controlled.
FIG.
Next, the oxide film 3 buried in the trench is anisotropically etched by about 100 nm so as to substantially match the surface of the p-type silicon substrate 1. Next, using an ordinary photolithography technique, the polycrystalline silicon film 29 and TiN17 are sequentially dried by using the trench element isolation region 3 embedded with a resist (not shown) and an oxide film (SiO ₂ ) as a mask layer. Etch. Next, the resist (not shown) is removed. Next, using normal photolithography technology, phosphorus is ion-implanted using the trench element isolation region 3 in which the resist (not shown), the polycrystalline silicon film 29 and the oxide film (SiO ₂ ) are embedded as a mask layer, and n A type source / drain region 4 is defined. Next, the resist (not shown) is removed. Next, the unnecessary gate oxide film 6 (Ta ₂ O ₅ / SiO ₂ ) is anisotropically dry etched using the polycrystalline silicon film 29 as a mask layer. Next, an oxide film (SiO ₂ ) is grown by chemical vapor deposition. Next, anisotropic dry etching is performed to form sidewalls 16 on the side walls of the polycrystalline silicon film 29. Then 10nm
An oxide film (SiO ₂ , not shown) for ion implantation of a certain degree is grown. Next, using a normal photolithography technique, a resist (not shown), a polycrystalline silicon film 29,
Arsenic ions are implanted using the trench isolation region 3 in which the sidewall 16 and the oxide film (SiO ₂ ) are buried as a mask layer to define the n + -type source / drain region 5. Next, the resist (not shown) is removed. Next, an oxide film (not shown) for ion implantation is removed by etching. Next, heat treatment (about 800 ° C.) is performed to activate the n-type and n + -type source / drain regions (4, 5) and control the diffusion layer.
FIG.
Next, an oxide film (SiO ₂ ) 9 having a thickness of about 120 nm is grown by chemical vapor deposition. Then, chemical mechanical polishing (CMP) is performed to embed it flat.
FIG.
Next, a selective chemical vapor deposition tungsten film of about 150 nm is formed on the polycrystalline silicon film 29.
Growing 33. Next, a tungsten film 34 of about 40 nm is grown by chemical vapor deposition. Next, the tungsten film 34 is anisotropically dry etched to leave the tungsten film 34 only on the sidewalls of the selective chemical vapor deposition tungsten film 33. At this time, the selective chemical vapor deposition tungsten film 33 may be slightly etched.
FIG.
Next, an oxide film (SiO ₂ ) 18 of about 150 nm is grown by chemical vapor deposition. Then, chemical mechanical polishing (CMP) is performed to embed it flat.
FIG.
Next, using the tungsten film (33, 34) as a mask layer, the oxide film 18 is anisotropically etched on the entire surface by about 50 nm. Next, with the oxide film 18 as a mask layer, the tungsten films (33, 34) are anisotropically dry etched to form a first trench. Next, the exposed polycrystalline silicon film 29 is anisotropically dry etched to form a second trench.
FIG.
Next, TiN 7 of about 6 nm as a barrier metal and Al 8 of about 80 nm serving as a low-resistance gate electrode are grown by continuous sputtering. Then chemical mechanical polishing (CMP
) And buried in the first and second trenches flatly.
FIG.
Next, a phosphosilicate glass (PSG) film 10 of about 400 nm is grown by chemical vapor deposition. Next, using an ordinary photolithography technique, the PSG film 10 is selectively dry etched anisotropically using a resist (not shown) as a mask layer to open a via. Next, the resist (not shown) is removed. Next, TiN11 serving as a barrier metal is grown by sputtering. Next, tungsten film 12 is formed by chemical vapor deposition.
To grow. Then, the conductive plug (W) 12 is formed by embedding in the via by chemical mechanical polishing (CMP).
FIG.
Next, TiN13 to be a barrier metal is grown to about 50 nm by sputtering. Next, Al (containing several percent of Cu) 14 to be a wiring is grown to about 500 nm by sputtering.
Next, TiN15 to be a barrier metal is grown to about 50 nm by sputtering. Next, using normal photolithography technology, using a resist (not shown) as a mask layer, barrier metal (TiN), Al (including several percent of Cu), and barrier metal (TiN)
Al wiring 14 with barrier metal (13, 15) on top and bottom by anisotropic dry etching
Form. Next, the resist (not shown) is removed to complete a self-aligned two-stage low melting point metal gate type MIS field effect transistor according to the second manufacturing method of the present invention.

FIG. 8 is a schematic sectional side view (channel length direction) of the third embodiment of the MIS field effect transistor of the present invention, including a fine N channel MIS field effect transistor formed using a p-type silicon substrate. A part of the semiconductor integrated circuit is shown. 1 to 15 and 17 are the same as those shown in FIGS. 2 and 6, and 19 is a side wall (SiO ₂ ).
In the figure, a barrier metal / etching stopper film 17 is formed on the bottom of the lower gate electrode portion 8a (including the barrier metal 7), and the gate insulating film 6 is formed on the lower gate electrode portion 8a (barrier metal 7). 7), and the lower gate electrode portion 8a (including the barrier metal 7) has a smooth curved surface from the upper gate electrode portion 8b (including the barrier metal 7). An N-channel LDD structure MIS field effect transistor having substantially the same structure as that of the first embodiment is formed except that a sidewall (Si 2 _O 2) 19 is formed so as to be formed in a thin column shape. ing.
In this embodiment, since the gate electrode is formed in a modified two-stage gate structure, the manufacturing process is somewhat complicated, but the lower gate electrode portion 8a can be embedded very easily. The same effect can be obtained.

FIG. 9 is a schematic sectional side view (channel length direction) of the fourth embodiment of the MIS field effect transistor of the present invention, including a fine N channel MIS field effect transistor formed using a p-type silicon substrate. A part of the semiconductor integrated circuit is shown. 1 to 18 are the same as those shown in FIGS. 2 and 6, and 20 is a barrier metal (TiN).
In the figure, N having the same structure as that of the second embodiment, except that the lower gate electrode portion 8a and the upper gate electrode portion 8b are formed in a self-aligned manner by separate manufacturing processes.
An MIS field effect transistor having a channel LDD structure is formed. Here, the same electrode material is used for the lower gate electrode portion 8a and the upper gate electrode portion 8b, but different electrode materials may be used.
Also in this embodiment, the same effect as in the first embodiment can be obtained.

FIG. 10 is a schematic sectional side view (channel length direction) of the fifth embodiment of the MIS field effect transistor according to the present invention. The p is provided on the p-type silicon substrate via an insulating film.
2 shows a part of a semiconductor integrated circuit including an SOI-type fine N-channel MIS field effect transistor formed by using a type SOI (Silicon On Insulator) substrate. Reference numeral 21 denotes a p-type SOI substrate having a thickness of about 50 nm, and 22 denotes an oxide film (SiO ₂ ) for SOI.
In the figure, an N channel having the same structure as that of the first embodiment is used except that a p type SOI substrate 21 provided on an oxide film (SiO ₂ ) 22 formed on a p type silicon substrate is used. An MIS field effect transistor having an LDD structure is formed.
In this embodiment, in addition to the effects of the first embodiment, the junction capacitance of the source / drain region can be reduced, and further speedup can be achieved. Further, since the gate structure is formed on the thin SOI substrate, the SOI substrate can be completely depleted, so that the depletion layer capacitance between the inversion layer under the gate oxide film and the substrate can be eliminated. Since the voltage applied to the gate electrode can be applied only between the gate electrode and the inversion layer, the subthreshold characteristic can be improved, the threshold voltage can be reduced, and the power can be reduced.

FIG. 11 is a schematic sectional side view (channel length direction) of the sixth embodiment of the MIS field effect transistor of the present invention. The p is provided on a p-type silicon substrate via an insulating film.
1 shows a part of a semiconductor integrated circuit including an SOI type fine N-channel MIS field effect transistor formed using a type SOI substrate.
2 is the same as FIG. 2, FIG. 6 and FIG. 10, 23 is a barrier metal (TiN), 24 is a metal source / drain region (W), and 25 is an oxide film (SiO ₂ ).
The metal source / drain region in the present invention is a metal film or alloy containing no impurity region unlike a conventional metal source / drain region made of a compound (silicide) of an impurity region and a metal film formed on a silicon semiconductor substrate. This is the region of the film only.
In the drawing, the trench element isolation region 3 in which the oxide film is buried is formed to the same height as the lower gate electrode portion 8a, and the side walls of the lower gate electrode portion 8a and the trench element isolation region 3 are formed on the side. The wall (SiO ₂ ) is formed, and the n-type and n + -type source / drain regions (under the sidewalls (SiO ₂ ))
4 and 5) are formed, and a barrier metal (TiN) 23 is provided on the side surface and bottom surface instead of the SOI substrate 21 provided with most of the n + -type source / drain regions 5. An N channel having substantially the same structure as that of the fifth embodiment except that a metal source / drain region (W) 24 is formed and connected to the Al wiring 14 through the conductive plug 12 on the metal source / drain region 24. MI of LDD structure of
An S field effect transistor is formed.
In this embodiment, the same effect as in the first and fifth embodiments can be obtained, and the resistance of the source / drain region can be reduced, so that further increase in speed can be expected.

FIG. 12 is a schematic sectional side view (channel length direction) of the seventh embodiment of the MIS field effect transistor of the present invention, using a p-type epitaxial silicon layer selectively formed on a p-type silicon substrate. 1 shows a part of a semiconductor integrated circuit including a formed pseudo SOI type fine N-channel MIS field effect transistor;
15, 23 and 24 are the same as those shown in FIGS. 2 and 11, and 26 is a p-type epitaxial silicon layer.
In the figure, p is selectively formed between trench element isolation regions 3 in which an oxide film is embedded.
A type epitaxial silicon layer 26 is provided, and the p type epitaxial silicon layer 26 is provided with a p type impurity well region, n type and n + type source / drain regions (4, 5).
) In contact with the n + -type source / drain region 5 and having a barrier metal (TiN) 23 on the side surface and bottom surface on the trench isolation region 3 (
W) 24 is selectively formed, and the conductive plug 12 is formed on the metal source / drain region 24.
An MIS field-effect transistor having an N-channel LDD structure having substantially the same structure as that of the first embodiment is formed except that the connection to the Al wiring 14 is made via the.
In this embodiment, the same effect as that of the first embodiment can be obtained, and the resistance and capacitance of the source / drain region can be reduced, so that further increase in speed can be expected.

FIG. 13 is a schematic side sectional view (channel length direction) of the eighth embodiment of the MIS field effect transistor of the present invention, and shows a fine N formed using a p-type silicon substrate.
1 shows a part of a semiconductor integrated circuit including a channel MIS field effect transistor, wherein 1 to 15, 19 and 20 are the same as those in FIGS. 2, 8 and 9, and 27 is an insulating film (Si ₃ N ₄ ). Is shown.
In the figure, a p-type impurity well region 2 for controlling a threshold voltage and a trench element isolation region 3 in which an oxide film is buried are selectively provided in a p-type silicon substrate 1.
A trench is selectively provided in the p-type silicon substrate 1 defined by the trench element isolation region 3, and a thin side wall 19 (to enhance insulation), a gate oxide film (Ta ₂ O ₅ / SiO ₂ ) is provided in the trench. ₂ ) A lower gate electrode portion 8a is flatly embedded via 6 and a barrier metal (TiN) 7, and is in contact with the upper surface of the lower gate electrode portion 8a, and is formed of a p-type via an insulating film (Si ₃ N ₄ ). An upper gate electrode portion 8b having a barrier metal (TiN) 20 extending on the silicon substrate 1 is provided, and is self-aligned with the lower gate electrode portion 8a so that an n + -type source / drain is formed on the p-type silicon substrate 1. A region 5 is provided, an n-type source / drain region 4 is provided at the bottom of the n + -type source / drain region 5, and an insulating film 9 and a PSG film 10 are opened in a part of the n + -type source / drain region 5. A via is provided and this via Barrier metal (TiN) 11 to flat conductive plug (W) 12 embedded is provided via the barrier metal vertically to the conductive plug 12 (
Al wiring 14 having TiN, 13, 15) is connected, and vias having a PSG film 10 are provided in a part of the flat upper gate electrode portion 8b on the upper surface of the two-stage gate electrode (lower gate). A conductive plug (W) 12 in which this via is flatly buried via a barrier metal (TiN) 11 is provided, and the barrier metal (TiN, 13, 15) is provided above and below the conductive plug 12. ) N-channel MIS field-effect transistors having a structure in which Al wirings 14 having the same structure are connected are formed.
Even in the present embodiment, although the manufacturing process is different, the effects of the first embodiment can be obtained.

FIG. 14 is a schematic side sectional view (channel length direction) of the ninth embodiment of the MIS field effect transistor of the present invention, using a p-type epitaxial silicon layer selectively formed on a p-type silicon substrate. 1 shows a part of a semiconductor integrated circuit including a formed fine N-channel MIS field effect transistor; 1 to 15, 20, 26, 27
The same thing as FIG.2, FIG.9, FIG12 and FIG.13 is shown.
In the figure, a trench is formed in a p-type silicon substrate 1 to form a thin sidewall 19 (to increase insulation), a gate oxide film (Ta ₂ O ₅ / SiO ₂ ) 6 and a barrier metal (TiN) 7. Instead of embedding the lower gate electrode portion 8a via the n + type source / drain region 5 is provided in the selectively formed p type epitaxial silicon layer 26, and n + type source / drain region 5 is formed at the bottom of the n + type source / drain region 5. Type source / drain region 4
An MIS field effect transistor having an N-channel LDD structure having substantially the same structure as that of the eighth embodiment is formed except that is provided.
Even in the present embodiment, although the manufacturing process is different, the effects of the first embodiment can be obtained.

In the description of the above embodiment, an N-channel MIS field effect transistor has been described. However, the present invention may be applied to a P-channel MIS field effect transistor (however, the hot carrier effect need not be considered, It is not necessary to provide a source / drain region having a concentration, and the present invention can be applied to C-MOS and bi-C-MOS.
Further, although TiN is used as the barrier metal, it is not limited to this, and the conductive plug is not limited to W. Furthermore, the gate electrode is not limited to Al, the metal source / drain region is not limited to W, and any low resistance metal or metal compound that can obtain the same characteristics can be used. Also good.
In the present invention, a self-aligned two-stage gate electrode is described. However, if the manufacturing process of the present invention is applied, a three-stage gate electrode can be formed. A two-stage gate structure having a deformed shape as described above may be used, and the present invention is established in any case.
Also, in the manufacturing method, two embodiments have been described. However, the present invention is not limited to these manufacturing methods, and the present invention can be manufactured if a self-aligned two-stage dummy gate electrode can be formed.
Further, the present invention is applied to the gate electrode of a MIS field effect transistor having a gate insulating film, but the junction field effect transistor having no gate insulating film and the Schottky junction field effect transistor using a metal / semiconductor junction are used. (ME
SFET) and gate electrodes such as high electron mobility transistors, or various semiconductor memory cells (flash memory, EEPROM, etc.), thin film transistors (TF) for liquid crystal display or organic EL (electroluminescence) display
T), gate electrodes of organic transistors, etc. (or electrodes having different names but similar functions) can also be applied.

Schematic plan view of the first embodiment of the MIS field effect transistor of the present invention Schematic side sectional view of first embodiment of MIS field effect transistor of the present invention (channel length direction) Schematic side sectional view of first embodiment of MIS field effect transistor of the present invention (channel width direction) Schematic enlarged three-dimensional view of the gate electrode of the first embodiment in the MIS field effect transistor of the present invention Schematic plan view of the second embodiment of the MIS field effect transistor of the present invention Schematic side sectional view of second embodiment of MIS field effect transistor of the present invention (channel length direction) Schematic side sectional view of second embodiment of MIS field effect transistor of the present invention (channel width direction) Schematic side sectional view of the third embodiment of the MIS field effect transistor of the present invention (channel length direction) Schematic side sectional view of fourth embodiment of MIS field effect transistor of the present invention (channel length direction) Schematic side sectional view of the fifth embodiment of the MIS field effect transistor of the present invention (channel length direction) Schematic side sectional view of the sixth embodiment of the MIS field effect transistor of the present invention (channel length direction) Schematic side sectional view of the seventh embodiment of the MIS field effect transistor of the present invention (channel length direction) Schematic side sectional view of the eighth embodiment of the MIS field effect transistor of the present invention (channel length direction) Schematic side sectional view of the ninth embodiment of the MIS field-effect transistor of the present invention (channel length direction) Process sectional drawing of the 1st manufacturing method in the MIS field effect transistor of this invention Process sectional drawing of the 1st manufacturing method in the MIS field effect transistor of this invention Process sectional drawing of the 1st manufacturing method in the MIS field effect transistor of this invention Process sectional drawing of the 1st manufacturing method in the MIS field effect transistor of this invention Process sectional drawing of the 1st manufacturing method in the MIS field effect transistor of this invention Process sectional drawing of the 1st manufacturing method in the MIS field effect transistor of this invention Process sectional drawing of the 1st manufacturing method in the MIS field effect transistor of this invention Process sectional drawing of the 1st manufacturing method in the MIS field effect transistor of this invention Process sectional drawing of the 2nd manufacturing method in the MIS field effect transistor of this invention Process sectional drawing of the 2nd manufacturing method in the MIS field effect transistor of this invention Process sectional drawing of the 2nd manufacturing method in the MIS field effect transistor of this invention Process sectional drawing of the 2nd manufacturing method in the MIS field effect transistor of this invention Process sectional drawing of the 2nd manufacturing method in the MIS field effect transistor of this invention Process sectional drawing of the 2nd manufacturing method in the MIS field effect transistor of this invention Process sectional drawing of the 2nd manufacturing method in the MIS field effect transistor of this invention Process sectional drawing of the 2nd manufacturing method in the MIS field effect transistor of this invention Schematic plan view of a conventional MIS field effect transistor Schematic side sectional view of a conventional MIS field effect transistor (channel length direction) Schematic side cross-sectional view of conventional MIS field effect transistor (channel width direction)

Explanation of symbols

1 p-type silicon substrate 2 p-type impurity well region 3 trench for element isolation region formation and buried oxide film (SiO ₂ )
4 n-type source / drain region 5 n + -type source / drain region 6 gate oxide film (Ta ₂ O ₅ / SiO ₂ )
7 Barrier metal (TiN)
8 Gate electrode (Al)
8a Lower gate electrode (Al)
8b Upper gate electrode (Al)
9 Insulating film (SiO ₂ )
10 Phosphosilicate glass (PSG) film
11 Barrier metal (TiN)
12 Conductive plug (W)
13 Barrier metal (TiN)
14 Al wiring (including several% Cu)
15 Barrier metal (TiN)
16 Side wall (SiO ₂ )
17 Barrier metal and etching stopper film (TiN)
18 Insulating film (SiO ₂ )
19 Side wall (SiO ₂ )
20 Barrier metal (TiN)
21 p-type SOI substrate
22 Insulating film for SOI (SiO ₂ )
23 Barrier metal (TiN)
24 Metal source / drain region (W)
25 Insulating film (SiO ₂ )
26 p-type epitaxial silicon layer
27 Nitride film (Si ₃ N ₄ )
28 Insulating film (SiO ₂ )
29 PolySi film
30 Tungsten film (W)
31 Nitride film (Si ₃ N ₄ )
32 Nitride film (Si ₃ N ₄ )
33 Selective chemical vapor deposition tungsten film (W)
34 Chemical vapor deposition tungsten film (W)

Claims (2)

A field effect transistor in which a source / drain region is provided on a semiconductor substrate or a semiconductor substrate having an insulating film on the bottom, and a gate electrode is provided on the semiconductor substrate directly or via a gate insulating film. A metal gate electrode having a structure in which the upper gate electrode portion is provided in a wide range by self-alignment, and the upper surface of the upper gate electrode portion and the lower surface of the lower gate electrode portion are provided flat. A field effect transistor characterized by. A low concentration source / drain region is provided in self-alignment with the lower gate electrode portion,
A high-concentration source / drain region is provided in self-alignment with the upper gate electrode portion, and is connected to a wiring body at a part of the upper gate electrode portion. The field effect transistor according to claim 1.

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