JP2003188376A - Mis field-effect transistor and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To form a super-fine MIS field-effect transistor of a low-melting-point-metal gate type having a gate length shorter than the resolution limit of a photo-resist. <P>SOLUTION: This super-fine MIS field-effect transistor comprises a trench isolation region 3 which is selectively formed in a p-type silicon substrate and in which an oxide film is filled; a gate electrode (Al) 8 formed on the p-type silicon substrate demarcated by the trench isolation region 3 via a gate insulating film 6 and a barrier metal 7, and having a gate length shorter than the resolution limit of a photo-resist (formed by forming a trench having a width that corresponds to the resolution limit of the photo-resist, forming an insulating film on the inside wall to form a finer trench, and filling this trench); a first insulating film 9 formed on the side face of the gate electrode 8 and both side faces of which are formed perpendicular to the p-type silicon substrate 1; a second insulating film 10 formed adjoining the first insulating film 9, and in the p-type silicon substrate, n-type source/drain regions 4 formed underneath the first insulating film 9 self-aligned by the gate electrode 8; and n<SP>+</SP>-type source/drain regions 5 formed underneath the second insulating film 10 self-aligned by the first insulating film 9. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit,
In particular, it relates to a highly integrated, high speed, high performance, low power and highly reliable short channel MIS field effect transistor. Conventionally, in increasing the speed of a MIS field effect transistor,
Gate length emphasis on miniaturization (channel length) is placed, LDD (L ightly D in order to improve the deterioration of the transmission conductance of the lifetime due to hot carrier effect caused for strong electric field in the vicinity of the drain of this time becomes a problem ope
It has been addressed by forming the d D rain) structure. It seems that electrical countermeasures for miniaturization of the gate length will be able to sufficiently cope with the future, but on the other hand, the technology for miniaturization of the gate length is approaching its limit. Conventionally, the gate length has been determined by anisotropic dry etching of a gate electrode material using a photoresist pattern resolved by photolithography as a mask layer. However, at the present time, the lower limit value for stable resolution of photoresist is about 100 nm, which is approaching the gate length value that is desired to be used in mass production technology, and further miniaturization can be achieved only by relying on the resolution limit of photoresist. Is getting harder. Further, there is a drawback that speeding up is not achieved despite the miniaturization of the gate length, and there is a drawback that high integration is not achieved other than the miniaturization of the pattern. Therefore, there is a demand for a means capable of forming an ultrafine short channel MIS field effect transistor having a gate length equal to or shorter than the resolution limit of photoresist and capable of further speeding up.

[0002]

31 and 32 show a conventional MIS field effect transistor, FIG. 31 is a schematic side sectional view in the channel length direction, and FIG. 32 is a schematic side sectional view in the channel width direction, showing a p-type silicon substrate. 1 shows a part of a semiconductor integrated circuit including a short-channel N-channel MIS field effect transistor formed by using, 51 is a p-type silicon substrate, 52 is a p-type impurity well region, and 53 is an element isolation region formation Trench and buried oxide film, 54 n-type source / drain region, 55 n ⁺ type source / drain region, 56 gate oxide film (SiO ₂ ), 57 gate electrode (WSi / PolySi), 58 underlayer oxide film, 59 is a side wall, 60 is an impurity blocking oxide film, 61 is a BPSG film, 62 is a barrier metal, 63 is a conductive plug, 64 is a barrier metal, 65 is an AlCu wiring, and 66 is a barrier metal. In the figure, a trench element isolation region 53 in which an oxide film is buried in a p-type silicon substrate 51 is selectively provided, and a gate oxide film (on the p-type silicon substrate 51 defined by the trench element isolation region 53 SiO ₂ )
A gate electrode (WSi / polySi) 57 having a gate length of about 100 nm is provided via 56, and the gate electrode 57 in the channel width direction is provided so as to protrude above the trench isolation region 53, and is formed on the side wall of the gate electrode 57 above. is provided sidewall 59 formed bent, the p-type silicon substrate 51, self-aligned to the gate electrode 57 by self-alignment in the n-type source drain region 54 and the side wall 59 n ⁺ -type source and drain A region 55 is provided, and a barrier metal (upper and lower) is provided via a conductive plug 63 having a barrier metal 62 in which a via is formed by selectively opening a part of a BPSG film 61 provided on a p-type silicon substrate 51. 64, 66) with AlCu wiring 65
The MIS field-effect transistor of the N-channel LDD structure is formed by the structure in which is connected. Although the manufacturing method is not shown, the gate electrode 57 is formed to have a gate length set by the resolved photoresist, and all are formed to have the same film thickness of about 300 nm. Therefore, since only the gate electrode having the gate length set by the resolved photoresist pattern can be formed, the MIS field effect transistor having the further short channel cannot be formed. Also, L
By forming the DD structure, the electric field in the vicinity of the drain region is relaxed, the deterioration of the transfer conductance over the lifetime due to the hot carrier effect is improved, and a short channel can be formed, but the gate electrode and the side wall formed in advance can be formed. In order to form the n-type source / drain region and the n ⁺ -type source / drain region by self-alignment,
Since high temperature treatment is required to activate the n-type and n ⁺ -type source / drain regions, the resistance of the gate electrode and the source / drain regions could not be reduced, and the gate electrode was a polycrystalline silicon layer having a semiconductor layer Since the polycrystalline silicon layer is depleted due to the existence of the depletion layer, the effective gate insulating film (gate insulating film thickness and gate electrode depletion layer thickness However, there is a drawback that speeding up has not been achieved in spite of trying to make a short channel because it was difficult to make a thin film, and the gate electrode is provided to extend over the trench element isolation region. So it is next to another M
In the case where the IS field effect transistor is formed, the degree of integration does not increase, and there is a drawback that high integration is not achieved other than the pattern miniaturization.

[0003]

The problem to be solved by the present invention is, as shown in the conventional example, that a gate electrode is formed by a resolved photoresist pattern. A MIS field effect transistor having a fine gate length (channel length) could not be formed, and an LDD structure with an improved hot carrier effect was formed to obtain a MIS field effect transistor with improved high-speed performance. Although it has achieved channelization, a polycrystalline silicon gate electrode (actually a double gate electrode of polycrystalline silicon and a refractory metal) must be used to form the source / drain region in a self-aligned and fine pattern. It was difficult to reduce the resistance of the gate electrode and the source / drain region because it had to be done. Depletion layer in the electrode is formed,
Due to the difficulty of effective thinning of the gate insulating film, etc., the short channel has been achieved but the speed has not been achieved, or high integration has not been achieved other than pattern miniaturization. However, the problem that it is difficult to achieve even higher speeds has become prominent.

[0004]

Means for Solving the Problems The above-mentioned problems are solved by a semiconductor substrate, a gate insulating film selectively provided on the semiconductor substrate, a barrier metal layer provided on the gate insulating film, and the barrier metal. A gate electrode provided on the layer,
A first insulating film self-aligned with the gate electrode and provided on both sides of the gate electrode substantially perpendicularly to the semiconductor substrate; and a first insulating film self-aligned with the first insulating film. A second insulating film (or a conductive film) provided in contact with the insulating film, and a low-concentration source / drain region provided in the semiconductor substrate below the first insulating film in self-alignment with the gate electrode. And a high-concentration source / drain region provided in the semiconductor substrate in self-alignment with the first insulating film and in contact with the low-concentration source / drain region. It

[0005]

[Operation] That is, the essential points of configuring the MIS field effect transistor of the present invention are: (1) First dummy gate electrode (polycrystalline silicon film via gate oxide film and barrier metal) (2) First dummy High-concentration source / drain region formed by self-alignment with the gate electrode (3) Flat second insulating film formed by self-alignment with the first dummy gate electrode (4) Removing the first dummy gate electrode First trench formed by (5) Insulating film formed on the sidewall of the first trench (the original sidewall is formed on the sidewall of the convex putter, but the sidewall insulating film of the present invention is formed on the sidewall of the concave putter). It's like a reverse side wall, and by anisotropic dry etching,
The lower side surface is formed perpendicular to the semiconductor substrate to be self-aligned with the first trench, while the upper side surface is curved. (6) The width of the lower part formed by self-alignment by the side wall insulating film of the first trench is twice as small as that of the side wall insulating film, and the upper part is formed in almost the same state as the first trench. Second trench gate (7) A second dummy gate electrode that is flatly buried in the second trench (even if the second dummy gate electrode is flatly buried in this second trench, the reverse taper structure The side wall of the second dummy gate electrode must be formed so that the side surface of the second dummy gate electrode is vertical to the semiconductor substrate in order to eliminate the reverse taper structure. The upper surface is also flattened.This improvement enables self-alignment between the high-concentration source / drain region and the second dummy gate electrode to form a low-concentration source / drain region.) (8) Sidewall insulation Formed by removing the film Third trench (9) Low-concentration source / drain region under the third trench formed in self-alignment with the second dummy gate electrode (10) First insulation flatly embedded in the third trench Film (11) Fourth trench formed by removing the second dummy gate electrode (similar to the second trench) (12) Gate electrode made of low melting point metal that is flatly embedded in the fourth trench It consists of the above. A further point is that in order to keep the aspect ratio of each trench to 4 or less (preferably 2 or less), the depth of each trench is formed to be fairly shallow (that is, the embedded conductive film or insulating film is thin). , The gate oxide film and the barrier metal (also as the etching stopper film) are formed in the initial stage and have a structure existing only on the bottom surface of the gate electrode.
As seen in (Chemical mechanical polishing planarization process), the structure in which the gate oxide film and the barrier metal are formed on the side surface and the bottom surface of the gate electrode (the structure in which the aspect ratio is extremely high when the gate electrode is formed) is not taken. Also, since the gate electrode to be embedded is made quite thin, the gate electrode wiring part that connects to the wiring body has a problem of etching in the opening of the via for forming the conductive plug (the gate electrode of the thin film is also considerably etched, and the side contact In order to prevent the contact resistance from increasing, the contact resistance is increased. Therefore, the N-channel MIS electric field of the LDD structure having an ultrafine gate electrode below the resolution limit of the photoresist formed by self-aligning each element on the first dummy gate electrode which is the resolution limit of the photoresist. It is possible to form an effect transistor. Further, by devising the material for forming the gate oxide film, the gate electrode, the high concentration source / drain region, the forming method, the substrate structure, etc.
It is also possible to form an IS field effect transistor.

[0006]

EXAMPLES The present invention will be described in detail below with reference to illustrated examples. 1 is a schematic side sectional view (channel length direction) of a first embodiment of a MIS field effect transistor of the present invention, and FIG. 2 is a schematic side sectional view (channel) of a first embodiment of a MIS field effect transistor of the present invention. Width direction),
3 is a schematic side sectional view of a second embodiment of the MIS field effect transistor of the present invention (in the channel length direction), and FIG. 4 is a schematic side sectional view of a second embodiment of the MIS field effect transistor of the present invention (the channel). Width direction), FIG. 5 is a schematic side sectional view of the third embodiment of the MIS field effect transistor of the present invention (channel width direction), and FIG. 6 is an MI of the present invention.
FIG. 8 is a schematic side sectional view (channel width direction) of the fourth embodiment of the S field effect transistor, and FIG. 7 is a schematic side sectional view (channel length direction) of the fifth embodiment of the MIS field effect transistor of the present invention. Is a schematic side sectional view of the sixth embodiment of the MIS field-effect transistor of the present invention (channel length direction), and FIG. 9 is a schematic side sectional view of the seventh embodiment of the MIS field-effect transistor of the present invention (channel length direction). ), FIG. 10 is a schematic side sectional view of the eighth embodiment of the MIS field effect transistor of the present invention (in the channel length direction), and FIG. 11 is a schematic side sectional view of the ninth embodiment of the MIS field effect transistor of the present invention. (Channel length direction), FIG. 12 is a schematic side cross-sectional view of the tenth embodiment of the MIS field effect transistor of the present invention (channel length direction), and FIGS. Sectional views of a first method for manufacturing the light of the MIS field-effect transistor, 23 to
FIG. 30 is a process sectional view of the second manufacturing method of the MIS field effect transistor of the present invention. The same object is denoted by the same symbol throughout the drawings. However, since the diagonal lines in the side sectional view are shown only in the main insulating film and show the essential part of the invention, the sizes in the horizontal direction and the vertical direction do not show accurate dimensions. 1 and 2 show a first embodiment of the MIS field-effect transistor of the present invention. FIG. 1 is a schematic side sectional view in the channel length direction, and FIG. 2 is a schematic side sectional view in the channel width direction. 1 shows a part of a semiconductor integrated circuit including an ultra-fine N-channel MIS field effect transistor formed by using a substrate, where 1 is a p-type silicon substrate of about 10 ¹⁵ cm ⁻³ , and 2 is 10 ¹⁶ cm p-type impurity-well region of about ^-3, the element isolation region forming trench and buried oxide film 3 (SiO _2), is 10 ¹⁷ cm ^-3 of about n-type source drain region 4, 5 about 10 ²⁰ cm ^-3 N ⁺ type source / drain region,
6 is a gate oxide film (SiO ₂ / Ta ₂ O ₅ ) of about 12 nm, 7 is 20
Barrier metal and etching stopper film (TiN
), 8 is a gate electrode (Al) having a gate length (channel length) of about 30 nm, 9 is a first insulating film (sidewall oxide film, SiO ₂ ), 10
Is a second insulating film (SiO ₂ ), 11 is a phosphosilicate glass (PSG) film of about 500 nm, 12 is a barrier metal (TiN) of about 20 nm,
13 is a conductive plug (W), 14 is a barrier metal (TiN) of about 50 nm, 15 is an AlCu wiring of about 500 nm (containing several% of Cu), and 16 is a barrier metal (TiN) of about 50 nm. . In the figure, a trench element isolation region 3 having an oxide film buried in a p-type silicon substrate 1 is selectively provided, and a gate oxide film is formed on the p-type silicon substrate 1 defined by the trench element isolation region 3. (SiO ₂ / Ta ₂ O ₅ ) 6
And barrier metal (also etching stopper film, TiN)
A gate electrode (Al) 8 having a gate length (channel length) less than or equal to the resolution limit of the photoresist is provided via the via 7, and both side surfaces of the gate electrode 8 are perpendicular to the p-type silicon substrate 1. Formed on the first surface having a flat upper surface
Insulating film (sidewall oxide film, SiO ₂ ) 9 of
The second insulating film (SiO ₂ ) 10 is provided in contact with the insulating film 9 of the p-type silicon substrate 1, and the p-type silicon substrate 1 has p
A type impurity well region is provided, self-aligned with the gate electrode 8 and under the first insulating film 9, and self-aligned with the n-type source / drain region 4 and the first insulating film 9 under the second insulating film 10. n
^{A +} type source / drain region 5 is provided, and a flat interlayer insulating film (PSG) 11 is formed on the flat gate electrode 8, the first insulating film 9 and the second insulating film 10. A via is provided in a part of the n ⁺ -type source / drain region 5 to open the interlayer insulating film 11, and the via is flatly buried via a barrier metal (TiN) 12 to form a conductive plug (W). An ultrafine N-channel MIS field effect transistor having a structure in which 13 is provided and AlCu wirings 15 having barrier metals (TiN, 14, 16) are connected to the conductive plug 13 at the upper and lower sides is formed. Although the manufacturing method will be described in detail later, the gate electrode of the present invention includes a double dummy gate electrode (first and second dummy gate electrodes) and a double damascene method (embedding formation of the second dummy gate electrode and the final gate electrode). ) Is used, and by embedding a finer trench formed by providing an insulating film on the side wall of the trench formed at the lower limit of the resolution of the photoresist, the The gate length (channel length) is about 30 nm, and the aspect ratio of the trench to be embedded (aspect ratio of 4 or less is required to fill a fine trench) is taken into consideration to form a film thickness of about 50 nm. Has been done. As is clear from FIG. 2, the gate electrode wiring portion connected to the AlCu wiring 15 has a problem of etching in the opening of the via for forming the conductive plug (the thin film gate electrode is also considerably etched and becomes a side contact state). Therefore, considering the contact resistance rises) and the aspect ratio of the trench to be embedded, the film is formed with a thickness of about 300 nm and is rather wide. Therefore, it is possible to form an N-channel MIS field-effect transistor of LDD structure having an ultrafine gate length (channel length) equal to or less than the resolution limit of photoresist. Further, it is self-aligned with the trench element isolation region and the first dummy gate electrode formed at the lower limit of resolution of the photoresist (the first dummy gate electrode (polycrystalline silicon) is formed in alignment with the element isolation region). hand,
Each element (first insulating film, second insulating film, gate electrode, low-concentration and high-concentration impurity source / drain regions, gate oxide film, and barrier metal) can be formed. In addition, since the source / drain regions, which require high-temperature treatment for activation of the impurity regions, can be formed in a self-aligned manner before the gate electrodes are formed, a gate electrode made of a low melting point metal (Al) can be formed. It is also possible to reduce the resistance and to form a gate electrode without a depletion layer (effective thinning of the gate oxide film). Also, Ta ₂ O having a high dielectric constant
_{Since 5} can be used as a gate oxide film, it is possible to increase the thickness of the gate oxide film, improve minute current leakage between the gate electrode and the semiconductor substrate, and reduce the gate capacitance.
At the same time, the gate oxide film can be thinned in terms of SiO ₂ film. Further, since the upper surfaces of the gate electrode, the first insulating film, and the second insulating film can be formed as continuous flat surfaces without steps, an extremely highly reliable interlayer insulating film and wiring body can be formed. As a result, the MIS of the LDD structure having an ultrafine low melting point metal gate electrode below the resolution limit of a photoresist having high speed, high reliability, high performance and high integration.
A field effect transistor can be obtained.

3 and 4 show a second embodiment of the MIS field effect transistor of the present invention. FIG. 3 is a schematic side sectional view in the channel length direction, and FIG. 4 is a schematic side sectional view in the channel width direction. 2 shows a part of a semiconductor integrated circuit including an ultra-fine N-channel MIS field effect transistor formed using a silicon substrate of the same type, 1 to 16 are the same as those in FIG. 1, and 17 is a selective chemical vapor phase. The grown conductive film (tungsten film, upper gate electrode), 18 is a barrier metal (TiN 3). In the figure, an upper gate electrode 17 made of a selective chemical vapor deposition tungsten film is formed directly on the gate electrode (Al) 8.
(For preventing increase in contact resistance as in the first embodiment), a barrier metal 18 is provided on the side wall of the upper gate electrode, and a conductive plug having the barrier metal (TiN) 12 directly on a part of the upper gate electrode 17 in the element region. (W) 13 is provided, and barrier metal (TiN, 14, 16) is formed on the top and bottom of this conductive plug 13.
An MIS field-effect transistor of the N-channel LDD structure having the same structure as that of the first embodiment is formed except that the AlCu wiring 15 having is connected. Also in this embodiment, the same effect as that of the first embodiment can be obtained, and since the gate electrode that hardly extends in the element isolation region can be formed, higher integration can be achieved.

FIG. 5 is a schematic side sectional view (in the channel width direction) of a third embodiment of the MIS field effect transistor of the present invention, which is an ultrafine N-channel MIS electric field formed by using a p-type silicon substrate. 1 shows a part of a semiconductor integrated circuit including an effect transistor, and 1 to 3 and 6 to 18 are shown in FIG.
3 shows the same thing as FIG. 3 and 19 shows a thin oxide film (SiO ₂ , a mask layer for forming a selective chemical vapor deposition conductive film). In the figure, an upper gate electrode 17 (for preventing contact resistance increase) made of a selective chemical vapor deposition tungsten film is provided directly above a part of the gate electrode (Al) 8 in the element isolation region, and a barrier metal is provided on the side wall of the upper gate electrode. 18 is provided, a conductive plug (W) 13 having a barrier metal (TiN) 12 is provided immediately above the upper gate electrode 17, and AlCu having barrier metal (TiN, 14, 16) above and below the conductive plug 13. Wiring 15
A MIS field-effect transistor of the N-channel LDD structure having the same structure as that of the first embodiment except that is connected is formed. Also in this embodiment, the same effect as that of the first embodiment can be obtained.

FIG. 6 is a schematic side sectional view (in the channel width direction) of the fourth embodiment of the MIS field effect transistor of the present invention. It is an ultrafine N-channel MIS electric field formed by using a p-type silicon substrate. 1 shows a part of a semiconductor integrated circuit including an effect transistor, and 1 to 3, 6 to 16 and 19 are the same as those in FIGS. In the figure,
Directly above a part of the gate electrode (Al) 8 in the element isolation region, a stacked conductive plug 13 (selective chemical vapor deposition tungsten film is buried flatly via a barrier metal with a via hole opened in the interlayer insulating film 11). Instead of the conductive plug, a part of the thin oxide film 19 formed on the gate electrode (Al) 8 is opened,
After forming a barrier metal on the side wall with a conductive plug formed by stacking direct selective chemical vapor deposition tungsten films,
A laminated conductive plug (embedded with an interlayer insulating film 11) is provided (for preventing an increase in contact resistance), a barrier metal 12 is provided on a side wall of the conductive plug 13, and a barrier metal (above and below) is provided on the conductive plug 13. An MIS field-effect transistor of the N-channel LDD structure having the same structure as that of the first embodiment is formed except that the AlCu wiring 15 having TiN, 14, 16) is connected. Also in this embodiment, the first
It is possible to obtain the same effect as that of the embodiment.

FIG. 7 is a schematic side sectional view (in the channel length direction) of a fifth embodiment of the MIS field effect transistor of the present invention, which is an ultrafine N channel MIS electric field formed using a p-type silicon substrate. 1 shows a part of a semiconductor integrated circuit including an effect transistor, and 1 to 9 and 11 to 16 are shown in FIG.
20 is a barrier metal (TiN) and 21 is a metal source / drain region (W). However, in the embodiments after this embodiment, the side sectional view in the channel width direction is omitted, but as a measure for preventing the increase of the contact resistance, any one of the measures of FIG. 2, FIG. 5 or FIG. 6 is taken. ing. Note that the metal source / drain region in the present invention is a metal film or alloy that does not include an impurity region, unlike a conventional metal source / drain region formed of a compound (salicide) of an impurity region formed on a silicon semiconductor substrate and a metal film. It is the area of the membrane only. In the figure, a trench element isolation region 3 in which an oxide film is buried is formed up to the same height as the gate electrode (Al) 8, and a barrier metal (Ti) is formed on the side surface and the bottom surface on the n ⁺ type source / drain region 5.
Metal source / drain region (conductive film) 21 having N 2) 20
A MIS field-effect transistor having an N-channel LDD structure, which has substantially the same structure as that of the first embodiment except that is formed, is formed. Also in this embodiment, the same effect as that of the first embodiment can be obtained, and the speedup can be expected due to the reduction of the contact resistance of the source / drain region.

[0011] Figure 8 is a schematic side sectional view of a sixth embodiment of the MIS field effect transistor of the present invention in (a channel length direction), the bonded SOI (S ilicon O n I
SO formed using an n-sulator wafer
1 shows a part of a semiconductor integrated circuit including an I-type ultra-fine N-channel MIS field effect transistor.
16 is the same as that of FIG. 1, 22 is an oxide film (SiO ₂ ) for SOI,
Reference numeral 23 indicates a p-type SOI substrate. In the figure,
The MIS electric field of the N-channel LDD structure having the same structure as that of the first embodiment except that the p-type SOI substrate 23 provided on the oxide film (SiO ₂ ) 22 formed on the p-type silicon substrate is used. An effect transistor is formed. In the present embodiment, in addition to the effect of the first embodiment, the junction capacitance of the source / drain region can be reduced, and further speedup can be achieved. Further, since the gate structure is formed on the thin SOI substrate, the SOI substrate can be completely depleted, so that the depletion layer capacitance between the inversion layer below the gate oxide film and the substrate can be eliminated. Since the voltage applied to the gate electrode can be applied only between the gate electrode and the inversion layer, the subthreshold characteristic can be improved, the threshold voltage can be reduced, and the power consumption can be reduced.

FIG. 9 is a schematic side sectional view (in the channel length direction) of the seventh embodiment of the MIS field effect transistor of the present invention, which shows an SOI type ultra-fine N channel formed by using a bonded SOI wafer. 1 shows a part of a semiconductor integrated circuit including a MIS field effect transistor,
3-9, 11-16, and 20-23 show the same thing as FIG. 1, FIG. 7 and FIG. In the figure, a p-type SOI substrate 23 provided on an oxide film (SiO ₂ ) 22 formed on a p-type silicon substrate is used, and the p-type SOI substrate 23 has a channel region,
Only the n-type source / drain region 4 and the minute n ⁺ -type source / drain region 5 are formed, and most of the source / drain region is formed by the metal source / drain region (W) 21 having the barrier metal (TiN) 20 on the side surface and the bottom surface. However, the MIS field effect of the N-channel LDD structure having substantially the same structure as that of the first embodiment except that the trench element isolation region 3 in which the oxide film is buried is formed to the same height as the gate electrode (Al) 8. A transistor is formed. In the present embodiment, in addition to the effects of the first and sixth embodiments, the source / drain regions can be formed to have a low resistance, so that the speed can be further increased.

FIG. 10 is a schematic side sectional view of an eighth embodiment of the MIS field effect transistor of the present invention, showing an SOI type ultra-fine N-channel MIS field effect transistor formed by using a bonded SOI wafer. It shows a part of a semiconductor integrated circuit including, 1, 3-9, 11-16,
20, 22 and 23 are the same as those in FIGS. 1, 7 and 8, and 24 is a low melting point metal source / drain region (Al). In the figure, an MIS field-effect transistor of the N-channel LDD structure having the same structure as that of the seventh practical example is formed except that Al having a low melting point is formed in the metal source / drain region. In the present embodiment, in addition to the effects of the first and seventh embodiments, the metal source / drain region can be formed to have a further lower resistance, so that the speed can be further increased.

FIG. 11 is a schematic side sectional view of a ninth embodiment of the MIS field-effect transistor of the present invention, which is an ultrafine N-channel M formed by using a p-type silicon substrate.
1 shows a part of a semiconductor integrated circuit including an IS field effect transistor, and 1 to 9, 11 to 16, 20, and 21 are shown in FIGS.
Shows the same thing as. In the figure, a trench element isolation region 3 in which an oxide film is buried is formed up to the same height as the gate electrode (Al) 8, and a barrier metal (TiN) is formed on a side surface and a bottom surface at a part of the trench element isolation region 3. N having substantially the same structure as that of the first embodiment except that a metal source / drain region (W) 21 having 20 is formed and a minute n ⁺ type source / drain region 5 is formed on the side wall of the metal source / drain region 21. A MIS field-effect transistor having an LDD structure of the channel is formed. Also in this embodiment, the first
It is possible to obtain the same effect as that of the above embodiment, and it is possible to speed up by reducing the resistance and the junction capacitance of the source / drain region even though the SOI substrate is not used.

FIG. 12 is a schematic side sectional view of a tenth embodiment of the MIS field-effect transistor of the present invention, which is a semiconductor including an ultrafine N-channel MIS field-effect transistor formed using a p-type silicon substrate. 1 shows a part of an integrated circuit, and 1 to 9 and 11 to 16 are the same as those in FIG. In the figure, an N-channel MIS field effect transistor having the same structure as that of the first embodiment is formed except that the first insulating film and the second insulating film are integrated. . Also in this embodiment, the same effect as that of the first embodiment can be obtained.

Next, an embodiment of the first manufacturing method of the MIS field effect transistor according to the present invention will be described with reference to FIGS. 13 to 22 and FIG. 1, and an embodiment of the second manufacturing method will be described with reference to FIG. -FIG. 29, FIG. 20-FIG. 22, and FIG.
Will be described with reference to. However, here, the MIS of the present invention
Only the manufacturing method for forming the field effect transistor will be described, and the description of the manufacturing method for forming various elements (other transistors, resistors, capacitors, etc.) mounted on a general semiconductor integrated circuit will be omitted. First, an example of the first manufacturing method will be described with reference to FIGS. 13 to 22 and FIG. 1. FIG. 13 A p-type silicon substrate 1 is formed by using an ordinary photolithography technique and using a resist (not shown) as a mask layer.
Is selectively subjected to anisotropic dry etching to form a trench for forming an element isolation region. Then, the resist (not shown) is removed. Then growing a chemical vapor deposition oxide film (SiO _2), a chemical mechanical polishing (C hemical M echa
nical P olishing after abbreviated as CMP) flatly buried, to form the trench isolation regions 3. Next, a gate oxide film 6 (SiO ₂ / Ta ₂ O ₅ ) having a thickness of about 12 nm is grown. Then, a barrier metal / etching stopper film (TiN) 7 of about 20 nm is grown. Then, a polycrystalline silicon film (PolySi) 25 having a thickness of about 80 nm is grown. Next, using a normal photolithography technique, boron ions are implanted into the p-type silicon substrate 1 using the trench element isolation region 3 in which a resist (not shown) and an oxide film (SiO ₂ ) are embedded as a mask layer. . Then, the resist (not shown) is removed. Next, the p-type impurity well region 2 is formed by running at high temperature, and the threshold voltage is controlled. Next, using a normal photolithography technique, using a resist (not shown) as a mask layer, the polycrystalline silicon film (PolySi) 25 and the barrier metal (TiN) 7 are sequentially anisotropically dry-etched, and if the present A first dummy gate electrode (PolySi) 25 having a gate length of about 100 nm, which is the resolution limit of the resist, is formed. Then resist (not shown)
To remove. Then the first dummy gate electrode (PolySi)
Arsenic is ion-implanted using the trench element isolation region 3 in which 25 and the oxide film (SiO ₂ ) are buried as a mask layer to define the n ⁺ type source / drain region 5. Next, the gate oxide film 6 except under the first dummy gate electrode (PolySi) 25
(SiO ₂ / Ta ₂ O ₅ ) is removed by etching. Next, a chemical vapor deposition oxide film (SiO ₂ ) is grown. Then, chemical mechanical polishing (CMP) is performed to bury the second insulating film (SiO ₂ ) 10 in a flat manner. Next, the first dummy gate electrode (PolySi) 25 is removed by etching to form a first trench. Then, a nitride film (Si ₃ N ₄ ) having a thickness of about 35 nm is grown by chemical vapor deposition. Next, the nitride film (Si ₃ N ₄ ) is anisotropically dry-etched, leaving the nitride film (Si ₃ N ₄ ) 26 only on the side wall of the first trench,
A finer second trench having a width of about 30 nm is formed in the central portion. Next, a polycrystalline silicon film (PolySi) is grown to such an extent that the fine second trench is sufficiently filled. Then, chemical mechanical polishing (CMP) is performed to bury the polycrystalline silicon film (PolySi) in the second trench evenly. At this point, the embedded polycrystalline silicon film is in an inversely tapered state, so that both side surfaces of the polycrystalline silicon film (PolySi) are further vertical to the p-type silicon substrate 1 (of course, the first trench Both sides of the nitride film (Si ₃ N ₄ ) 26 left on the side walls are also perpendicular to the p-type silicon substrate 1 and the top surface is flat) About 30
Chemical mechanical polishing (CMP) of about nm is performed. Thus, the second dummy gate electrode (PolySi) 27 having a gate length of about 30 nm and a thickness of about 50 nm is formed. Fig. 19 Next, nitride film (Si ₃ N ₄ ) 26 and barrier metal (TiN) 7
Is sequentially anisotropically dry-etched to form a third trench. Then, phosphorus is ion-implanted into the third trench using the oxide film 10 and the second dummy gate electrode (PolySi) 27 as a mask layer to define the n-type source / drain region 4.
Next, heat treatment is performed to activate the n-type and n ⁺ -type source / drain regions (4, 5) and control the diffusion layer. Then, the extra gate oxide film 6 (SiO ₂ / Ta ₂ O ₅ ) is removed by etching. Next, a chemical vapor deposition oxide film (SiO ₂ ) is grown. Then, chemical mechanical polishing (CMP) is performed to bury the third trench in a flat manner to form a first insulating film (SiO ₂ ) 9. Next, the second dummy gate electrode (PolySi) 27 is removed by etching to form a fourth trench. Next, although not shown in the figure, a barrier metal (TiN) 7 is formed by using a normal photolithography technique and using a resist (a hole for connecting the gate electrode and the wiring body on the element isolation region as an opening) as a mask layer. , The gate oxide film 6 (SiO ₂ / Ta ₂ O ₅ ) and part of the oxide film 3 are sequentially anisotropically dry-etched.
(Here, the etching of the oxide film 3 and the width of the opening are selected so that the aspect ratio of the opening is 4 or less.) Next, the resist is removed. Next, an Al film is grown by sputtering so as to sufficiently fill the fourth trench. Next, chemical mechanical polishing (CMP) is performed to form a gate electrode (Al) 8 in which the fourth trench is buried evenly. Next, a phosphosilicate glass (PSG) film 11 having a thickness of about 500 nm is grown by chemical vapor deposition. Then, using a normal photolithography technique, the resist (not shown) is used as a mask layer to selectively anisotropically dry-etch the PSG film 11 to open a via hole. Then, the resist (not shown) is removed. Then, by sputtering, Ti becomes the barrier metal
Grow N 12. Then, the tungsten film 13 is grown by chemical vapor deposition. Then chemical mechanical polishing (CMP)
Thus, the conductive plug (W) 13 is formed by embedding it in the via. Fig. 1 Next, sputtered TiN 14 as barrier metal to 50
Grow about nm. Next, sputtered Al
15 (containing several% of Cu) is grown to about 500 nm. Next, TiN 16 to be a barrier metal is grown to a thickness of about 50 nm by sputtering. Then, using a normal photolithography technique, the barrier metal (TiN), Al (containing several% of Cu) and the barrier metal (TiN) are anisotropically dry-etched using a resist (not shown) as a mask layer. The AlCu wiring 15 is formed. Then, the resist (not shown) is removed, and the double dummy gate electrode and the double damascene method (also used for filling the insulating film and planarizing as a damascene process) according to the first manufacturing method of the present invention are used. Ultra fine low melting point metal gate type MI below the resolution limit of resist
The S field effect transistor is completed.

Next, regarding the embodiment of the second manufacturing method,
This will be described with reference to FIGS. 23 to 30, FIG. 21, FIG. 22 and FIG. FIG. 23: A p-type silicon substrate 1 is formed by using a normal photolithography technique and using a resist (not shown) as a mask layer.
Is selectively subjected to anisotropic dry etching to form a trench for forming an element isolation region. Then, the resist (not shown) is removed. Next, a chemical vapor deposition oxide film (SiO ₂ ) is grown, and chemical mechanical polishing (CMP) is performed to bury it flatly to form a trench element isolation region 3. Then, a gate oxide film 6 (SiO ₂ / Ta ₂ O ₅ ) having a thickness of about 12 nm is grown. Then, a barrier metal / etching stopper film (TiN) 7 of about 20 nm is grown. Next, a nitride film (Si ₃ N
₄ ) grow 28. Then, using a normal photolithography technique, a resist (not shown) and an oxide film (Si
O ₂₎ is used as a mask layer a trench isolation region 3 embedded, ion implantation of boron into the silicon substrate 1 of p-type. Then, the resist (not shown) is removed. Next, the p-type impurity well region 2 is formed by running at high temperature, and the threshold voltage is controlled. Next, using a normal photolithography technique, using a resist (not shown) as a mask layer, a nitride film (Si ₃ N ₄ ) is formed.
28 is anisotropically dry-etched to open a first trench having a width of about 100 nm, which is the resolution limit of the resist at the present time. (Although the pattern has the opposite concavities and convexities, it corresponds to the first dummy gate electrode.) Next, the resist (not shown) is removed. Next, an oxide film (SiO ₂ ) having a thickness of about 35 nm is grown by chemical vapor deposition. Next, this oxide film (SiO ₂ ) is anisotropically dry-etched to leave the oxide film (SiO ₂ ) 29 only on the sidewalls of the trench, and a _second finer trench having a width of about 30 nm is formed in the central portion. Next, a polycrystalline silicon film (PolySi) is grown to such an extent that the fine second trench is sufficiently filled. Then, chemical mechanical polishing (CMP) is performed to bury the polycrystalline silicon film (PolySi) in the second trench evenly. At this point, the embedded polycrystalline silicon film is in an inversely tapered state, so that both side surfaces of the polycrystalline silicon film (PolySi) are further vertical to the p-type silicon substrate 1 (of course, the first trench Both side surfaces of the oxide film (SiO ₂ ) 29 left on the side wall are also perpendicular to the p-type silicon substrate 1 and the top surface is flat) about 30 nm
Chemical mechanical polishing (CMP) is performed. Thus the gate length
The second dummy gate electrode (Po
lySi) 27 is formed. Next, the oxide film (SiO ₂ ) 29 and the barrier metal (TiN) 7 are anisotropically dry-etched sequentially to form a third trench. Then, using the nitride film (Si ₃ N ₄ ) 28 and the second dummy gate electrode (PolySi) 27 as a mask layer, phosphorus is ion-implanted into the third trench to define the n-type source / drain region 4. Next, the extra gate oxide film 6 (SiO ₂ / Ta ₂ O ₅ ) is anisotropically dry-etched. Next, a chemical vapor deposition oxide film (SiO ₂ ) is grown. Then, chemical mechanical polishing (CMP) is performed to bury the third trench in a flat manner to form a first insulating film (SiO ₂ ) 9. Next, the remaining nitride film (Si ₃ N ₄ ) 28 and barrier metal (TiN) 7 are successively anisotropically dry-etched. Then, a trench element in which a second dummy gate electrode (PolySi) 27 having a first insulating film (SiO ₂ ) 9 on its side wall (this corresponds to the first dummy gate electrode pattern) and an oxide film (SiO ₂ ) are buried. Using the isolation region 3 as a mask layer, arsenic is ion-implanted to define the n ⁺ type source / drain region 5. Next, heat treatment is performed to activate the n-type and n ⁺ -type source / drain regions (4, 5) and control the diffusion layer. Then, the extra gate oxide film 6 (SiO ₂ / Ta ₂ O ₅ ) is removed by etching. Next, a chemical vapor deposition oxide film (SiO ₂ ) is grown. Then, chemical mechanical polishing (CMP) is performed to bury the second insulating film (SiO ₂ ) 10 in a flat manner. After that, the steps of FIGS. 21, 22 and 1 used in the embodiment of the first manufacturing method are performed to solve the resist using the double dummy gate electrode and the double damascene method according to the second manufacturing method of the present invention. An ultra-fine, low-melting-point metal gate type MIS field-effect transistor below the image limit is completed.

Although the N-channel MIS field-effect transistor has been described in the above description of the embodiments, it may be applied to a P-channel MIS field-effect transistor (however, the hot carrier effect need not be considered. Therefore, it is not necessary to provide a low concentration source / drain region), and it is also possible to apply to C-MOS and bi-C-MOS. Although TiN is used as the barrier metal, it is not limited to this and the conductive plug is not limited to W. Further, the gate electrode is not limited to Al, the metal source / drain region is not limited to W, and any metal or metal compound having a low resistance may be used. In addition, the resolution limit of the resist at the present time is temporarily set to about 100 nm, but this is based on the value estimated to be mass-producible in the current technology as a guide, and the absolute resolution limit in future technology is Does not mean that. The present invention is effective even when the resolution limit is dramatically improved. In the above manufacturing method,
Although a polycrystalline silicon film (PolySi) is used as the first and second dummy gate electrodes, the invention is not limited to this and a refractory metal or a refractory metal compound may be used.
Further, regarding a method of forming an insulating film on the side wall of the first trench and forming a second trench, anisotropic insulating etching is performed on the insulating film formed on the entire surface including the first trench,
A method of forming a finer second trench inside the first trench by leaving it on the sidewall of the first trench is used. However, an insulating film is formed on the entire surface including the side surface and the bottom surface of the first trench. To form a finer second trench inside the first trench.
After growing poly-crystalline silicon film (PolySi) to the extent that the trenches of the above can be sufficiently filled, chemical mechanical polishing (CMP)
Then, a flat side wall insulating film and a second dummy gate electrode are formed, and an extra insulating film (a part of the side wall insulating film) left under the second dummy gate electrode at the time of forming the fourth trench is removed. The method may be performed.

[0019]

As described above, according to the present invention, the trench from which the first dummy gate electrode formed at the lower limit of resolution of the photoresist is removed is self-aligned with the side wall to form the insulating film. By further miniaturizing the gate electrode and embedding the gate electrode in the fine trench, a gate electrode having a photoresist resolution limit or less can be easily formed in a self-aligned manner. Therefore, it is possible to form an N-channel MIS field-effect transistor of LDD structure having an ultrafine gate electrode having a resolution limit of the photoresist or less, which is not determined by the mask pattern of the photoresist. The first dummy gate electrode (first dummy gate electrode (polycrystalline silicon)) formed at the lower limit of resolution of the trench element isolation region and the photoresist.
Are self-aligned with the element isolation region) and each element (first insulating film, second insulating film, gate electrode, low concentration and high concentration impurity source / drain regions, gate oxide film and barrier) It is possible to form a metal). In addition, since the source / drain regions, which require high-temperature treatment for activation of the impurity regions, can be formed in a self-aligned manner before the gate electrodes are formed, a gate electrode made of a low melting point metal (Al) can be formed. It is also possible to reduce the resistance and to form a gate electrode without a depletion layer (effective thinning of the gate oxide film). Further, a metal source / drain region can be formed by a metal layer, and the resistance of the source / drain region and the junction capacitance can be reduced. In addition, since Ta ₂ O ₅ having a high dielectric constant can be used as the gate oxide film, the gate oxide film can be made thicker to improve the minute current leakage between the gate electrode and the semiconductor substrate (or the SOI substrate) and to improve the gate. The capacity can be reduced, and at the same time, the gate oxide film can be thinned in terms of SiO ₂ film. When a fully depleted SOI substrate is used, the depletion layer capacitance can be eliminated and the threshold voltage can be reduced by improving the subthreshold characteristics. Further, since the upper surfaces of the gate electrode, the first insulating film, and the second insulating film can be formed as continuous flat surfaces without steps, an extremely highly reliable interlayer insulating film and wiring body can be formed. That is, the MIS electric field effect of the LDD structure having an ultrafine low melting point metal gate electrode below the resolution limit of the photoresist, which enables formation of a semiconductor integrated circuit of extremely high speed, high reliability, high performance, low power and high integration. A transistor can be obtained.

[Brief description of drawings]

FIG. 1 is a schematic side sectional view of a first embodiment of a MIS field effect transistor of the present invention (channel length direction).

FIG. 2 is a schematic side sectional view of the first embodiment of the MIS field effect transistor of the present invention (channel width direction).

FIG. 3 is a schematic side sectional view of a second embodiment of the MIS field effect transistor of the present invention (channel length direction).

FIG. 4 is a schematic side sectional view of a second embodiment of the MIS field effect transistor of the present invention (channel width direction).

FIG. 5 is a schematic side sectional view of a third embodiment of the MIS field effect transistor of the present invention (channel width direction).

FIG. 6 is a schematic side sectional view of a fourth embodiment of the MIS field effect transistor of the present invention (channel width direction).

FIG. 7 is a schematic side sectional view of a fifth embodiment of the MIS field effect transistor of the present invention (channel length direction).

FIG. 8 is a schematic side sectional view of a sixth embodiment of the MIS field effect transistor of the present invention (channel length direction).

FIG. 9 is a schematic side sectional view of a seventh embodiment of the MIS field effect transistor of the present invention (channel length direction).

FIG. 10 is a schematic side sectional view of an eighth embodiment of the MIS field effect transistor of the present invention (channel length direction).

FIG. 11 is a schematic side sectional view of a ninth embodiment of the MIS field effect transistor of the present invention (channel length direction).

FIG. 12 is a schematic side sectional view of a tenth embodiment of the MIS field-effect transistor of the present invention (channel length direction).

FIG. 13 is a process sectional view of the first manufacturing method of the MIS field-effect transistor of the present invention.

FIG. 14 is a process sectional view of the first manufacturing method of the MIS field-effect transistor of the present invention.

FIG. 15 is a process sectional view of a first manufacturing method of the MIS field-effect transistor of the present invention.

FIG. 16 is a process sectional view of the first manufacturing method of the MIS field-effect transistor of the present invention.

FIG. 17 is a process cross-sectional view of the first manufacturing method of the MIS field-effect transistor of the present invention.

FIG. 18 is a process cross-sectional view of the first manufacturing method of the MIS field-effect transistor of the present invention.

FIG. 19 is a process sectional view of the first manufacturing method of the MIS field-effect transistor of the present invention.

FIG. 20 is a process cross-sectional view of the first manufacturing method of the MIS field-effect transistor of the present invention.

FIG. 21 is a process sectional view of the first manufacturing method of the MIS field-effect transistor of the present invention.

FIG. 22 is a process sectional view of the first manufacturing method of the MIS field-effect transistor of the present invention.

FIG. 23 is a process sectional view of a second manufacturing method of the MIS field-effect transistor of the present invention.

FIG. 24 is a process sectional view of a second manufacturing method of the MIS field-effect transistor of the present invention.

FIG. 25 is a process sectional view of a second manufacturing method for the MIS field-effect transistor of the present invention.

FIG. 26 is a process sectional view of the second manufacturing method of the MIS field-effect transistor of the present invention.

FIG. 27 is a process cross-sectional view of the second manufacturing method of the MIS field-effect transistor of the present invention.

FIG. 28 is a process sectional view of the second manufacturing method of the MIS field-effect transistor of the present invention.

FIG. 29 is a process sectional view of a second manufacturing method of the MIS field-effect transistor of the present invention.

FIG. 30 is a process sectional view of a second manufacturing method of the MIS field-effect transistor of the present invention.

FIG. 31 is a schematic side sectional view of a conventional MIS field effect transistor (channel length direction).

FIG. 32 is a schematic side sectional view of a conventional MIS field effect transistor (channel width direction).

[Explanation of symbols]

1 p-type silicon substrate 2 p-type impurity well region 3 element isolation region forming trench and buried oxide film (SiO ₂ ) 4 n-type source / drain region 5 n ⁺ type source / drain region 6 gate oxide film (SiO ₂ / Ta ₂ O ₅ ) 7 Barrier metal and etching stopper film (TiN) 8 Gate electrode (Al) 9 First insulating film (sidewall insulating film, SiO ₂ ) 10 Second insulating film (SiO ₂ ) 11 Phosphorus silicate glass (PSG) Film 12 Barrier metal (TiN) 13 Conductive plug (W) 14 Barrier metal (TiN) 15 AlCu wiring 16 Barrier metal (TiN) 17 Selective chemical vapor deposition conductive film (W, upper gate electrode) 18 Barrier metal (TiN) 19 Thin oxide film (SiO ₂ , mask layer for forming selective chemical vapor deposition conductive film) 20 Barrier metal (TiN) 21 Metal source / drain region (W) 22 SOI oxide film (SiO ₂ ) 23 p-type SOI substrate 24 Low melting point metal sauce Rain region (Al) 25 First dummy gate electrode (PolySi) 26 Sidewall nitride film (Si ₃ N ₄ for forming second dummy gate electrode) 27 Second dummy gate electrode (PolySi) 28 Nitride film (Si ₃ N ₄ ) 29 Sidewall oxide film (SiO ₂ , for forming second dummy gate electrode)

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 29/43 H01L 29/78 617J 29/786 301P F term (reference) 4M104 AA01 AA09 BB02 BB30 CC01 CC05 DD02 DD03 DD04 DD16 DD37 DD43 DD66 DD75 EE03 EE09 EE12 EE16 FF01 FF04 FF18 FF22 FF26 FF27 GG08 GG09 GG10 GG14 HH14 HH20 5F033 GG03 HH04 HH08 HQ QQ QQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQMQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQMQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQUQOQ there's KKQU KK01 KK01 KK01 KK08. QQ48 QQ58 QQ65 QQ73 RR03 RR04 RR06 RR14 SS11 TT02 TT07 TT08 VV06 XX01 XX03 XX10 XX24 5F110 AA01 AA04 CC02 DD05 DD13 EE01 EE03 EE14 QANNQ25QQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQDD BA01 BC06 BD01 BD12 BF10 BF11 BF15 BF59 BF60 BG03 BG04 BG30 BG36 BG38 BG40 BG60 BH15 BJ10 BJ11 BJ17 B J20 BJ27 BK02 BK03 BK13 BK21 CA02 CA03 CB04 CB08 CB10 CC05

Claims (6)

[Claims] 1. A semiconductor substrate, a gate insulating film selectively provided on the semiconductor substrate, a barrier metal layer provided on the gate insulating film, and a gate electrode provided on the barrier metal layer. A first insulating film self-aligned with the gate electrode and provided on the sidewall of the gate electrode on both side surfaces substantially perpendicular to the semiconductor substrate; and a first insulating film self-aligned with the first insulating film. A second insulating film (or a conductive film) provided in contact with the first insulating film, and a low-concentration source / drain provided in the semiconductor substrate below the first insulating film in self-alignment with the gate electrode. Region and a high-concentration source / drain region provided in the semiconductor substrate in self-alignment with the first insulating film and in contact with the low-concentration source / drain region. Transistor. 2. The MIS field effect transistor according to claim 1, wherein the first insulating film and the second insulating film are formed of an integrated insulating film. 3. A gate electrode portion extending to an element isolation region,
The device according to claim 1, wherein the gate electrode portion in the element formation region is formed to be thicker than the gate electrode portion.
The MIS field effect transistor described. 4. A gate electrode is provided which is in contact with the upper surface of the gate electrode and is wider than the gate electrode and self-aligned with the gate electrode, the gate electrode having a thick upper gate electrode. The MIS field effect transistor according to claim 1 or 2, wherein 5. A high-concentration source / drain region is formed in self-alignment with the first dummy gate electrode, and a finer second dummy gate electrode is formed in self-alignment with the first dummy gate electrode. And forming a low-concentration source / drain region in self-alignment with the second dummy gate electrode, and then forming a low-melting point gate electrode in the trench formed by removing the second dummy gate electrode. A method of manufacturing a MIS field effect transistor, comprising: 6. A finer second dummy gate electrode is formed by self-aligning with a trench of the same size as the first dummy gate electrode, and is self-aligning with the second dummy gate electrode so as to have a low concentration. A source / drain region is formed, a first insulating film is formed on a sidewall in self-alignment with the second dummy gate electrode, and a high-concentration source / drain region is formed in self-alignment with the first insulating film. And a low melting point gate electrode is formed in a trench formed by removing the second dummy gate electrode.