JPH1174526A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provided a semiconductor device and its manufacturing method capable of reducing size and preventing a punch through. SOLUTION: A method of manufacturing semiconductor device comprises a process for forming a gate structure 18 including a dummy electrode and a gate electrode having at least an insulation film at its bottom, and forming an element separation insulation film 16 on one of the main face of a wafer 11, so that the dummy gate or a first groove 19 separated by the gate electrode is formed on the surface of the wafer 11, the dummy gate and one of the gate electrode are positioned in the first groove 19, and the upper face of the gate structure 18 being equal to or lower than the height of the upper face of the element separation insulation film 16. The method further comprises a process for forming a source electrode and a drain electrode in the first groove 19.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method for manufacturing the same.

[0002]

2. Description of the Related Art In recent years, it has been required to further increase the degree of integration of LSIs and to improve the operation speed thereof. In order to achieve this, it is common practice to proportionately reduce the dimensions of each member constituting the transistor. However, when the width of the gate electrode is reduced to about 0.1 μm, such a method causes the following problems.

FIG. 38 schematically shows an example of a conventional MOSFET. FIG. 38 is a sectional view. In FIG. 38, on one main surface of the p-type silicon substrate 1, Si
A gate insulating film 2 made of O ₂ or the like and a gate electrode 3 in which an N-type impurity such as phosphorus is introduced into polycrystalline silicon at a high concentration of 2 × 10 ²⁰ cm ⁻³ or more are sequentially laminated. A gate sidewall 4 made of an insulator is formed on a side surface of the gate electrode 3 with a thermal oxide film 10 interposed therebetween. In the surface region of the substrate 1, an n-type impurity diffusion region 5 called an extension formed shallowly below the side wall 4,
N-type impurity diffusion region 6 formed deeper than
An element isolation region 7 made of O ₂ or the like is provided. Furthermore, in order to reduce the resistance value of the source / drain diffusion layer, salicide (Self Ali
The metal silicide layer 8 is formed by the gn silicide method. In the MOSFET shown in FIG. 38, extension 5 and n-type impurity diffusion region 6 constitute a source / drain diffusion layer. In addition, the metal silicide layer 8
It is also provided on the gate electrode 3.

In order to suppress the short channel effect and the increase in electric resistance in the MOSFET shown in FIG. 38, the impurity concentration in the extension 5 is reduced to 10 ¹⁹ cm ^−3.
It must be controlled to a very high level, and the depth must be controlled to be very shallow, 0.05 μm or less. In order to form the extension 5 shallowly, the acceleration voltage at the time of ion implantation must be several K
It needs to be controlled to be as low as eV. However,
When the acceleration voltage is reduced, the ion current decreases, and it becomes very difficult to complete the ion implantation within a realistic processing time.

In order to prevent an increase in leakage current due to a reverse bias of the pn junction, the bottom surface of the metal silicide layer 8 formed in the surface region of the substrate 1 and the bottom surface of the n-type impurity diffusion region 6 are formed. The distance between them should typically be at least 0.07 μm. On the other hand, the thickness of the metal silicide layer 8 is
The parasitic resistance of the source / drain diffusion layer is
Is determined to be sufficiently smaller than the resistance value in the state where the voltage is continuously applied. Therefore, the metal silicide layer 8 needs to be formed to a predetermined value required to obtain a low resistance value, for example, a thickness of 0.05 μm or more. That is, n-type impurity diffusion region 6 is formed such that its bottom surface is located at a depth of 0.12 μm or more from the surface of substrate 1. However, in this case, the gate electrode 3
There is a possibility that so-called punch-through, in which a current flows even in a state in which no voltage is applied, that is, in an off state, may occur.

An elevated source / drain structure shown in FIG. 39 (b) is known as a means for preventing the occurrence of the punch-through.

FIGS. 39A and 39B show a conventional MOSFET having an elevated source / drain structure.
FIG. 4 is a cross-sectional view schematically showing a manufacturing process of the first embodiment. Note that FIG.
In the MOSFET shown in FIGS.
The same reference numerals are given to members common to the MOSFET shown in FIG.

In manufacturing a conventional MOSFET having an elevated source / drain structure, first,
As shown in FIG. 39A, Si is selectively epitaxially grown on the n-type impurity diffusion region 5 to form a Si film 9. That is, the region where the source / drain diffusion layers are formed is enlarged above the substrate 1. Note that the Si film 9 is also formed on the gate electrode 3. Next, as shown in FIG. 39B, an n-type impurity diffusion region 6 is formed by performing ion implantation. Further, a MOSFET is obtained by forming a metal silicide layer (not shown) similar to that described with reference to FIG. In FIGS. 39A and 39B, the gate electrode 3 is formed lower than the side wall 4. This is to prevent the Si film 9 formed on the gate electrode 3 from growing laterally and conducting between the gate electrode 3 and the source / drain regions.

In the MOSFET formed as described above, although the n-type impurity diffusion region 6 is formed with a sufficient thickness, its effective depth, that is, the depth from the surface of the substrate 1 is increased. The MOSFET shown in FIG.
Has been reduced as compared to. That is, according to the MOSFET, the distance between the bottom surface of the metal silicide layer (not shown) and the bottom surface of the n-type impurity diffusion region 6 can be made sufficiently large. However, according to this method, during the epitaxial growth, Si grows not only on the n-type impurity diffusion region 5 shown in FIG. As a result, the Si film 8 is also formed on the element isolation region 7, and it may be difficult to maintain an insulating state between adjacent transistors.

In the above description, the NMOS has been described as an example.
S and PMOS have the same structure except that the conductivity types of the semiconductors are opposite. Therefore, the above-mentioned problem is the same for the PMOS.

[0011]

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device capable of reducing the size and preventing the occurrence of punch-through, and a method of manufacturing the same.

It is another object of the present invention to provide a semiconductor device capable of maintaining an insulating state between elements even when the size is reduced, and a method of manufacturing the same.

It is still another object of the present invention to provide a semiconductor device capable of reducing the size, preventing the occurrence of punch-through, and maintaining an insulating state between elements, and a method of manufacturing the same. It is in.

[0014]

SUMMARY OF THE INVENTION The present invention relates to a) a gate structure including one of a dummy gate electrode and a gate electrode having an insulating film on at least a bottom surface on one main surface of a substrate; The film and a dummy gate electrode or a first groove parted by the gate electrode on the surface of the substrate, so that one of the dummy gate electrode and the gate electrode is located in the first groove part, and Forming the upper surface of the structure to have a height equal to or lower than the height of the upper surface of the element isolation insulating film; and b) a first step.
And forming a source electrode and a drain electrode in the trench.

Preferred embodiments of the method for manufacturing a semiconductor device will be described below.

(1) The gate structure includes a first gate structure including a dummy gate line and the dummy gate electrode, and a second gate including a gate line having an insulating film on at least a bottom surface and the gate electrode. The dummy gate line and the gate line are formed on the element isolation insulating film, are respectively connected to the dummy gate electrode and the gate electrode, and intersect with the first groove. In this case, it is preferable to satisfy the following conditions.

[1] The gate structure comprises the first gate structure, and after the step of forming the source and drain electrodes, a step of removing the first gate structure to form a second trench. And an insulating film in the second groove,
The gate electrode and the gate wiring are separated such that the gate electrode divides the gate wiring and is located between the source and drain electrodes, and between the gate electrode and the gate wiring and the inner wall of the second groove. And forming the insulating film so as to interpose the insulating film. In this case, it is more preferable to satisfy the following conditions.

The gate electrode and the gate wiring are formed by coating a second thin film made of a material constituting the gate wiring or a material used for forming the gate wiring on the entire surface of one main surface of the substrate. Forming, and the second
The portion of the thin film located outside the second groove is formed by CMP.
That they are integrally and simultaneously formed by removal using a method.

Before the step of forming the insulating film and the gate wiring, a step of doping a conductive impurity in a surface region of the substrate corresponding to the second groove; A step of forming a semiconductor film on the bottom surface using an epitaxial growth method;

[2] The step of forming the gate structure and the element isolation insulating film includes forming the element isolation insulating film on one main surface of the substrate, and forming a third layer on the element isolation insulating film.
Forming a third thin film made of a material constituting the gate structure on the entire surface of one main surface of the substrate; and forming a third thin film on the outside of the third groove portion of the third thin film. The portion located is removed by a CMP method, and the third portion is removed.
Forming the gate structure in the groove, and forming a first groove having at least a part of a side surface made of the element isolation insulating film so as to intersect with the gate structure.

[3] The gate structure comprises a second gate structure, and the gate electrode and the gate wiring are made of metal.

(2) Before the step of forming the source and drain electrodes, a step of forming a source diffusion layer and a drain diffusion layer in a surface region of the substrate corresponding to the first groove is provided. To do.

(3) Before the step of forming the source and drain electrodes, a step of forming a semiconductor film on the bottom surface of the first trench by using an epitaxial growth method, and a step of forming a source diffusion layer in the semiconductor film. And forming a drain diffusion layer.

(4) In the step of forming the source and drain electrodes, the material for forming the source and drain electrodes or the source and drain electrodes is formed on the whole of one main surface of the substrate. Forming a first thin film made of a material to be obtained, and removing a portion of the first thin film located outside the first groove by using a CMP method.

(5) The source and drain electrodes are made of metal.

(6) The gate structure comprises one of the dummy gate electrode and the gate electrode having an insulating film on at least a bottom surface. In this case, it is preferable to satisfy the following conditions.

[1] In the step of forming the gate structure and the element isolation insulating film, the step of forming the gate structure and the element isolation insulating film is performed on a part of the element isolation insulating film and the gate structure, and the height of the upper surface is the upper surface of the element isolation insulating film Forming a dummy wiring that is higher than the height of the dummy wiring. In this case, it is preferable to further satisfy the following condition.

A step of forming a fourth thin film on the entire surface of one of the main surfaces of the substrate before the step of forming the source and drain electrodes, and polishing the fourth thin film to form an upper surface of the dummy wiring And forming a fourth groove in the thin film by removing the dummy wiring. In this case, it is more preferable to satisfy the following conditions.

Between the step of forming the fourth groove and the step of forming the source and drain electrodes, removing at least a part of the element isolation insulating film exposed in the fourth groove; Forming an eighth groove at the bottom of the fourth groove.

The gate structure comprises a dummy gate electrode, and the dummy gate electrode is removed between the step of forming the fourth groove and the step of forming the source and drain electrodes. A step of forming a seventh groove at the bottom of the fourth groove, and a step of forming a gate electrode in the fourth groove. In this case, after the step of forming the element isolation insulating film and the gate structure, a step of removing a part of the element isolation insulating film to form a fifth groove, and a step of forming a source in the fifth groove. It is preferable that the method further includes a step of forming a connection wiring connected to at least one of the electrode, the drain electrode, and the gate electrode, and the step of forming the gate wiring and the step of forming the connection wiring are performed at the same time.

The fourth thin film is made of a material forming the source and drain electrodes or a material used to form the source and drain electrodes.

A step of removing the fourth thin film before the step of forming the source and drain electrodes.

A step of forming a fifth groove by removing a part of the element isolation insulating film after the step of forming the element isolation insulating film and the gate structure; Forming a connection wiring connected to at least one of the source electrode, the drain electrode, and the gate electrode; In this case, a step of forming the connection wiring;
More preferably, the step of forming the source electrode and the drain electrode is performed simultaneously.

(7) In the step of forming the gate structure and the element isolation insulating film, a third thin film made of a material constituting the dummy gate wiring is formed on the entire one main surface of the substrate. The third thin film has a forward tapered sixth shape.
Forming the trench, forming the element isolation insulating film on one main surface of the substrate, and removing a portion of the element isolation insulating film located outside the sixth groove by using a CMP method. And anisotropically etching the third thin film to simultaneously perform the formation of the gate structure and the first groove and the formation of a sidewall on a side surface of the element isolation insulating film. .

The present invention also provides a step of forming a dummy gate wiring on one main surface of a substrate, a step of forming a semiconductor film on an exposed surface of one main surface of the substrate by using an epitaxial growth method, And a method of manufacturing a semiconductor device including a step of forming a gate sidewall made of an insulator and covering a side surface of a dummy gate wiring on a semiconductor film.

In the method of manufacturing a semiconductor device, after the step of forming the gate side wall, a step of forming an interlayer insulating film on the entire surface of one main surface of the substrate, such that an upper surface of the dummy gate wiring is exposed. Planarizing the interlayer insulating film, removing the dummy gate wiring to form a groove, forming a gate insulating film on the bottom surface and side walls of the groove, and forming a gate wiring in the groove. Is preferably provided. In this case, it is more preferable to satisfy the following conditions.

(1) Before the step of forming the gate side wall, a step of doping the semiconductor film with a conductive impurity is provided. In this case, between the step of forming the gate side wall and the step of forming the interlayer insulating film, a step of doping a conductive region into the surface region of one main surface of the substrate and the semiconductor film is provided. Is preferred.

(2) The step of forming the semiconductor film includes epitaxially growing a semiconductor containing a conductive impurity. In this case, between the step of forming the gate side wall and the step of forming the interlayer insulating film, a step of doping a conductive region into the surface region of one main surface of the substrate and the semiconductor film is provided. Is preferred.

(3) The step of forming the gate wiring comprises:
Depositing a conductor or semiconductor material on one main surface of the substrate so as to fill the groove, and removing a portion of the conductor or semiconductor material outside the groove.

The present invention further provides a substrate, an element isolation insulating film formed on one main surface of the substrate, a gate electrode formed on one main surface of the substrate, and an element isolation insulating film formed on the element isolation insulating film, A gate wiring connected to the gate electrode, a source electrode and a drain electrode provided on one main surface of the substrate to face each other with the gate electrode interposed therebetween, and insulation formed on the bottom and side surfaces of the gate electrode and the wiring Having a film, a gate electrode,
The gate wiring, the source electrode, and the drain electrode provide a semiconductor device in which the height of the upper surface is equal to or lower than the height of the upper surface of the element isolation insulating film.

Preferred embodiments of the above semiconductor device are described below.

(1) A source diffusion layer and a drain diffusion layer are provided below the source electrode and the drain electrode on the substrate, respectively. In this case, it is more preferable that the bottom surfaces of the gate electrode and the gate wiring are lower than the top surfaces of the source diffusion layer and the drain diffusion layer.

(2) The upper surfaces of the gate electrode, gate wiring, source electrode and drain electrode have the same height.

(3) The upper surfaces of the gate electrode and the gate wiring are lower than the upper surfaces of the source electrode and the drain electrode.

(4) The upper surfaces of the gate electrode and the gate wiring are higher than the upper surfaces of the source electrode and the drain electrode.

(5) On one main surface of the substrate, a connection wiring connected to at least one of the source electrode, the drain electrode, the gate electrode, and the gate wiring is provided. The height is equal to or lower than the height of the upper surface of the element isolation insulating film.

Further, according to the present invention, a substrate, a gate wiring formed on one main surface of the substrate, a gap between the substrate and the gate wiring,
An insulating film formed on the side surface of the gate wiring, a semiconductor formed on one main surface of the substrate by epitaxial growth, and a pair of thin films disposed on both sides of the gate wiring; A semiconductor device that covers a side surface of a gate wiring and has a gate side wall made of an insulator.

In the above semiconductor device, a region between the gate side wall of the pair of thin films and the substrate, another region of the pair of thin films, and a surface region in contact with the other region of the substrate are: It preferably contains conductive impurities.

[0049]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

First, the first embodiment will be described.

FIGS. 1 and 2 show the first embodiment of the present invention, respectively.
FIG. 8 is a drawing schematically showing a manufacturing process according to the embodiment. 1 and 2, (a) to (k) are perspective views. Hereinafter, the first embodiment will be described with reference to FIGS. 1 and 2.

First, as shown in FIG.
0) A silicon substrate 11 having an exposed surface is prepared, and a thermal oxide film 12 having a thickness of about 5 nm is formed on the surface. After that, silicon nitride is deposited on the thermal oxide film 12 by LPCVD to form a silicon nitride film 13 having a thickness of about 150 nm.

Next, a resist pattern (not shown) is formed on the silicon nitride film 13 by using a photolithography technique or an EB drawing method. Further, as shown in FIG. 1B, the silicon nitride film 13, the oxide film 12, and the silicon substrate 11 are etched using RIE (Reactive Ion Etching) to form an element region 15. The groove 14 formed at this time is used for element isolation (STI: Shallow Trench) later.
Isolation). The depth of the groove is, for example, 300
Set to about nm.

Thereafter, a TEOS-based oxide film 1 having a thickness of, for example, about 600 nm is formed on the surface of the substrate 11 on which the grooves 14 are formed.
6 is formed by the CVD method, and TEOS is
Embed with system oxide. Further, as shown in FIG. 1C, the TEOS-based oxide film 16 is formed by CMP (Chemical Mechanical).
cal Polishing). At this time, since the silicon nitride film 13 functions as a stopper film, the CM
Polishing of the TEOS-based oxide film 16 by the P method can be stopped when the silicon nitride film 13 is exposed. The thickness of the silicon nitride film 13 is slightly reduced by performing the CMP, but the CMP conditions are controlled so that about 130 nm remains.

Next, as shown in FIG. 1D, a groove 17 for burying the gate electrode is formed. This is performed by the following method. First, a resist pattern (not shown) is formed on a region other than a region where a gate electrode is to be formed by using a photolithography technique or performing EB lithography. Next, the silicon nitride film 13 and the TEOS oxide film 16 located in the region where the gate electrode is to be formed are removed by etching using RIE. If necessary, a polysilicon film may be formed below the silicon nitride film. In this case, the RIE of the silicon nitride film can be stopped when the polysilicon film is exposed.

This groove 17 is preferably formed at a depth equal to the thickness of silicon nitride film 13. In addition, when the RIE of the silicon nitride film 13 and the RIE of the oxide film 16 are separately performed under conditions that provide a sufficient etching selectivity, the following advantages can be obtained. This will be described with reference to FIGS.

FIG. 3A schematically shows the same step as that shown in FIG. 1D, and FIG. 3B and FIG. 3C show the BB ′ line and FIG. It is sectional drawing along CC '.

As shown in FIG. 3B, RIE of the TEOS oxide film 16 is performed first, and
When E is performed, the thermal oxide film 12 below the nitride film 13 remains, so that the silicon substrate 11 is not damaged by RIE. Further, the RIE of the TEOS oxide film 16 is made slightly smaller, and the TEOS oxide film 16 is stopped at a position where the side surface of the element isolation groove is not exposed. In this manner, formation of a parasitic transistor at a channel edge portion when a transistor is formed later can be prevented.

On the other hand, as shown in FIG. 3C, RIE of the nitride film 13 is performed first, and then RIE of the oxide film 16 is performed.
Is performed, the oxide film 12 under the nitride film 13 is removed, so that the silicon substrate 11 is subjected to RIE damage.
Further, under the condition that a sufficient etching selectivity cannot be obtained between the nitride film and the oxide film, the nitride film 13 and the oxide film 16
Is performed simultaneously, the oxide film 12 is removed and the silicon substrate 11 is subjected to RIE damage. Further, in this case, a parasitic transistor is formed at the channel edge portion, so that device characteristics are degraded.

Returning to the description of the manufacturing process shown in FIGS. As shown in FIG. 1E, a polysilicon film 18 is formed on the surface of the substrate 11 on which the groove 17 is formed by LPCVD.
Is formed to a thickness of about 300 nm, and the trench 17 is filled with polysilicon. Further, the polysilicon film 18 is left only in the groove 17 by the CMP method. This polysilicon film 18 is used as a dummy gate wiring. Thus, the polysilicon film 18, the TEOS oxide film 1
The heights of the upper surfaces of the silicon nitride film 13 and the silicon nitride film 13 are made uniform to realize complete flattening. In this step, the CMP conditions are controlled so that the silicon nitride film 13 and the polysilicon film 18 remain at a thickness of about 110 nm.

Next, as shown in FIG. 1F, the silicon nitride film 13 is removed by performing etching with hot phosphoric acid, and a groove 19 is formed. In this way,
The height of the polysilicon film 18 as the dummy gate wiring is made equal to the height of the TEOS oxide film 16 constituting the element isolation region, and a structure is obtained in which only the region where the source electrode and the drain electrode are formed is depressed.

Next, as shown in FIG. 2G, the side and top surfaces of the polysilicon film 18 are oxidized to form an oxide film 20 having a thickness of about 4 nm.

Next, as shown in FIG.
On the surface on which the groove 19 is formed, a thickness of 1 is formed by LPCVD.
A silicon nitride film 21 of about 5 to 20 nm is formed. Further, using the entire surface RIE, the silicon nitride film 21 is selectively left on the side walls of the trench (the side wall of the polysilicon film 18 and the side wall of the TEOS oxide film 16), and the remaining silicon nitride film 21 is removed. After that, a source diffusion layer and a drain diffusion layer (not shown) are formed in a surface region located at the bottom of the groove of the silicon substrate 11. As a forming method, an ion implantation method, a solid phase diffusion method, a gas phase diffusion method, or the like can be given. If necessary, Si in a region where a source / drain is formed may be lifted by using an epitaxial growth method, that is, an elevated source / drain structure may be formed.

Next, as shown in FIG.
The thermal oxide film 12 on the drain region is removed by RIE or the like to expose the silicon surface, and silicide is sputtered to form a silicide (Co silicide or Ti silicide) film 22 having a thickness of about 100 nm. Then, C
The silicide on the polysilicon 18 (on the gate region) and the TEOS oxide film 16 (on the element isolation region) is removed by the MP method, and the silicide 2 is formed only on the source / drain regions.
2 is left. Thus, the silicide film 22 can be formed on the source / drain regions in a self-aligned manner without performing the silicidation annealing. Therefore, generation of crystal defects can be reduced.

Although the silicide film is buried in this embodiment, a tungsten film may be buried.
This is because not only silicide but also metal such as tungsten may be directly adhered on the source / drain regions in order to achieve the purpose of reducing the resistance of the source / drain regions. The transistor formed in this manner exhibits good electrical characteristics at high speed due to low leakage and low resistance of the source / drain regions. The following description is made for a case where silicide is attached to the source / drain regions, but the same applies to the case of tungsten.

After the silicide film 22 is buried in the step of FIG. 2 (i), if necessary, FIGS. 4 (a) to 4 (c)
As shown in (1), the silicide film 22 on the source / drain region is recessed by about 50 nm by etching (that is, the thickness of the silicide film 22 becomes about 50 nm), and a groove formed by this is formed by LPCVD and CMP. It may be embedded with a TEOS-based oxide film 31 serving as a cap film.

In this example, after the step shown in FIG. 2I, as shown in FIG. 2J, the polysilicon film 18 serving as the dummy gate wiring is removed by RIE or the like, and the oxide film 12 thereunder is removed.
Is removed with an HF-based etchant, thereby forming the groove 2
Form 3

Next, as shown in FIG. 2K, a gate insulating film 24 having an oxide film equivalent effective thickness (T _eff ) of about 3 to 4 nm is formed by a deposition method or a thermal oxidation method. Since the source / drain regions have already been formed (including activation) and there is basically no high-temperature process thereafter, a Ta ₂ O ₅ film or a (Ba, Sr) TiO ₃ film is used for the gate insulating film 24. For example, a high-dielectric film or a ferroelectric film can be used. Further, a high melting point metal can be used for the gate electrode (gate wiring). When a high dielectric film or a ferroelectric film is used for the gate insulating film, it is necessary to select a gate wiring material according to the type of the gate insulating film to be used. Ru, TiN, Al, or the like can be used for the gate wiring. In this example, a silicon oxynitride film is used for the gate insulating film 24. Subsequently, a barrier metal (TiN or tungsten nitride, not shown) having a thickness of about 5 to 10 nm is formed on the gate insulating film 24. Further, a gate wiring 25 is formed by depositing a metal gate wiring material such as tungsten thereon by the CVD method and flattening the material by a CMP method.

Thereafter, if necessary, the metal gate wiring 25 is recessed by etching by about 30 nm (that is, the thickness of the metal gate wiring 25 becomes about 70 nm). In this case, the groove formed by the LPCV
A silicon nitride film serving as a cap film is formed on the upper surface of the metal gate by embedding with silicon nitride by using the D method and the CMP method. When such a process is adopted, even if a contact hole is erroneously formed on a gate wiring in a later step, the silicon nitride film serves as an etching stopper, so that a short-circuit between another wiring and the gate wiring is performed. Failure can be prevented.

FIG. 5 shows the source / drain electrodes 22.
An example is shown in which, for example, a TEOS oxide film 31 is formed as a cap film and a silicon nitride film 32 is formed as a cap film on the gate wiring 25.

The subsequent steps follow a normal LSI manufacturing process. That is, an interlayer insulating film such as TEOS is deposited and formed, and a contact hole for connecting a gate electrode, a source / drain electrode, and an upper wiring is formed in the interlayer insulating film. Further, a metal wiring such as aluminum is formed on the interlayer insulating film in which the contact hole is formed.

Next, a second embodiment of the present invention will be described.

FIGS. 6A to 6D are diagrams schematically showing a manufacturing process according to the second embodiment of the present invention. In addition,
The second embodiment is different from the first embodiment only in the step shown in FIG. 2 (i), and the other steps are the same. Therefore, only the steps corresponding to the steps shown in FIG.

In this example, as shown in FIG. 6A, the silicide film 22 does not completely fill the trench on the source / drain region. Therefore, as shown in FIG.
The groove formed by the silicide film 22 is formed by TEO by CVD.
The surface is buried with the S oxide film 41 and its surface is planarized by the CMP method. After the step of FIG. 6B, if necessary, as shown in FIG.
FIG. 6 shows a groove formed by recessing
As shown in (d), the TEOS oxide film 4 is formed by the CVD method.
2 is buried and flattened. Thus, a cap film including the TEOS oxide films 41 and 42 can be formed on the silicide film 22. The subsequent steps are:
This is the same as in the first embodiment.

In the second embodiment, when the trenches on the source / drain regions cannot be completely filled with the silicide film 22, the remaining trenches are filled with a TEOS oxide film, and the adverse effects on the subsequent steps are reduced. This is an effective way to prevent this.

Next, a third embodiment of the present invention will be described.

FIG. 7 is a view schematically showing a manufacturing process according to the third embodiment of the present invention. Note that, in the third embodiment, the steps shown in FIGS. 1A to 1D of the first embodiment are performed, and the subsequent steps are different. Therefore, steps subsequent to the step shown in FIG. 1D will be described.

First, as shown in FIG. 7A, the oxide film 12 at the bottom of the trench 17 for burying the gate wiring is formed.
Is removed with an HF-based solution. Next, as shown in FIG. 7B, a gate insulating film 51 is formed. After that, LPCVD
A polysilicon film 52 serving as a gate electrode (gate wiring) is formed to a thickness of about 300 nm by a method, and the trench 17 is buried, and this is planarized by a CMP method. In this manner, the surface heights of the polysilicon film 52, the TEOS oxide film 16, and the silicon nitride film 13 are made uniform, and complete planarization is realized. At the time of CMP, the CMP conditions are controlled so that the silicon nitride film 13 and the polysilicon film 52 remain at a thickness of about 100 nm.

Next, as shown in FIG. 7C, the silicon nitride film 13 is removed by etching using hot phosphoric acid, and a groove 19 is formed. In this manner, the height of the polysilicon film 52 serving as a gate wiring and the T
The height of the EOS oxide film 16 is made uniform to form a structure in which only the region where the source / drain electrodes are formed is depressed.

Next, as shown in FIG. 7D, the surface of the polysilicon film 52 is oxidized to form an oxide film 5 having a thickness of about 4 nm.
Form 3

Next, as shown in FIG.
Silicon nitride film 2 having a thickness of about 15 to 20 nm by D method
Form one. Further, the silicon nitride film 21 is selectively left on the side walls of the trench (the side walls of the polysilicon film 52 and the side wall of the TEOS oxide film 16) by RIE, and the remaining silicon nitride film 21 is removed. After that, a source diffusion layer and a drain diffusion layer (not shown) are formed.
As a forming method, an ion implantation method, a solid phase diffusion method, a gas phase diffusion method, or the like can be considered. If necessary, an elevated source / drain structure may be formed by using an epitaxial growth method.

Next, as shown in FIG.
The thermal oxide film 12 on the drain region is removed by RIE or the like to expose the silicon surface. Furthermore, silicide (Co
(Silicide or Ti silicide) to a thickness of 10
A silicide film 22 of about 0 nm is formed. Then, C
The silicide on the polysilicon gate 52 and the TEOS oxide film (element isolation region) 16 is removed by the MP method, and the silicide film 22 is left only on the source / drain regions. In this manner, the silicide 22 can be formed in a self-aligned manner on the source / drain regions without performing the silicidation annealing. Therefore, generation of crystal defects can be reduced.

Although the silicide film is buried in the process shown in FIG. 7, a tungsten film may be buried. This is because a metal such as tungsten may be directly adhered on the source / drain region in order to achieve the purpose of reducing the resistance of the source / drain region. The transistor formed in this manner exhibits good electrical characteristics at high speed due to low leakage and low resistance of the source / drain regions.

The subsequent steps follow a normal LSI manufacturing process. That is, an interlayer insulating film such as TEOS is deposited,
Then, a contact hole for connecting the gate wiring or the source / drain electrode to the upper wiring is formed. Further, a metal wiring made of aluminum or the like is formed on the interlayer insulating film in which the contact hole has been formed.

As described above, the first to third embodiments of the present invention
According to the embodiment, a MOSFET in which the source / drain electrodes are made of silicide can be obtained without performing silicidation annealing.

Conventionally, in a fine device, a low-resistance silicide, which is a compound of a high melting point metal and silicon, is used as an electrode (source / drain electrode) above the source / drain region.
And gate electrodes. However, in such a conventional device, dislocations are likely to occur near the interface between silicide and silicon due to stress accompanying volume expansion during silicidation annealing.
These dislocations reduce the reliability of the gate insulating film, or cause pn in the channel region or the source / drain region.
It degrades the properties of the electrically active region that forms the junction.

As described above, conventionally, when the source / drain electrodes are formed in a self-aligned manner by using a low-resistance material such as silicide, there has been a problem that the reliability of the device and the characteristic deterioration are likely to occur. .

On the other hand, according to the first to third embodiments, without performing the silicidation annealing,
MOSFE whose source and drain electrodes are made of silicide
T can be obtained. Therefore, according to the first to third embodiments, the source / drain electrodes can be formed in a self-aligned manner by using a low-resistance material such as silicide, and furthermore, it is possible to prevent a reduction in device reliability and a deterioration in characteristics. A semiconductor device and a method for manufacturing the same are provided.

Next, a fourth embodiment of the present invention will be described.

FIGS. 8 and 9 are views schematically showing a manufacturing process according to the fourth embodiment of the present invention. In the fourth embodiment, FIGS. 1A to 1C of the first embodiment are used.
The step shown in (d) is performed, and the subsequent steps are different from those of the first embodiment. Therefore, steps subsequent to the step shown in FIG. 1D will be described.

As shown in FIG. 8A, a silicon oxide film (hereinafter, referred to as a FOX film) 18 containing hydrogen is
The groove 17 is formed to a thickness of about nm, and the groove 17 is buried, and this is flattened by the CMP method. The FOX film 18 is made of H
It has a composition represented by _0.5 SiO _0.5 and is characterized by a higher HF etching rate than a normal SiO ₂ film formed by thermal oxidation. The FOX film 18 left in the groove 17 is used as a dummy gate wiring.

As described above, the FOX film 18, TEO
The surface heights of the S oxide film 16 and the silicon nitride film 13 are made uniform to realize complete flattening. At the time of the CMP, the CMP conditions are controlled so that the silicon nitride film 13 and the FOX film 18 remain at a thickness of about 110 nm.

Next, as shown in FIG. 8B, the silicon nitride film 13 is removed by etching using hot phosphoric acid, and a groove 19 is formed. Thus, the height of the FOX film 18 serving as the dummy gate electrode and the T
The height of the EOS oxide film 16 is made uniform to form a structure in which only the region where the source / drain electrodes are formed is depressed.

Next, as shown in FIG.
Silicon nitride film 2 having a thickness of about 10 to 20 nm by D method
Form one. Further, the entire surface is etched by RIE (side wall of the FOX film 18 and side wall of the TEOS oxide film 16).
The silicon nitride film 21 is selectively left thereon, and the remaining silicon nitride film 21 is removed. At this time, the oxide film 1
The exposed portion 2 is thinned or removed by the RIE. Thereafter, the silicon surface is exposed in the groove 19 by performing RIE or HF wet etching for a short time.

Next, as shown in FIG. 8D, Si in the region where the source / drain is to be formed is enlarged upward by epitaxial growth (a single-crystal silicon film is formed). Further, as shown in FIG. 9E, the overgrown portion like the lateral grouse portion 22A is subjected to CMP.
The crystalline silicon film 22 only in the groove 19
Is left.

Thereafter, the NMO is deposited in the crystalline silicon film 22.
A source / drain diffusion layer (not shown) for S and PMOS is formed. As a forming method, an ion implantation method, a solid phase diffusion method, a gas phase diffusion method, or the like can be considered. Further, a heat treatment for activating the conductive impurities is performed.

In this example, after the step shown in FIG. 9E, as shown in FIG.
The film 18 is removed with an HF solution or the like, and the underlying oxide film 12 is
The groove 23 is formed by removing with a system etchant. As described above, since the FOX film 18 has a higher HF etching rate than the TEOS-based oxide film 16,
It can be selectively removed.

Next, by performing etching using hot phosphoric acid or the like, a portion constituting a part of the side wall of the trench 23 of the nitride film 21 is removed. At this time, the other nitride film 2
It is believed that the top of 1 is etched. However, since the thickness of the nitride film 21 is small, short time etching is sufficient. Therefore, for example, the other nitride film 2
Even if the upper part of 1 is etched, the amount removed is small, so that no adverse effect is caused.

Next, as shown in FIG. 9G, a gate insulating film 24 having an effective oxide film equivalent thickness (T _eff ) of about 2 to 3 nm is formed by using a deposition method or a thermal oxidation method. Since the source / drain regions (including activation) have already been formed and there is basically no high-temperature step of 600 ° or more after this, a Ta ₂ O ₅ film or (Ba, S
r) A high dielectric film such as a TiO ₃ film or a ferroelectric film can be used. Further, a metal material can be used for the gate electrode (gate wiring). When a high dielectric film or a ferroelectric film is used for the gate insulating film, it is necessary to select a gate wiring material according to the type of the gate insulating film to be used. Ru, TiN, Al, W, etc. can be used for the gate wiring. Further, it is desirable to form a TiN film, a WN film, or the like as a barrier metal between the gate insulating film and the gate electrode.

In this embodiment, a silicon oxynitride film is used for the gate insulating film 24. Subsequently, as shown in FIG. 9G, a barrier metal (TiN or tungsten nitride, not shown) having a thickness of about 5 to 10 nm is formed on the gate insulating film 24. Next, a metal gate wiring material such as tungsten is deposited thereon by the CVD method, and is further flattened by the CMP method to form the gate wiring 2.
5 is formed.

Thereafter, if necessary, the metal gate wiring 25 is recessed by about 30 nm by etching (that is, the thickness of the metal gate wiring 25 becomes about 70 nm). Further, the groove formed thereby is formed by LPCVD.
And then buried with silicon nitride using CMP,
A silicon nitride film serving as a cap film is formed on the upper surface of the metal gate. When such a process is adopted, when a contact hole is erroneously formed on the gate wiring in a later step, this silicon nitride film serves as an etching stopper, and short-circuits between another wiring and the gate wiring. Failure can be prevented.

FIG. 9H shows the metal gate wiring 2
5 shows an example in which, for example, a silicon nitride film 32 is formed as a cap film.

The subsequent steps follow a normal LSI manufacturing process. That is, an interlayer insulating film such as TEOS is deposited and formed, and a contact hole for connecting a gate electrode, a source / drain electrode, and an upper wiring is formed in the interlayer insulating film. Further, a metal wiring such as aluminum is formed on the interlayer insulating film provided with the contact hole.

Next, a fifth embodiment of the present invention will be described.

FIG. 10 is a diagram schematically showing a manufacturing process according to the fifth embodiment of the present invention. Note that, in the fifth embodiment, the steps shown in FIGS. 1A to 1D of the first embodiment are performed, and the subsequent steps are different.
Therefore, steps subsequent to the step shown in FIG. 1D will be described.

First, as shown in FIG. 10A, the oxide film 1 at the bottom of the groove 17 for burying the gate electrode is formed.
2 is removed with an HF solution. Next, as shown in FIG. 10B, for example, an HTO film 24 is formed as a gate insulating film. Thereafter, a polysilicon film 25 serving as a gate electrode (gate wiring) is formed to a thickness of about 400 nm by LPCVD to fill the trench 17, and the trench 17 is planarized by CMP. Thus, the polysilicon film 2
5. The surface heights of the TEOS oxide film 16 and the silicon nitride film 13 are made uniform to realize complete flattening. At the time of CMP, the silicon nitride film 13 and the polysilicon film 25
The CMP conditions and the film forming conditions (film thickness) are controlled so that the film remains with a thickness of about nm. If necessary, NMOS
Polysilicon film 25 for each of
Doping.

Thereafter, the polysilicon film 25 is recessed by about 50 nm by RIE or CDE (that is, the thickness of the polysilicon film 25 becomes about 150 nm), and a groove formed by the recess is formed by using LPCVD and CMP. It is embedded with a TEOS-based oxide film 32 serving as a cap film.

Next, as shown in FIG. 10C, the silicon nitride film 13 is removed by etching using hot phosphoric acid, and a groove 19 is formed. In this way, the height of the TEOS oxide film 32 serving as the cap film is made equal to the height of the TEOS oxide film 16 in the element isolation region, and a structure in which only the region where the source / drain electrodes are formed is recessed.

Next, as shown in FIG.
By performing _2- RIE for a short time, the exposed oxide film 12 is removed, and the silicon surface is exposed in the groove 19.

Next, as shown in FIG. 10E, the Si in the region where the source / drain is to be formed is enlarged upward by epitaxial growth (a single-crystal silicon film is formed). Further, the overgrown portion such as the lateral grouse portion is removed by the CMP method, and the crystalline silicon film 22 is left only in the groove portion 19.

Then, NMO is added to the crystalline silicon film.
Source / drain regions for S and PMOS (not shown)
To form As a forming method, an ion implantation method, a solid phase diffusion method, a gas phase diffusion method, or the like can be considered. Further, a heat step for activating the conductive impurities is performed.

The subsequent steps follow a normal LSI manufacturing process. That is, an interlayer insulating film such as TEOS is formed,
Then, a contact hole for connecting the gate electrode or the source / drain electrode to the upper wiring is formed. Further, a metal wiring made of aluminum or the like is formed on the interlayer insulating film in which the contact hole has been formed.

Next, a sixth embodiment of the present invention will be described.
This will be described with reference to FIGS.

First, except that the polysilicon film 13 is formed instead of the silicon nitride film 13, FIGS.
The same steps as shown in (d) are performed.

Next, as shown in FIG. 8A, a silicon nitride film 18 is formed to a thickness of about
Is buried and planarized by a CMP method. In addition,
The silicon nitride film 18 is used as a dummy gate wiring. As described above, the surface heights of the silicon nitride film 18, the TEOS oxide film 16, and the polysilicon film 13 are made uniform to realize complete flattening. At the time of CMP, the CMP conditions are controlled so that the polysilicon film 13 and the silicon nitride film 18 remain at a thickness of about 110 nm.

Next, as shown in FIG. 8B, the polysilicon film 13 is removed by etching using the RIE method, and a groove 19 is formed. In this manner, the height of the silicon nitride film 18 as the dummy gate wiring is made equal to the height of the TEOS oxide film 16 in the element isolation region, and a structure is formed in which only the region where the source / drain electrodes are formed is depressed.

Next, as shown in FIG.
A TEOS-based oxide film 21 having a thickness of about 15 to 20 nm is formed by the method D. Further, the entire surface is subjected to RIE so that the side wall of the trench (the side wall of the silicon nitride film 18 and the TEOS-based oxide
The TEOS-based oxide film 21 is selectively left on the (side wall 6) and the remaining TEOS-based oxide film 21 is removed. At this time, the exposed oxide film 12 is thinned or removed by the RIE. After that, RIE or H
The silicon surface is exposed in the groove 19 by performing the F-based wet etching for a short time.

Next, as shown in FIG. 8D, Si in the region where the source / drain is to be formed is expanded upward by epitaxial growth (a single-crystal silicon film is formed). Further, as shown in FIG. 9E, the overgrown portion like the lateral grouse portion 22A is subjected to CMP.
The crystalline silicon film 22 only in the groove 19
Is left.

After that, N.
A source / drain diffusion layer (not shown) for MOS and PMOS is formed. As a forming method, an ion implantation method,
A solid-phase diffusion method, a gas-phase diffusion method, and the like are conceivable. Further, a heat treatment for activating the conductive impurities is performed.

In this example, after the step shown in FIG. 9E, as shown in FIG. 9F, the silicon nitride film 18 serving as the dummy gate wiring is removed by using hot phosphoric acid, so that the trench 23 is formed. To form

Next, by performing etching using HF or the like, a portion constituting a part of the side wall of the groove 23 of the TEOS-based oxide film 21 is removed. At that time, other TEO
It is considered that the upper surfaces of the S-based oxide film 21 and the TEOS-based oxide film 16 are etched. However, since the thickness of the TEOS-based oxide film 21 is small, short time etching is sufficient. Therefore, even if the other portions of the TEOS-based oxide film 21 and the TEOS-based oxide film 16 are etched, the removal amount is small, so that the device characteristics are not adversely affected.

Further, the structure shown in FIGS. 9G and 9H is obtained by the same method as described in the fourth embodiment.

Next, a seventh embodiment of the present invention will be described.

FIG. 11 is a diagram schematically showing a manufacturing process according to the seventh embodiment of the present invention. Note that, in the seventh embodiment, the same steps are performed up to the step shown in FIG. 9E of the sixth embodiment, and the subsequent steps are different from the sixth embodiment.

First, the structure shown in FIG. 9E is obtained by the same method as described in the sixth embodiment. Note that FIG. 11A shows one of the semiconductor devices shown in FIG.
It is sectional drawing along 1A-11A 'line.

Next, as shown in FIG. 11B, the crystalline silicon film 22 is recessed by about 50 nm by RIE or the like. Thereafter, the NMOS and PM are formed in the crystalline silicon film 22.
A source / drain diffusion layer (not shown) for the OS is formed. As a forming method, an ion implantation method, a solid phase diffusion method, a gas phase diffusion method, or the like can be considered. Further, a heat treatment for activating the conductive impurities is performed.

Next, as shown in FIG. 11C, a metal material film 31 made of cobalt silicide, tungsten, or the like is formed by a sputtering method or a CVD method. Embed with Further, the metal material film 31 is left only in the groove by the CMP method.

Thereafter, as shown in FIG. 11D, the silicon nitride film 18 serving as the dummy gate wiring is removed by using hot phosphoric acid to form the groove 23.

Next, the structure shown in FIG. 11E is obtained by a method similar to that described in the sixth embodiment.
In this example, the gate insulating film 24 is made of Ta ₂ O ₅
And the gate wiring 25 is made of Al. If necessary, a SiO ₂ film or a SiN film having a thickness of about 0.5 nm may be formed under the Ta ₂ O ₅ film. In this case, the film can be formed at a low temperature (600 ° C. or lower) by using radical oxidation or radical nitridation.

Then, if necessary, as shown in FIG. 11F, the surface of the Al metal gate wiring 25 is oxidized, and an alumina (Al ₂ O ₃ ) film 32 is formed on the upper surface of the gate wiring 25 as a cap film. To form When such a process is adopted, when a contact hole is erroneously formed on the gate wiring in a later step, this alumina film 3
2 serves as an etching stopper and can prevent a short circuit between another wiring and a gate wiring.

The subsequent steps follow a normal LSI manufacturing process. That is, an interlayer insulating film such as TEOS is deposited and formed, and a contact hole for connecting a gate electrode, a source / drain electrode, and an upper wiring is formed in the interlayer insulating film. Further, a metal wiring made of aluminum or the like is formed on the interlayer insulating film.

Next, an eighth embodiment of the present invention will be described.
This will be described with reference to FIG.

FIG. 12 is a diagram schematically showing a manufacturing process according to the eighth embodiment of the present invention. In the eighth embodiment, the steps up to the step shown in FIG. 1D of the first embodiment are performed in the same manner, and the subsequent steps are different from those of the first embodiment. Therefore, steps subsequent to the step shown in FIG. 1D will be described.

After forming the structure shown in FIG. 1D, FIG.
As shown in FIG. 2A, a dummy gate wiring 18 is formed in the groove 17. The dummy gate wiring 18 is made of TiN,
It can be made of WN _x , W, Al, Ge, RuO _x or the like. Since these materials can be easily removed by SH treatment or the like, they are preferably used for the dummy gate wiring 18. Hereinafter, a case where the dummy gate wiring 18 is a germanium film will be described.

A germanium film 18 is formed to a thickness of about 300 nm to fill the groove 17, and this is flattened by the CMP method. Thus, the germanium film 18,
The surface heights of the TEOS oxide film 16 and the silicon nitride film 13 are made uniform to realize complete flattening. At the time of CMP, the CMP conditions are controlled so that the silicon nitride film 13 and the germanium film 18 remain at a thickness of about 110 nm.

Next, as shown in FIG. 12B, the silicon nitride film 13 is removed by etching using hot phosphoric acid, and a groove 19 is formed. Thus, the height of the germanium film 18 and the TEOS oxide film 1 in the element isolation region are set.
6, the height of each of them is made uniform to form a structure in which only the region where the source / drain electrodes are formed is depressed.

Next, as shown in FIG.
Silicon nitride film 21 having a thickness of 10 to 20 nm by VD method
Is formed, and the silicon nitride film 21 is selectively left on the side walls of the trench 19 (side surfaces of the germanium film 18 and side surfaces of the TEOS-based oxide film 16) by RIE. This RI
With E, the exposed oxide film 12 is thinned or removed. Thereafter, the silicon surface is exposed in the groove 19 by performing RIE or HF wet etching for a short time.

Next, H ₂ cleaning is performed, and FIG.
As shown in (d), the Si in the region where the source / drain is to be formed is enlarged upward using an epitaxial growth method (a single-crystal silicon film is formed). Further, the overgrown portion (not shown) such as the lateral grouse portion is removed by the CMP method, and the crystalline silicon film 22 is left only in the groove 19.

Thereafter, the NMO is deposited in the crystalline silicon film 22.
A source / drain diffusion layer (not shown) for S and PMOS is formed. As a forming method, an ion implantation method, a solid phase diffusion method, a gas phase diffusion method, or the like can be considered. Next, a heat treatment step (RTA or the like) for activating the conductive impurities is performed. Furthermore, Ti
Or Co is sputtered to form a silicide film on the source / drain regions.

In this example, after the step shown in FIG.
As shown in FIG. 12E, the trench 23 is formed by removing the germanium film 18 as the dummy gate wiring and the oxide film 12 thereunder by SH treatment and HF wet etching.

Next, by performing etching using hot phosphoric acid or the like, a portion constituting a part of the side wall of the groove 23 of the nitride film 21 is removed. At this time, the other nitride film 2
It is believed that the top of 1 is etched. However, since the thickness of the nitride film 21 is small, short time etching is sufficient. Therefore, for example, the other nitride film 2
Even if the upper part of 1 is etched, the removal amount is small, so that the element characteristics are not adversely affected.

Further, the structure shown in FIG. 12F is obtained by the same method as described in the fourth embodiment.

Thereafter, if necessary, the metal gate wiring 25 is recessed by etching by about 30 nm (that is, the thickness of the metal gate wiring 25 becomes about 70 nm). Further, the groove formed thereby is formed by LPCVD.
And then buried with silicon nitride using CMP,
A silicon nitride film serving as a cap film is formed on the upper surface of the metal gate. When such a process is adopted, when a contact hole is erroneously formed on the gate wiring in a later step, this silicon nitride film serves as an etching stopper, and short-circuits between another wiring and the gate wiring. Failure can be prevented.

The subsequent steps follow a normal LSI manufacturing process. That is, an interlayer insulating film such as TEOS is deposited and formed, and a contact hole for connecting a gate electrode, a source / drain electrode, and an upper wiring is formed in the interlayer insulating film. Further, a metal wiring made of aluminum or the like is formed on the interlayer insulating film.

According to the above-described first to eighth embodiments, prior to the formation of the source / drain electrodes, the gate structure and the element isolation insulating film are formed so that their upper surfaces are equal in height, and A trench that intersects the structure and is divided into gate structures is formed. In addition, source / drain electrodes are formed in the groove. Therefore, according to the first to eighth embodiments, the source / drain electrodes can be formed in a self-aligned manner. That is, according to the first to eighth embodiments, since the height of the upper surface of the gate structure is equal to the height of the upper surface of the element isolation insulating film, a metal material can be embedded in the source / drain regions by using the CMP method. . When the trench is buried with a silicon film using an epitaxial growth method, an overgrown portion such as a lateral glow portion can be removed by a CMP method. Therefore, the insulating state between the adjacent transistors can be favorably maintained, and a high-density fine transistor can be realized.

According to the fourth to eighth embodiments, a concave type transistor can be obtained without performing RIE on a portion of a substrate where a channel region is formed.
Therefore, it is possible to prevent RIE damage to the channel region when a concave transistor is manufactured. That is, deterioration of the electric characteristics of the element can be prevented.

Further, in the first to eighth embodiments,
When the source / drain electrodes are composed of silicide, the source / drain electrodes can be formed by performing silicide sputtering without performing silicidation annealing. Therefore, it is possible to prevent a decrease in the reliability and characteristics of the device.

In the first to eighth embodiments, when the elevated source / drain structure is adopted,
The source / drain regions can be formed to a sufficient thickness, and the effective junction depth can be reduced. Therefore, even when the size is reduced, it is possible to prevent the occurrence of punch-through and to maintain the insulating state between the elements.

In the first to eighth embodiments, components denoted by the same reference numerals are substantially the same unless otherwise specified.

Next, a ninth embodiment of the present invention will be described.
This will be described with reference to FIGS.

FIGS. 13 to 15 are views schematically showing a manufacturing process of the semiconductor device according to the ninth embodiment of the present invention. (A) to (o), (q) and (r) are sectional views, and (p) is a plan view.

First, as shown in FIG. 13A, a thermal oxide film 102 having a thickness of about 4 nm is formed on one surface of a silicon substrate 101. Then, the CVD is performed on the thermal oxide film 102.
The polysilicon film 103 having a thickness of about 200 nm
To form

Next, as shown in FIG. 13B, a trench 104 is formed by etching the polysilicon film 103, the thermal oxide film 102 and the silicon substrate 101 by using lithography and RIE. The groove 104 is used later for element isolation.

Further, as shown in FIG. 13C, a thermal oxide film 105 is formed on the exposed surfaces of the polysilicon film 103 and the silicon substrate 101.

Thereafter, as shown in FIG. 13D, a silicon oxide film 106 is formed by CVD on the surface of the substrate 101 on which the groove 104 has been formed, and the groove 104 is filled with silicon oxide. Further, the silicon oxide film 106 is
Polishing by MP method. This polishing is performed on the polysilicon film 1
Stop when 03 is exposed. The element isolation region is formed as described above.

Next, as shown in FIG. 13E, a thermal oxide film 107 is formed on the exposed surface of the polysilicon film 103, and a SiN film 108 having a thickness of about 150 nm is formed thereon. This thermal oxide film 107 is used as an etching stopper. Furthermore, lithography technology and R
Using the IE technology, only the SiN film 108 located in the region where the gate wiring is to be formed is left, and other SiN films 108 are left.
The film 108 is removed.

Next, as shown in FIG. 13F, the thermal oxide film 1 is formed by RIE or wet etching for a short time.
The exposed portion of 07 is removed. Further, the polysilicon film 103 is etched using the SiN film 108 and the silicon oxide film 106 as a mask.

Note that in the step shown in FIG.
The groove 104 may be formed in a forward tapered shape. Groove 10
In the case where the silicon film 1 is formed as described above, the silicon film 1 is formed as shown in FIG.
The polysilicon film 103 remains on the side wall of the substrate 03. Since the polysilicon film 103 becomes a gate electrode later, the parasitic capacitance between the gate electrode and the source / drain electrode may be increased. Therefore, the silicon oxide film 1
The taper angle of the groove portion 104 is set so that all of the polysilicon film 103 remaining on the sidewalls of 06 becomes an oxide film in the subsequent thermal oxidation step.

Thereafter, as shown in FIG. 14H, a thermal oxide film 109 having a thickness of about 4 nm is formed on the side surface of the polysilicon film 103 to protect the gate edge. When the trench 104 is formed in a forward tapered shape, the polysilicon film 1 remaining on the side wall of the silicon oxide film 106
Oxidize all of 03. Further, an extension is formed in a surface region of the substrate 101 by performing ion implantation and activation on the substrate 101, and then, SiN is formed by a CVD method.
Form a film. By further performing RIE, FIG.
As shown in (i), the SiN film is replaced with the polysilicon film 10.
3. Thermal oxide film 105, thermal oxide film 107, and SiN film 1
08 is selectively left only on the side surfaces of the SiN side walls 11.
0 is formed.

At this point, a deeper diffusion region may be formed in the surface region of the substrate 101 by performing ion implantation. In this example, since an elevated source / drain structure is formed in a step described later, it is not necessary to form a deep diffusion region here. That is, here, only the extension is sufficient. The side wall 110 is provided for the purpose of reducing the coupling capacitance between the source / drain electrode and the gate electrode and preventing the occurrence of a short circuit between the source / drain electrode and the gate electrode.

Next, the thermal oxide film 102 exposed by the wet processing is removed. Thereafter, as shown in FIG. 14J, a polysilicon film 111 is formed by the CVD method.
Further, as shown in FIG. 14K, the polysilicon film 1 is formed by using the CMP technique or the resist etch back technique.
11 is flattened. This planarization is performed until the SiN film 108 and the side wall 110 are exposed. As described above, the entire region except the region where the gate wiring is to be formed is covered with the polysilicon film 111. On the surface of the polysilicon film 111, a thermal oxide film (not shown) used as an etching stopper is formed.

Thereafter, as shown in FIG. 14 (l), a part of the side wall 110 and the S are etched by wet etching using hot phosphoric acid or the like, radical etching or RIE.
The iN film 108 is removed.

Further, the thermal oxide film (not shown) and the thermal oxide film 105 formed on the surface of the polysilicon film 111 are removed by wet processing.

Next, as shown in FIG. 15 (m), the polysilicon films 103 and 111 and the sidewall 110 made of SiN are formed.
The trench 112 is formed by removing the exposed portion of the silicon oxide film 106 by RIE using the mask as a mask. The silicon oxide film 106 is removed so that the channel edge is not exposed, that is, the side surface of the thermal oxide film 102 is not exposed. As a result, it is possible to prevent the gate breakdown voltage and the transistor characteristics from deteriorating, which are problems in the conventional STI structure.

Next, as shown in FIG.
01 on the surface where the groove 112 is formed.
Is formed. Further, as shown in FIG.
Flattening is performed using the P method or a resist etch-back technique. This planarization is performed until the silicon oxide film 106 is exposed.

FIG. 15 (p) is a plan view of the semiconductor device shown in FIG. 15 (o). As shown in this figure, the region where the gate electrode is formed is made of the polysilicon film 103, the region where the source / drain electrodes are formed is made of the polysilicon film 111, and the region where the gate wiring is formed is the polysilicon. It is composed of a silicon film 113. next,
Ion implantation is performed simultaneously on the polysilicon films 103, 111, and 113, and a heat treatment for activation is performed. Here, when the diffusion region formed in advance by the heat treatment becomes excessively deep, the extension may be formed by solid-phase diffusion of the dopant ion-implanted in this step without forming the extension in advance. . Thereby, the extension can be formed at a desired depth.

Next, as shown in FIG. 15 (q), a salicide process using Co or Ti or the like is performed.
As a result, a silicide film 114 is formed in the surface regions of the polysilicon films 103, 111, and 113. That is, the gate electrode and the source / drain electrodes are formed in a self-aligned manner. If the silicide film 114 is also formed on the side wall 110 due to the disturbance of the selection reaction, the CM
The surface may be slightly polished by a P method or the like. Thus, the silicide film 114 formed on the side wall 110 can be easily removed. Alternatively, as shown in FIG. 15 (r), before performing the salicide process, the polysilicon films 103, 111, and 113 are appropriately etched back so that the sidewalls 110 are formed on the polysilicon films 103, 111, and 1.
13 may be protruded.

As described above, according to the ninth embodiment of the present invention, when forming a MOSFET having an elevated source / drain structure and having source / drain electrodes made of silicide, It is possible to prevent the drain region from being formed on the STI. In addition, according to the present embodiment, since the gate edge is not exposed due to the STI receding, a MOSFET having excellent electric characteristics can be obtained.

Next, a tenth embodiment of the present invention will be described. In the present embodiment, a plurality of MOSFETs
Are formed simultaneously, the electrical connection between the source or drain electrode of one MOSFET and the source or drain electrode of another MOSFET, or the electrical connection between the source or drain electrode of one MOSFET and the gate electrode of another MOSFET Is performed.

FIGS. 16 to 18 schematically show the steps of manufacturing the semiconductor device according to the tenth embodiment of the present invention. Hereinafter, the two connection methods described above will be described with reference to FIGS.

First, the ninth embodiment shown in FIGS.
The structure shown in FIG. 16A or FIG. 16B is obtained by the same method as described with reference to (f) and FIGS. 14 (g) to (i). Note that FIG. 16C shows C- in FIG.
FIG. 16D is a sectional view taken along the line C ′, and FIG.
It is sectional drawing along the DD 'line of (b).

Next, the ninth embodiment shown in FIGS.
By performing the same steps as those described with respect to (l), the structures shown in FIGS. 16E and 16F are obtained.

Thereafter, as shown in FIGS. 17G and 17H, a resist film 120 is formed, and an opening is formed in the resist film 120 by using a lithography technique. Further, using this resist film 120 as a mask, the polysilicon film 111 is removed so that the silicon oxide film 106 is exposed. 17G and 17J are plan views of the semiconductor device shown in FIGS. 17G and 17H, respectively.

Next, as shown in FIGS. 17 (k) and (l), using the thermal oxide film 105, the polysilicon film 111, and the resist film 120 as a mask, RIE is performed.
The iN side wall 110 is etched. The SiN side wall 110 does not need to be completely removed. SiN sidewall 110
It is sufficient that the removal is performed to a position lower than the bottom surface of the silicide film formed in a later step.

Next, the resist film 120 is removed. Thereafter, the structures shown in FIGS. 18 (m) and 18 (n) are obtained by the same method as described with reference to FIG. 15 (m) of the ninth embodiment. Further, FIG. 15 of the ninth embodiment
The structures shown in FIGS. 18 (o) and (p) are obtained by the same method as described with respect to (n) to (q). 18 (q) and 18 (r) are plan views of the semiconductor device shown in FIGS. 18 (o) and 18 (p), respectively.

An example in which the above method is applied to the manufacture of an SRAM having a CMOS-6tr-cell structure will be described below.

FIGS. 19 to 23 schematically show the steps of manufacturing a semiconductor device according to the tenth embodiment of the present invention. 19 to 23 are plan views.

First, in the ninth embodiment, FIG.
By performing the steps described with respect to (a) to (d), FIG.
The structure shown in FIG. Note that, in FIG.
An NMOS element region 152, a PMOS element region 153, and an element isolation region 154 are formed on 1.

Next, as shown in FIG. 20, by forming a gate wiring pattern 155, the NMOS and PMOS gate wirings of the inverter circuit 156 in the cell are connected, and a word line 157 is formed.

Thereafter, as shown in FIG. 21, a bonding wiring region pattern 158 is formed. Conventionally, in a flip-flop circuit 170, a junction wiring 159 connecting a source / drain electrode of one element to a source / drain electrode of another element, and a source / drain electrode of one element and a gate electrode of another element are connected. It was formed in a separate layer from the connecting wiring 160 to be connected. That is, conventionally, it is necessary to provide one or more wiring layers in order to form at least one of the bonding wirings 159 and 160 separately from the layer in which the gate wiring is formed. On the other hand, according to the tenth embodiment, the above-described wiring can be formed in the layer where the gate wiring is formed. Therefore, only the bit line, the V + line, and the V- line need to be formed in the upper layer provided on the layer where the gate wiring is formed. That is, three terminals of the bit contact region 161, the V-contact region 162, and the V + contact region 163 are sufficient as the contact region formed in the layer where the gate wiring is provided.

Here, when cells are coupled as shown in FIG. 22, the bit lines, V + lines, and V- lines formed in the upper layer are arranged without intersecting as shown in FIG. Therefore, the bit line 164, the V + line 165, and the V- line 166 can be formed in the same layer. Therefore, according to the tenth embodiment, the wiring of all the SRAM cells can be formed by the gate wiring layer and one upper layer.

As described above, according to the tenth embodiment of the present invention, a wiring connecting a source / drain electrode of a certain MOSFET to another source / drain electrode, a source / drain electrode of a certain MOSFET, and another Can be formed in a layer where the gate wiring is formed. Therefore, the number of steps can be significantly reduced. Conventionally, a certain MOSFE
In order to connect the source / drain electrode of T to another source / drain electrode, it was necessary to form a large source / drain region. On the other hand, according to the tenth embodiment, the size of the source / drain region can be made smaller than that of the related art. Therefore, an increase in diffusion capacitance can be prevented, and transistor characteristics can be improved.

Next, an eleventh embodiment of the present invention will be described. In the ninth embodiment, the source / drain electrodes are formed after the gate electrode is formed in advance, but in the present embodiment, first, a dummy gate wiring is formed instead of the gate electrode. Also, according to the present embodiment,
MOSFET having a structure using a part of the side surface of the gate electrode as a channel (hereinafter referred to as a half concave structure)
Can be manufactured. Hereinafter, description will be made with reference to FIGS.

FIGS. 24 to 27 are sectional views schematically showing manufacturing steps of a semiconductor device according to the eleventh embodiment of the present invention.

First, as shown in FIG. 24A, a thermal oxide film 102 having a thickness of about 4 nm is formed on one surface of a silicon substrate 101. The thermal oxide film 102 is formed on the substrate 10
1 to protect the surface and to be used as an etching stopper in a later step. afterwards,
A silicon nitride film 103 having a thickness of about 150 nm is formed on the thermal oxide film 102 by a CVD method.

Next, as shown in FIG. 24B, a trench 104 is formed by etching the silicon nitride film 103, the thermal oxide film 102, and the silicon substrate 101 by using lithography and RIE techniques. The groove 104 is used later for element isolation. In the present embodiment, the groove 1
04 is formed in a forward tapered shape. Further, a thermal oxide film 105 is formed on the exposed surface of the silicon substrate 101.

Thereafter, as shown in FIG. 24C, a silicon oxide film 106 is formed on the surface of the substrate 101 on which the groove 104 is formed by a CVD method, and the groove 104 is filled with silicon oxide. Further, the silicon oxide film 106 is
Polishing by MP method. This polishing is performed on the silicon nitride film 1.
Stop when 03 is exposed. The element isolation region is formed as described above.

Next, on the silicon nitride film 103 and the silicon oxide film 106, a silicon oxide film 108 having a pattern shown in FIG.
The reason for using silicon oxide here is that silicon oxide has a sufficient etching selectivity with respect to the silicon nitride film 103. However, part of the silicon oxide film 106 is also removed during this etching. When the removal amount of the silicon oxide film 106 becomes excessive, a SiN film may be provided between the silicon oxide film 108 and the silicon oxide film 106 as an etching stopper.

Then, as shown in FIG. 24E, the silicon nitride film 103 is anisotropically etched by RIE or the like using the silicon oxide films 106 and 108 as a mask and the silicon oxide film 102 as an etching stopper. .
At this time, the silicon nitride film 10 is located between the silicon oxide film 106 and the substrate 101 in the forward tapered groove 104.
3 remain without being etched. That is, the source
SiN sidewalls can be formed in a self-aligned manner around the region where the drain electrode is formed. Therefore, according to the present embodiment, there is no need to separately form a SiN side wall. When the side wall is formed sufficiently thick and the STI region is narrowed, the groove 104 may be formed as shown in FIG. That is, the silicon nitride film 103 may be taper-etched, and the substrate 101 may be etched in a rectangular shape.

Thereafter, the exposed portions of the silicon oxide film 102 are removed by wet etching using diluted hydrofluoric acid or the like. Further, as shown in FIG. 25 (g), silicon is selectively epitaxially grown on the exposed surface of the substrate 101,
A crystalline silicon film 130 is formed. When the outer peripheral portion of the exposed surface of the substrate 101 is covered with a silicon oxide film, abnormal growth such as facet growth occurs during the epitaxial growth. In contrast, in the present embodiment, since the outer peripheral portion of the exposed surface of the substrate 101 is covered with the SiN film, the crystalline silicon film 130 must be formed to have a uniform and sufficient thickness without causing abnormal growth. Can be. Subsequently, a thermal oxide film 131 is formed on the surface of the crystalline silicon film 130. The thermal oxide film 131 is used as an etching stopper in a later step.

Next, conductive impurities are implanted into the crystalline silicon film 130 by ion implantation or the like, and activation is performed. Note that, instead of the above-described steps, a mixture of a conductive impurity and silicon may be epitaxially grown.
When the concave structure is not required, the epitaxial growth is not performed. Further, when the extension is formed, after forming the extension by ion implantation, a side wall made of silicon oxide or the like is formed, and then a diffusion region having a high impurity concentration is formed. What is necessary is just to remove by wet etching etc. By forming this side wall using BPSG or the like having an etching rate higher than that of a normal silicon oxide, the side wall can be removed by a short etching process. Therefore, it is not necessary to remove the silicon oxide film 106 excessively. Further, formation of a diffusion region with a high impurity concentration requires a higher activation temperature than formation of an extension. Therefore, after forming the side wall, a diffusion region having a high impurity concentration may be formed first, and after removing the side wall, ion implantation and activation for forming an extension which is a shallower junction region may be performed.
Thereby, a shallower junction can be formed.

Next, as shown in FIG.
A polysilicon film 111 is formed by a method. Further, as shown in FIG.
The polysilicon film 111 is flattened using an etch back technique. This planarization is performed until the silicon oxide film 108 is exposed. As described above, the entire region except the region where the gate wiring is to be formed is covered with the polysilicon film 111. By using the polysilicon film 111 as a mask, it is possible to form a groove corresponding to a region where a gate wiring is to be formed.

Thereafter, as shown in FIG. 25J, the silicon oxide film 108 is removed by RIE or the like using the polysilicon film 111 as a mask.

Further, as shown in FIG. 25K, the silicon oxide film 106 is etched by RIE or the like using the silicon nitride film 103 and the polysilicon film 111 as a mask. This etching stops until the channel edge is not exposed.

Next, as shown in FIG. 25 (l), the exposed portion of the silicon nitride film 103 is anisotropically etched by RIE or the like using the polysilicon film 111 and the thermal oxide film 102 as a mask. At this time, the silicon nitride film 10
If the etching selectivity between the polysilicon film 3 and the polysilicon film 111 is insufficient, the polysilicon film
A thermal oxide film is formed on the surface of the substrate 11. Thereby, a sufficient etching selectivity can be obtained.

Next, as shown in FIG. 26 (m), the thermal oxide film 102 is removed using diluted hydrofluoric acid or the like, and a gate insulating film 132 is formed. The gate insulating film 132 may be formed by thermal oxidation or may be formed by a CVD method or the like. Thereafter, a film 1 made of a material having a low resistivity, for example, W
13 is formed. Here, when a barrier layer is required, after forming the barrier layer on the gate insulating film 132,
A W film 113 is formed. Before forming the gate insulating film 132, a thin thermal oxide film is formed and removed.
Alternatively, hydrogen annealing or the like may be performed. Thus, the edge of the crystalline silicon film 130 can be rounded.
Further, ion implantation into the channel region is performed by
By performing the step immediately before forming the second region, a channel region having a high impurity concentration can be formed only in a desired portion of the element region. Therefore, the junction capacitance of the source / drain diffusion layers can be reduced.

Further, as shown in FIG. 26 (n), before forming the gate insulating film 132, a channel region 133 having a high impurity concentration is formed by ion implantation or the like. A film 134 made of Si-Ge may be formed. Thus, a MOSFET having a retrograde channel structure can be obtained. Here, at the time of the selective epitaxial growth, there is a possibility that Si or Si—Ge may be epitaxially grown on the polysilicon film 111, but this is a problem because it is removed simultaneously when the polysilicon film 111 is etched later. Does not. FIG. 26 (n) is an enlarged view of the groove.

Next, as shown in FIG. 26 (o), the W film 1
13 is flattened using a CMP method or a resist etch-back technique. This planarization is performed by the polysilicon film 111.
Repeat until is exposed.

Thereafter, as shown in FIG. 26 (p), the silicon oxide film 106, the W film 113, and the gate insulating film 13
Using polysilicon 2 as a mask, the polysilicon film 111 is etched by RIE or the like. This etching need not be anisotropic etching, but may be etching using radical atoms. Therefore, there is no need to damage the gate edge. Here, when repairing the damaged gate edge portion, the oxidation treatment is performed in an atmosphere containing hydrogen, water, and nitrogen,
Crystallized silicon film 130 without oxidizing W film 113
Can be repaired.

Next, as shown in FIG.
By forming a film and performing RIE on it, the source
An SiN side wall 110 for preventing an electrical short circuit between the drain electrode and the gate electrode is formed. Subsequently, the thermal oxide film 131 is removed using dilute hydrofluoric acid or by dry etching. Instead of forming the side wall 110 from SiN, the side wall 110 may be formed from silicon oxide having a lower dielectric constant. By using such a material, the parasitic capacitance between the source / drain electrode and the gate electrode can be reduced. Although the crystalline silicon film 130 is doped with conductive impurities in the step shown in FIG.
When the gate electrode is made of a high melting point metal such as W, FIG.
By performing ion implantation after the steps shown in FIGS. 6 (p) and (q) and further performing annealing for activation,
The heat treatment described with reference to FIGS. 26 (m) and (n) can be omitted. Therefore, a shallower junction can be formed.

Thereafter, as shown in FIG.
A film 135 is formed and planarized by using a CMP method or a resist etch-back technique. This planarization is performed until the silicon oxide film 106 is exposed. Thus, source / drain electrodes are formed. If a barrier layer is required, the Al film 135 is formed after forming the barrier layer.
May be formed.

As described above, a half concave type MOSFET can be obtained.

According to the present embodiment, when a plurality of half concave type MOSFETs are simultaneously formed,
Electrical connection between a source electrode of a certain MOSFET and a drain electrode of another MOSFET or electrical connection between a source electrode or a drain electrode of a certain MOSFET and a gate electrode of another MOSFET can be performed. The method will be described below.

First, after completing the step shown in FIG. 26 (q), a resist film 136 is formed as shown in FIG. 27 (s), and an opening is formed in the resist film 136 by using lithography. Next, a part of the silicon nitride film 103 and the side wall 110 made of SiN are removed by etching using radical atoms or the like. Subsequently, the silicon oxide film 106 is etched using RIE technology or the like so as to be almost the same height as the crystalline silicon film 130. Note that this etching amount is related to the thickness of a wiring to be formed later. Therefore, when the necessity of reducing the resistance of the wiring is low, the etching amount may be set smaller than that described above.

Next, the resist film 136 is removed. Further, by performing the steps shown in FIGS. 27 (q) and (r), the semiconductor device shown in FIG. 27 (t) can be obtained.

As described above, according to the present embodiment,
Forming a plurality of half concave type MOSFETs;
Electrical connection between the source electrode of a certain MOSFET and the drain electrode of another MOSFET, or electrical connection between the source or drain electrode of a certain MOSFET and the gate electrode of another MOSFET can be performed simultaneously.

According to the present embodiment, it is possible to form a silicon nitride film only on a gate electrode. Hereinafter, the method and the effect obtained by the method will be described.

First, after completing the step shown in FIG. 26 (o), as shown in FIG. 27 (u), the W film 113 is etched back by performing RIE or SH processing. Next, as shown in FIG. 27 (v), a silicon nitride film 137 is formed.
Is formed and planarized using a CMP method or a resist etch-back technique. This flattening is performed by the polysilicon film 1.
Repeat until 11 is exposed.

Thereafter, by performing the steps shown in FIGS. 26 (p) to (r), the semiconductor device shown in FIG. 27 (w) can be obtained. In the semiconductor device in which the silicon nitride film 137 is formed only on the gate electrode as described above, an electric short circuit between the gate electrode and the source / drain electrodes is less likely to occur. The reason will be described with reference to FIG.

In FIG. 27 (x), an insulating film 13 such as a silicon oxide film is formed on the MOSFET shown in FIG.
8 are formed. In order to form an opening in the insulating film 138 for connection with a source / drain electrode, it is necessary to form a resist film (not shown) on the insulating film 138 and use a lithography technique. here,
For example, if a misalignment occurs, the gate electrode 11
The insulating film 138 located above 3 may also be opened. In such a case, when the opening of the insulating film 138 is buried with a metal 139 such as Al, the gate electrode 113 and the source
An electric short circuit occurs with the drain electrode 135. On the other hand, as shown in FIG.
When the silicon nitride film 137 is formed only on the gate electrode 113, the gate electrode 113 is covered with the silicon nitride film 137.
No electrical short circuit occurs between the third and source / drain electrodes 135. When the gate insulating film 132 is a silicon oxide film, a part of the opening is etched when the opening is formed. However, since the upper surface of the gate electrode is located below the upper surfaces of the source / drain electrodes, the opening can be formed without excessively etching the gate insulating film 132.

Next, a twelfth embodiment of the present invention will be described. In the ninth embodiment, the resistivity of the source / drain / gate electrode is reduced by employing an elevated source / drain structure and using silicide. However, if the resistivity can be reduced without using silicide, it is not always necessary to adopt the elevated source / drain structure. In this embodiment, the gate electrode has a polymetal structure and the source / drain electrode is made of W, Al, or the like, without employing the elevated source / drain structure.

FIGS. 28 and 29 schematically show the steps of manufacturing a semiconductor device according to the twelfth embodiment of the present invention. 28 and 29, (a) to (h) are cross-sectional views.

First, the ninth embodiment shown in FIGS.
Steps similar to those described with reference to (f) and FIGS. 14 (g) to (i) are performed. However, the polysilicon film 103
The doping and activation of conductive impurities into
This is performed after the step shown in FIG.

Next, as shown in FIG.
Form one. If a barrier layer is required, the W film 111 is formed after forming the barrier layer. Then, FIG.
As shown in (b), the W film 111 is formed by using a CMP technique or the like.
Is flattened. As described above, all the regions except the region where the gate wiring is formed are covered with the W film 111.

Thereafter, as shown in FIG. 28C, a part of the side wall 110 and the SiN film 108 are formed by radical etching or RIE using the W film 111 as a mask.
Is removed. At this time, the thermal oxide film 107 functions as an etching stopper.

Further, as shown in FIG. 28D, the silicon oxide film 106 is removed by RIE or the like, and the polysilicon film 103 is etched back. Here, the polysilicon film 103 is not completely removed because the gate electrode has a stacked structure of polysilicon and metal. Next, as shown in FIG. 28E, the W film 111 and the side walls 11 are formed.
0, the silicon oxide film 106 and the like are etched using the polysilicon film 103 as a mask. The silicon oxide film 106 is removed so that the channel edge is not exposed, that is, the side surface of the thermal oxide film 102 is not exposed.

Next, as shown in FIG. 28F, an Al film 113 is formed, and planarization is performed by using a CMP method or the like. Here, when a barrier layer is required, the Al film 113 may be formed after forming the barrier layer. This flattening is performed until the silicon oxide film 106 is exposed. As described above, it is possible to obtain a MOSFET in which the gate electrode has a polymetal structure in which polysilicon and Al are stacked, and the source / drain electrodes are composed of W.

According to the present embodiment, similarly to the tenth embodiment, when forming a plurality of MOSFETs, an electrical connection between a source electrode of a certain MOSFET and a drain electrode of another MOSFET or a certain MOSFET is formed. And the gate electrode of another MOSFET can be simultaneously connected.
Hereinafter, description will be made with reference to FIGS.

First, the structure shown in FIG. 28D is obtained by the method described above. Next, as shown in FIG. 29G, a resist film 120 is formed, and an opening is formed in the resist film 120 by using a lithography technique. Then, the silicon oxide film 10
The W film 111 is etched using 6 as an etching stopper. Subsequently, the side wall 110 made of SiN
Is etched back until the height is substantially the same as the polysilicon film 103.

Next, after removing the resist film 120, the steps described with reference to FIGS. 28E and 28F are performed. As a result, as shown in FIG.
The formation of the OSFET and the electrical connection between the source electrode or the drain electrode of one MOSFET and the gate electrode of another MOSFET, for example, can be performed simultaneously.

Next, a thirteenth embodiment of the present invention will be described. In the ninth and twelfth embodiments, the CM
Each of the planarization processes using the P method was performed three times. On the other hand, according to the present embodiment, the use of the resist recess technique makes it possible to perform the planarization step twice. This will be described below with reference to FIG.

In the twelfth embodiment, FIG.
In the steps shown in (a) and (b), the W film 111 was formed so as to cover all regions other than the gate wiring region. In the twelfth embodiment, the SiN film 108 is etched using the W film 111 as a mask. On the other hand, according to this embodiment, instead of the W film 111, a resist film 111A is used as shown in FIG.

That is, first, the ninth embodiment shown in FIG.
Steps similar to those described with reference to (a) to (f) and FIGS. 14 (g) to (i) are performed. However, the doping and activation of the conductive impurity into the polysilicon film 103 are performed as follows.
This is performed after the step shown in FIG.

Next, as shown in FIG. 30A, a resist film 111A is formed. Thereafter, a resist recess is performed by appropriately controlling the amount of exposure, and the SiN film 108 is exposed. The resist film 11 having the opening formed as described above
By using 1A as a mask, the SiN film 108
Can be selectively etched.

Further, in the twelfth embodiment, FIG.
The steps described with respect to (d) and (e) are performed. Thereafter, the resist film 111A is removed, and the steps described with reference to FIG. 28F in the twelfth embodiment are performed, so that the source, drain, and gate electrodes are formed of Al as shown in FIG. Obtained MOSFET.

In this embodiment, unlike the ninth, eleventh, and twelfth embodiments, the mask used when etching the SiN film 108 is formed of a resist. Therefore, in the present embodiment, it is not necessary to perform a planarization step to form an opening in the mask. Therefore, according to the present embodiment, the number of CMP steps can be reduced, and the manufacturing cost can be reduced.

Next, a process common to the ninth to thirteenth embodiments will be described with reference to FIG. FIGS. 31A and 31B show the ninth to ninth embodiments of the present invention.
FIG. 35 is a drawing schematically illustrating a method for manufacturing a semiconductor device according to a thirteenth embodiment.

According to the ninth to thirteenth embodiments, the groove for burying the source / drain electrodes and the groove for burying the gate electrode are formed in separate steps. That is, first, FIG.
As shown in (a), two types of grooves having different depths are formed on one main surface of the substrate. Note that in FIG. 31 (a), R ₁ represents a region where the source and drain electrodes are formed, R ₂ represents a region where the gate wiring is formed, R ₃ denotes an element isolation region.

[0229] Next, as shown in FIG. 31 (b), each of the grooves, filled with the mask material M _1. Mask material M
₁ are chosen so that region R ₂ can be selectively removed relative to the material M _1. Further, by carrying out the planarization process to expose the region R _2.

[0230] Then, using a thin film made of the material M ₁ as a mask to form a groove in a region R _2. Thus formed was a groove, the embedded in the material used to form the gate wiring (not shown), further, by performing a planarization process to expose an isolation region R _3.

Here, when the mask material M ₁ is an electrode material used for the source / drain electrodes, the MOSFET is obtained by ending the above steps. Further, if the mask material M ₁ is a material to be removed, after removing the mask material M _1, thereby burying a groove formed in the electrode material, still performing the planarization process. As described above, a MOSFET is obtained.

As described above, according to the method of manufacturing the semiconductor device according to the ninth to thirteenth embodiments of the present invention, the gate wiring, the source electrode, and the drain electrode can be formed in a self-aligned manner. In the embodiment of the ninth and twelfth respectively using polysilicon and W in the material M _1, and a source-drain electrode in these materials M _1. Further, in Embodiment 11 and 13, using polysilicon and resist the respective material M _1, to form the source and drain electrodes after the removal of these materials M _1. In the thirteenth embodiment, after forming the gate insulating film, the gate wiring, the source electrode, and the drain electrode were simultaneously buried.

Further, according to the ninth to thirteenth embodiments described above, prior to the formation of the source / drain electrodes, the gate structure and the element isolation insulating film are so formed that their upper surfaces are equal in height. And a groove crossing the gate structure and being divided into the gate structure. Since the source / drain electrodes are formed in the grooves as in the first to eighth embodiments, according to the ninth to thirteenth embodiments, in addition to the effects described individually, 8th
The same effect as that described in the embodiment can be obtained. In the ninth to thirteenth embodiments, components denoted by the same reference numerals are substantially the same unless otherwise specified.

In the first to thirteenth embodiments, the element isolation region is formed such that its upper surface is higher than the bottom surface of the region where the source / drain electrodes are formed. Hereinafter, effects produced by such a configuration will be described in more detail with reference to FIGS. 32 and 33.

FIG. 32A is a cross sectional view schematically showing a conventional method for manufacturing a MOSFET. FIG. 32
(B) is an MO according to the first to thirteenth embodiments of the present invention.
It is sectional drawing which shows the manufacturing method of SFET schematically. FIGS. 32A and 32B show an intermediate step for manufacturing a MOSFET having an elevated source / drain structure.

FIGS. 33A and 33B are graphs showing the relationship between the width of the element isolation region and the short yield of the MOSFET shown in FIGS. 32A and 32B, respectively. In the figure, the horizontal axis represents the width d _{1 of the} element isolation region 106.
Alternatively, d ₂ is shown, and the vertical axis shows the short yield.

As shown in FIG. 32A, conventionally, the element isolation region 106 is formed so as to be completely buried in the surface region of the substrate 101. Therefore, the crystalline silicon film 13 is formed on the substrate 101 by selective epitaxial growth.
When 0 was formed, the crystalline silicon film 130 was also grown in the lateral direction. For example, the thickness t of the crystalline silicon film 130
_{If 1 is set} to 50 nm, the crystalline silicon film 130 will also grow about 50 nm in the lateral direction. Therefore, FIG.
(A), the began to decrease the yield by narrowing than 0.2μm width d ₁ of the element isolation region 106, approximately 0% of the yield in the case where the width d ₁ and 0.1μm or less Will be. That is, a short circuit occurs between almost all adjacent MOSFETs. Further, assuming that the thickness t ₁ is 100 nm in the conventional method, the width d ₁ needs to be at least about 0.3 μm.

On the other hand, as shown in FIG.
When the element isolation region 106 is formed so that its upper surface is higher than the substrate surface, no short circuit occurs between adjacent MOSFETs. That is, as shown in FIG. 33B, even if the width d ₂ of the element isolation region 106 is reduced to 0.1 μm, a high yield can be obtained without depending on the thickness t ₂ of the crystalline silicon film 130. You can do it.

In the future, in semiconductor devices, wiring will be 0.1 μm.
It is conceivable that it is formed in a width of about m. In such a case, it is necessary to reduce the width d ₁ or d ₂ to about 0.15 μm. When the source electrode, the drain electrode and the gate wiring are made of cobalt silicide,
It is said that their thickness needs to be 50 nm or more in order to realize low resistance.

Here, when forming a silicide film having a thickness of 50 nm, a crystalline silicon film having a thickness of about 50 nm is consumed. Therefore, in order to realize a shallow junction of about 30 nm and to suppress junction leakage due to silicide in the source and drain portions, the thickness t ₁ or t ₂ needs to be 50 nm or more.

However, when the width d _{1 is set} to 0.15 μm, a high yield cannot be obtained if the crystalline silicon film 130 having a thickness of 50 nm is formed by using the conventional technique. In order to obtain a high yield, the width d ₁ must be 0.2 μm.
m or more. This means that the degree of integration cannot be higher than that achieved in a semiconductor device having a wiring width of about 0.15 μm. Further, when the miniaturization is further advanced, further lowering the resistance is required, so that it is necessary to increase the thickness of the silicide film. In this case, according to the conventional method, it is necessary to further increase the width d ₁ . As described above, according to the conventional method, the degree of integration is reduced as the miniaturization is advanced.

On the other hand, according to the first to thirteenth embodiments of the present invention, the yield depends on the width d of the element isolation region 106.
₂ and the thickness t ₂ of the crystalline silicon film 130.
Therefore, it is possible to improve the degree of integration without lowering the yield.

Further, when the conventional method is used, when the source electrode and the drain electrode are formed in a self-aligned manner, they have to be constituted by silicide. On the other hand, according to the first to thirteenth embodiments of the present invention, low-resistance metals such as W, Al, and Cu having lower resistivity than silicide can be used. When silicide is used, the crystalline silicon film 1 is used to prevent junction leakage.
It is necessary to form 30 thick. On the other hand, when the low-resistance metal is used, the crystalline silicon film 130 does not need to be formed as thick as when silicide is used.

Next, a fourteenth embodiment of the present invention will be described. In the following, a method of manufacturing an NMOS will be described. However, by inverting the conductivity type of the impurity, a PMOS can also be manufactured by the same method.

FIGS. 34 to 36 schematically show steps of manufacturing a semiconductor device according to the fourteenth embodiment of the present invention. 34A to 36, (a) to (k) are cross-sectional views.

First, as shown in FIG.
01 in the surface region of one of the main surfaces.
To form Note that the substrate 201 is a p-type silicon substrate or a silicon substrate on which a p-type well region is formed. The element isolation 206 does not necessarily have to be a trench type, and may be a LOCOS method. next,
An oxide film 202 having a thickness of about 8 nm is formed on a substrate 201. Further, a thin film 203 made of a material such as Si ₃ N ₄ is formed on the oxide film 202.

Next, as shown in FIG.
03 is patterned to form a dummy gate wiring.
Further, the exposed portion of the oxide film 202 is removed using a liquid containing diluted hydrofluoric acid or the like.

Thereafter, as shown in FIG. 34C, selective epitaxial growth of silicon is performed using the exposed portion of the substrate 201 as a seed. Thereby, a thickness of 20 nm
A crystalline silicon film 204 'of a degree is formed. Next, FIG.
As shown in FIG. 4D, a SiO ₂ film having a thickness of about 10 nm is formed on the crystalline silicon film 204 ′ and the dummy gate wiring 203.
An insulating film 205 made of, for example, is formed. Further, the acceleration energy as 20 KeV, to form the impurity diffusion region by implanting As ⁺ ions at a concentration of about 1 × 10 ¹⁴ cm ^-1 in crystalline silicon film 204 '.

Next, as shown in FIG. 35 (e), an S film is formed on the side surface of the dummy gate wiring 203 via an insulating film 205.
A gate side wall 207 made of an insulator such as i ₃ N ₄ is formed. Then, using the gate sidewall 207 as a mask,
As ⁺ ions or the like are ion-implanted into the crystalline silicon film 204 ′. Thus, the extension 204 is formed below the gate side wall 207, and further, the extension 2 is formed.
The n ⁺ diffusion region 208 is formed adjacent to the N ⁺ . In addition,
The extension 204 is formed shallower than the n ⁺ diffusion region 208. Also, extension 204
And n ⁺ diffusion region 208 constitute a source / drain diffusion layer.

In this step, the insulating film 205 is used not only as an etching stopper for the etching performed when the gate sidewall 207 is formed, but also in the n ⁺ diffusion region 20.
8 also plays a role in preventing the occurrence of channeling at the time of ion implantation for forming 8. The effective depth of n ⁺ diffusion region 208 formed as described above, ie, oxide film 2
The depth from 02 becomes shallower by the thickness of the extension 204 than the actual depth. Where SALICID
When a silicide film is formed on the source / drain regions by using the E method, after performing the above steps, the exposed portion of the insulating film 205 is removed, and a metal film (not shown) made of a metal such as Ti or Co is used. ) Is formed. Further, this metal and Si constituting n ⁺ diffusion region 208 are reacted by RTA or the like, and the unreacted metal is removed with a mixed solution containing sulfuric acid and hydrogen peroxide or the like. As described above, a silicide film can be formed.

Next, as shown in FIG.
01 on the entire surface on which the n ⁺ diffusion region 208 is formed.
An insulating film 209 made of O ₂ or the like is formed. Further, FIG.
As shown in FIG. 5 (g), the surface is smoothed using a CMP method or the like. This smoothing is performed so that the gate side wall 207 is not exposed and the upper surface of the dummy gate wiring 203 is exposed.

Thereafter, as shown in FIG. 35H, the dummy gate wiring 203 is removed. As in this example, the dummy gate wiring 203 is made of Si ₃ N ₄ and the insulating film 20 is formed.
When 9 is made of SiO ₂ , only the dummy gate wiring 203 can be selectively removed by using hot phosphoric acid. In this example, the dummy gate wiring 203 is made of Si ₃ N ₄ , and the insulating film 205 is made of Si ₃ N _4.
O ₂ and the insulating film 209 was made of SiO ₂ ,
In the state shown in FIG.
Other materials may be used as long as only 3 can be selectively removed. However, when the dummy gate wiring 203 is removed, it is desirable that only the dummy gate wiring can be selectively etched without damaging the channel portion. Here, ion implantation may be performed in order to adjust the threshold value of the transistor. In this case, since ion implantation can be selectively performed only in the channel portion, the junction capacitance of the source / drain diffusion layers does not increase.

Next, as shown in FIG. 36 (i), the exposed portions of the insulating film 205 and the oxide film 202 are removed using a solution containing diluted hydrofluoric acid. Further, as shown in FIG. 36J, a gate insulating film 210, a reaction prevention layer 211, and a gate electrode material film 212 are sequentially stacked.

The gate insulating film 210 is made of, for example, Ta ₂ O ₅
It is preferably a high-dielectric compound such as BST or BST. Further, the gate insulating film 210 is preferably formed by a CVD method. By using the CVD method,
The gate insulating film 210 can be formed in a shape corresponding to the shape of the groove.

The reaction preventing layer 211 is formed of the gate insulating film 210
To prevent a reaction between the gate electrode material film 212 and the gate electrode material film 212. Therefore, when the gate insulating film 210 and the gate electrode material film 212 hardly cause a thermal reaction or the gate electrode material hardly diffuses into the gate insulating film 210, the reaction prevention layer 211 is not necessarily provided. . The material forming the reaction prevention layer 211 should be determined according to the combination of the material forming the gate insulating film 210 and the gate electrode material. The reaction preventing layer is generally, TiN, or a metal nitride such TaN and WN _x, composed of ternary compounds containing a metal, nitrogen and silicon.

The gate electrode material film 212 is preferably made of a material mainly containing a metal such as W or Al.
Further, the gate electrode material film 212 is preferably formed by a CVD method. When the CVD method is used, the gate electrode material film 212 can be formed in a good shape. In addition, as long as the gate electrode material film 212 can be formed in a favorable shape, a PVD method may be used.

The gate electrode material film 212 can be made of Al by using the following method. That is, first, the trench is filled with amorphous silicon by using a low pressure CVD method, and Al and Ti are further deposited thereon. Next, this is heated to a temperature of about 450 ° C. Thereby, Si in the groove part diffuses into the Al layer.
Diffused Si reacts with Ti, forms a TiSi _x. TiSi _x is Si is stable compounds are fixed in Ti, the result, Si in the groove is replaced by Al.

After performing the step shown in FIG. 36 (j), as shown in FIG. 36 (k), planarization is performed by using a CMP method or the like. This planarization is performed so that the insulating film 209 is exposed. Thus, the gate electrode 212 is formed in the groove.

According to the fourteenth embodiment of the present invention described above, since the overlap between the source / drain region and the gate electrode can be made very small, the parasitic capacitance between the gate electrode and the source / drain region can be reduced. Can be reduced. Further, according to the fourteenth embodiment, the source / drain regions are formed with a sufficient thickness, and the effective depth is controlled to be small. Therefore, even when the size is reduced, it is possible to prevent punch-through from occurring.

Next, a fifteenth embodiment of the present invention will be described. In the present embodiment, a CMOS is manufactured,
A method of doping conductive impurities for forming an extension is different from that of the fourteenth embodiment.

FIG. 37 schematically shows a process of manufacturing a semiconductor device according to the fifteenth embodiment of the present invention. Note that FIG.
1A to 1D are cross-sectional views.

First, as shown in FIG. 37A, an element isolation 206, a p-type well region 221, and an n-type well region 222 are formed in a surface region of a silicon substrate 201.
Next, an oxide film 202 and a thin film 203 made of a material such as Si ₃ N ₄ are sequentially formed on the surface of the substrate 201 on which the element isolation 206 and the like are formed.

Further, as shown in FIG. 37B, the thin film 203 located on the p-type well region 221 is patterned to form a dummy gate wiring 203A. Thereafter, as shown in FIG. 37C, the exposed portion of the oxide film 202 is removed using a solution containing diluted hydrofluoric acid or the like. Next, using the exposed surface of the substrate 201 as a seed, selective epitaxial growth of silicon is performed to a thickness of 20 μm.
A crystalline silicon film 204A of about nm is formed. In addition,
This selective epitaxial growth is performed in an atmosphere containing gases such as AsH ₃ and PH _3, thereby doping the crystalline silicon film 204A with n-type impurities. Thereafter, a silicon oxide film 205 having a thickness of about 10 nm is formed by oxidizing the surface of the crystalline silicon film 204A or by using a CVD method or the like.

Next, as shown in FIG. 37D, the thin film 203 located on the n-type well region 222 is patterned to form a dummy gate wiring 203B. afterwards,
By the above-described method, the exposed portion of the oxide film 202 is removed using a solution containing diluted hydrofluoric acid or the like. Next, selective epitaxial growth of silicon is performed using the exposed surface of the substrate 201 as a seed to form a crystalline silicon film 204B having a thickness of about 20 nm. By performing this selective epitaxial growth in an atmosphere containing a gas such as B ₂ H ₆ , p
Doping with a type impurity. Thereafter, a silicon oxide film (not shown) having a thickness of about 10 nm is formed by oxidizing the surface of the crystalline silicon film 204B or by using a CVD method or the like.

Next, in the fourteenth embodiment, FIG.
The MISFET is obtained by performing the steps described with reference to (f) to (h) and FIGS. 36 (i) to (k).

According to the fifteenth embodiment described above,
The effects described in the fourteenth embodiment can be obtained. When the ion implantation method is used to form the extension, PEP (Photo Engraving) is performed a total of three times in patterning and doping of the gate electrode.
Process) is required. On the other hand, according to the present embodiment, PEP can be reduced to twice. Further, when the ion implantation method is used, the impurity concentration decreases from the substrate surface to the deep portion, but according to the present embodiment, no concentration gradient of the conductive impurity occurs. for that reason,
An extension in which conductive impurities are contained uniformly and at a high concentration can be formed. Therefore, the fifteenth
According to the embodiment, the parasitic resistance can be further reduced.

[0267]

As described above, according to the present invention, the gate structure and the element isolation insulating film are formed prior to the formation of the source / drain electrodes. The formation of the gate structure and the element isolation insulating film was performed such that the height of the upper surface of the gate structure was equal to or lower than the height of the upper surface of the element isolation insulating film, and was intersected with the gate structure and divided into gate structures. This is performed so that a groove is formed. Further, the source / drain electrodes are formed in a self-aligned manner in the groove. Therefore, according to the present invention, the insulating state between adjacent transistors can be favorably maintained, and a high-density fine transistor can be realized.

Further, according to the present invention, the overlap between the source / drain region and the gate electrode can be made very small, so that the parasitic capacitance between the gate electrode and the source / drain region can be reduced. Further, according to the present invention, the source / drain regions are formed with a sufficient thickness,
In addition, the effective depth can be controlled to be shallow. Therefore, according to the present invention, it is possible to prevent the occurrence of punch-through even when the size is reduced.

[Brief description of the drawings]

FIG. 1 is a perspective view schematically showing a manufacturing process according to a first embodiment of the present invention.

FIG. 2 is a perspective view schematically showing a manufacturing process according to the first embodiment of the present invention.

FIG. 3 is a view schematically showing a manufacturing process according to the first embodiment of the present invention.

FIG. 4 is a sectional view schematically showing a manufacturing process according to the first embodiment of the present invention.

FIG. 5 is a perspective view showing the semiconductor device according to the first embodiment of the present invention.

FIG. 6 is a sectional view schematically showing a manufacturing process according to a second embodiment of the present invention.

FIG. 7 is a perspective view schematically showing a manufacturing process according to a third embodiment of the present invention.

FIG. 8 is a perspective view schematically showing a manufacturing process according to a fourth embodiment of the present invention.

FIG. 9 is a perspective view schematically showing a manufacturing process according to a fourth embodiment of the present invention.

FIG. 10 is a perspective view schematically showing a manufacturing process according to a fifth embodiment of the present invention.

FIG. 11 is a view schematically showing a manufacturing process according to a seventh embodiment of the present invention.

FIG. 12 is a perspective view schematically showing a manufacturing process according to an eighth embodiment of the present invention.

FIG. 13 is a sectional view schematically showing a manufacturing process of a semiconductor device according to a ninth embodiment of the present invention.

FIG. 14 is a sectional view schematically showing a manufacturing process of a semiconductor device according to a ninth embodiment of the present invention.

FIG. 15 is a view schematically showing a manufacturing process of a semiconductor device according to a ninth embodiment of the present invention.

FIG. 16 is a view schematically showing a manufacturing process of the semiconductor device according to the tenth embodiment of the present invention.

FIG. 17 is a view schematically showing a manufacturing process of the semiconductor device according to the tenth embodiment of the present invention.

FIG. 18 is a view schematically showing a manufacturing process of the semiconductor device according to the tenth embodiment of the present invention.

FIG. 19 is a plan view schematically showing a manufacturing step of the semiconductor device according to the tenth embodiment of the present invention.

FIG. 20 is a plan view schematically showing a manufacturing step of the semiconductor device according to the tenth embodiment of the present invention.

FIG. 21 is a plan view schematically showing a manufacturing step of the semiconductor device according to the tenth embodiment of the present invention.

FIG. 22 is a plan view schematically showing a manufacturing step of the semiconductor device according to the tenth embodiment of the present invention.

FIG. 23 is a plan view schematically showing a manufacturing step of the semiconductor device according to the tenth embodiment of the present invention.

FIG. 24 is a sectional view schematically showing a manufacturing step of the semiconductor device according to the eleventh embodiment of the present invention.

FIG. 25 is a sectional view schematically showing a manufacturing step of the semiconductor device according to the eleventh embodiment of the present invention.

FIG. 26 is a sectional view schematically showing a manufacturing step of the semiconductor device according to the eleventh embodiment of the present invention.

FIG. 27 is a sectional view schematically showing a manufacturing step of the semiconductor device according to the eleventh embodiment of the present invention.

FIG. 28 is a sectional view schematically showing a manufacturing step of the semiconductor device according to the twelfth embodiment of the present invention;

FIG. 29 is a cross-sectional view schematically showing a manufacturing step of the semiconductor device according to the twelfth embodiment of the present invention.

FIG. 30 is a sectional view schematically showing a manufacturing step of the semiconductor device according to the thirteenth embodiment of the present invention;

FIG. 31 is a view schematically showing a method for manufacturing a semiconductor device according to ninth to thirteenth embodiments of the present invention.

FIG. 32 is a cross-sectional view schematically showing a conventional method for manufacturing a MOSFET according to the first to thirteenth embodiments of the present invention.

FIG. 33 is a graph showing the relationship between the width of the element isolation region and the short yield of conventional MOSFETs and the first to thirteenth embodiments of the present invention.

FIG. 34 is a cross-sectional view schematically showing a manufacturing step of the semiconductor device according to the fourteenth embodiment of the present invention.

FIG. 35 is a sectional view schematically showing a manufacturing step of the semiconductor device according to the fourteenth embodiment of the present invention;

FIG. 36 is a sectional view schematically showing a manufacturing step of the semiconductor device according to the fourteenth embodiment of the present invention;

FIG. 37 is a cross-sectional view schematically showing a manufacturing step of the semiconductor device according to the fifteenth embodiment of the present invention.

FIG. 38 is a sectional view schematically showing a conventional MOSFET.

FIG. 39 is a sectional view schematically showing a manufacturing process of a conventional MOSFET having an elevated source / drain structure.

[Explanation of symbols]

11, 101, 151, 201 ... substrate 12, 16, 20, 53, 102, 105 ... oxide film 107, 109, 131, 202, 106 ... oxide film 13, 21, 108, 137 ... silicon nitride film 14, 17, 19, 23, 104, 112 ... groove 15, 152, 153 ... element region 18, 52, 103, 111 ... polysilicon film 22, 130, 204, 204A, 204B ... crystalline silicon film 22A ... lateral grouse portion 24, 51, 132, 210 gate insulating film 25 gate wiring 31 TEOS oxide film, metal material film 32 silicon nitride film, alumina film 41, 42 TEOS oxide film 110, 207 sidewall 111A, 120, 136 resist film 114 Silicide film 133 Channel region 134 Thin film 113 W film 135 Al film 13 205, 209 insulating film 139 metal 154 element isolation region 155 gate wiring pattern 156 inverter circuit 157 word line 158 junction wiring region pattern 170 flip-flop circuit 159, 160 junction wiring 161 to 163 contact Region 164 Bit line 165 V + line 166 V- line 203, 203A, 203B Dummy gate wiring 204 Extension 206 Trench isolation 208 N ⁺ diffusion region 211 Reaction prevention layer 212 Gate electrode material film 221 222: Well area

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Yasushi Akasaka 8 Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa Prefecture Inside the Toshiba Yokohama Office (72) Inventor Yoshitaka Tsunashima 8 Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa Company Toshiba Yokohama Office

Claims (10)

[Claims] A) a gate structure including one of a dummy gate electrode and a gate electrode having an insulating film on at least a bottom surface on one main surface of the substrate, and an element isolation insulating film; To form a first trench portion divided by the dummy gate electrode or the gate electrode,
One of the dummy gate electrode and the gate electrode is the first
Forming the upper surface of the gate structure to be equal to or lower than the height of the upper surface of the element isolation insulating film; and b) forming the first groove portion Forming a source electrode and a drain electrode in the semiconductor device. 2. A gate structure comprising: a first gate structure including a dummy gate wiring and a dummy gate electrode; and a second gate structure including a gate wiring having an insulating film on at least a bottom surface and the gate electrode. Wherein the dummy gate wiring and the gate wiring are formed on the element isolation insulating film, are respectively connected to the dummy gate electrode and the gate electrode, and intersect with the first groove. The method of manufacturing a semiconductor device according to claim 1. 3. A step of forming a semiconductor film on the bottom surface of the first trench by using an epitaxial growth method before the step of forming the source and drain electrodes, and a step of forming a source diffusion layer and a semiconductor layer in the semiconductor film. 2. The method according to claim 1, further comprising a step of forming each of the drain diffusion layers. 4. The step of forming the source and drain electrodes is used to form a material constituting the source and drain electrodes or the source and drain electrodes on the entire surface of one main surface of the substrate. 2. The method according to claim 1, further comprising: forming a first thin film made of a material; and removing a portion of the first thin film located outside the first groove by using a CMP method. The manufacturing method of the semiconductor device described in the above. 5. The method according to claim 1, wherein the gate structure includes one of the dummy gate electrode and the gate electrode having an insulating film on at least a bottom surface. 6. The step of forming the gate structure and the element isolation insulating film, wherein the step of forming the gate structure and the element isolation insulating film is performed on a part of the element isolation insulating film and the gate structure, and the height of the top surface is 6. The method according to claim 5, further comprising forming a dummy wiring higher than the height. 7. A step of forming a fourth thin film on the entire surface of one main surface of the substrate before the step of forming the source and drain electrodes, and polishing the fourth thin film to form the dummy wiring. 7. The method according to claim 6, further comprising: exposing an upper surface; and forming a fourth groove in the thin film by removing the dummy wiring. 8. A step of forming a dummy gate wiring on one main surface of the substrate, a step of forming a semiconductor film on an exposed surface of the one main surface of the substrate by epitaxial growth, and A method of manufacturing a semiconductor device, comprising: forming a gate side wall made of an insulator on a film and covering a side surface of the dummy gate wiring. 9. A substrate, an element isolation insulating film formed on one main surface of the substrate, a gate electrode formed on one main surface of the substrate, A gate wiring connected to a gate electrode, a source electrode and a drain electrode provided on one main surface of the substrate with the gate electrode interposed therebetween, and formed on bottom and side surfaces of the gate electrode and the wiring. A gate electrode, a gate wiring, a source electrode, and a drain electrode, wherein a height of an upper surface is equal to or lower than a height of an upper surface of the element isolation insulating film. 10. A substrate, a gate wiring formed on one main surface of the substrate, an insulating film formed between the substrate and the gate wiring, and on a side surface of the gate wiring, one of the substrates A pair of thin films disposed on both sides of the gate wiring, and a gate formed on the pair of thin films and covering the side surfaces of the gate wiring and made of an insulator. A semiconductor device comprising a side wall.