JPH1174508A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve problems which arise when a gate electrode is formed through a gate insulating film on an area from which a dummy gate pattern and a dummy insulating film are eliminated. SOLUTION: A method for manufacturing a semiconductor device is composed of a process for forming a dummy film 13 and a dummy gate pattern 14 on an area for forming a gate on a semiconductor substrate, a process for forming first a side wall insulating film 15 on the side walls of the dummy gate pattern 14, a process for forming an interlayer insulating film 18 on the semiconductor substrate around the dummy gate pattern 14 with the first side wall insulating film 15, a process for forming a groove 30 by eliminating the dummy pattern 14, a process for eliminating the dummy film 13 exposed in the groove 30 in such a way that a part of the first side wall insulating film 15 and the part of the dummy film 13 under it are left, a process for forming a gate insulating film at least in the bottom of the groove and a process for forming a gate electrode on the gate insulating film in the groove.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method for manufacturing the same.

[0002]

2. Description of the Related Art In a MOS transistor using a silicon oxide film as a gate oxide film, high reliability of the gate oxide film plays an important role in improving the performance of the transistor. However, thinning of the gate oxide film (for example, a film thickness of about 4 nm or less) may cause a problem during the process, such as doping of impurities into the gate electrode, plasma damage during processing of the gate electrode, and ion implantation into the channel region and the source / drain regions. It is expected that reliability deterioration (TDDB deterioration, increase in leak current, deterioration in breakdown voltage, etc.) of the gate oxide film due to ion damage or the like will become a problem.

As one solution to such a problem, a method of forming a gate electrode using a dummy gate pattern has been proposed (for example, Japanese Patent Application No. 8-35649).
3). This method forms a dummy gate pattern via a pad oxide film in an area where a gate is to be formed on a semiconductor substrate,
After ion implantation into the channel region and the source / drain regions, the gate insulating film and the gate electrode are buried using CMP in the trench formed by removing the dummy gate pattern and the pad oxide film. Things. According to this method, it is possible to avoid damage to the gate insulating film, such as plasma damage during processing of the gate electrode and damage during ion implantation into the channel region and the source / drain regions.

However, when such a method is used, there is a problem that it is difficult to control the dimensions of the gate electrode. That is, the Si formed around the dummy gate pattern
The O ₂ deposited film (interlayer insulating film) is a pad oxide film (thermal oxidation S
For fast etching rate as compared with iO ₂ film), it will be setback interlayer insulating film upon removal of the pad oxide film, so that the width of the groove in which a gate electrode is embedded varies greatly.

In order to prevent such a problem, it is conceivable to form a Si ₃ N ₄ film on the side wall of the dummy gate pattern. FIG. 14 shows a configuration of a transistor provided with such a sidewall Si ₃ N ₄ film. 14, reference numeral 101 denotes a gate electrode, 102 denotes a gate insulating film, 103 denotes a source / drain diffusion layer, 104 denotes a side wall insulating film, and 105 denotes a pad oxide film.

However, as described above, the side wall Si ₃ N ₄
Even if the film 104 is provided, the oxide film 105 under the side wall Si ₃ N ₄ film 104 recedes when the pad oxide film under the dummy gate pattern is peeled off, and a depression 106 is formed at the lower end of the gate electrode. The problem of formation occurs. Therefore, the source / drain region 103 and the gate electrode 10
The breakdown voltage between the gate electrode 101 and the gate insulating film 102 at the lower end of the gate electrode 101 changes.

As a result, the characteristics of the transistor are degraded (eg, the channel current is reduced and the interface state is increased) and the reliability is reduced (the insulating property is reduced due to electric field concentration at the lower end of the gate electrode and deterioration of the burying property of the gate insulating film). Etc.). In addition, since the recess 106 is formed at the lower end of the gate electrode, the groove width at the bottom of the groove in which the gate electrode is buried may vary, which also makes it difficult to control the dimensions of the gate electrode.

As described above, the pad oxide film (dummy insulating film) and the dummy gate pattern are formed in the area where the gate is to be formed, and the gate insulating film is formed in the groove formed by removing the dummy gate pattern and the dummy insulating film. Further, when forming the gate electrode, there is a problem that it is difficult to control the dimension of the groove, that is, the dimension of the gate electrode.

In addition, Si on the side walls of the dummy gate pattern
_{Even when a 3} N ₄ film or the like is formed, when the dummy insulating film is removed, the dummy insulating film is etched in the lateral direction to form a dent. There is a problem that deterioration and reliability decrease occur. Further, there is a problem that the formation of the depression makes it difficult to control the dimensions of the gate electrode.

On the other hand, in order to improve the performance of a semiconductor integrated circuit using a MIS transistor, a metal material having low resistance is used for at least a part of a gate electrode, or a Ta ₂ O ₅ film is used for at least a part of a gate insulating film. The effective gate insulating film thickness has been reduced by using a high dielectric film such as the above. Then, at this time, in order to avoid deterioration of the characteristics of the gate electrode / gate insulating film due to a high-temperature heating step such as activation of the source / drain regions, the source / drain region layers are formed first, A method has been proposed in which a gate insulating film and a gate electrode are buried and formed in a groove formed in a portion where a gate is to be formed in a self-aligned manner with respect to a source and a drain.

An example of a conventionally proposed manufacturing process of a semiconductor device will be described below with reference to FIGS.

As shown in FIG. 15A, an SiO ₂ film 1 having a thickness of 10 nm is formed on the surface of a transistor forming region of an Si substrate 111 having a trench type element isolation layer (not shown).
Then, a poly-Si film 113 for a dummy gate pattern is deposited on the SiO ₂ film 112 to a thickness of about 300 nm.

Next, as shown in FIG. 15B, the poly-Si film 1 is formed by using, for example, a lithography method and an RIE method.
13 is processed into a dummy gate pattern. Then, FIG.
As shown in FIG. 5C, using the dummy gate pattern 113 as a mask, for example, 4 × 10
^This is performed at a dose of about ¹³ cm ^-2 to form n ^- type source / drain regions 114.

Next, after depositing a Si ₃ N ₄ film on the entire surface,
The whole surface is etched back, and the dummy gate pattern 113 is etched.
Aspect of Si ₃ N ₄ sidewall 115 is formed on, for example, is implanted arsenic ions at a dose of about 5 × 10 ¹⁵ cm ^-2,
An n ⁺ type source / drain region 116 is formed to form an LDD structure shown in FIG. 2D. Then, for example, 1000 ° C.
Annealing is performed for about 30 seconds to activate the source / drain regions.

Next, as shown in FIG. 16E, a CVD-SiO ₂ film 117 is deposited on the entire surface to a thickness of, for example, 300 nm, and densification is performed in an N ₂ atmosphere at, for example, about 800 ° C. for about 30 minutes. After that, the entire surface is flattened by chemical mechanical polishing to expose the upper surface of the dummy gate pattern 113.

Thereafter, as shown in FIG. 16F, the exposed dummy gate pattern 113 is selectively removed, the SiO ₂ film 112 under the dummy gate pattern 113 is removed, and the gate insulating film and the gate electrode are removed. Groove 1 for forming
18 are formed.

Next, for example, T
An a ₂ O ₅ film 119 is formed with a thickness of about 20 nm, a Ru film 120 is deposited as a gate electrode with a thickness of about 300 nm, and the entire surface is processed by a chemical mechanical polishing method.
The gate insulating film 119 and the gate electrode 120 are buried therein, thereby forming a transistor structure as shown in FIG. Thereafter, deposition of an interlayer film (not shown), contact opening, and wiring formation are performed.

[0018]

However, as described above, when the SiO ₂ film 112 is removed, the SiO ₂ film 112 is formed in the groove 118 for forming the gate electrode and the gate insulating film formed as described above. ₂ film 112 is also etched in the lateral direction, and as shown in FIG.
1 is formed. Therefore, the gate insulating film 119
When the gate electrode 120 and the gate electrode 120 are formed, a cavity 122 is formed as shown in FIG. 16 (i), and the embedding failure of the gate electrode 120 occurs, or as shown in FIG. A disadvantage occurs that the radius of curvature of the corner portion 123 becomes small.

As a result, the formed transistor has low reliability such as a low withstand voltage at the gate edge of the gate insulating film.

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a semiconductor device in which deterioration of transistor characteristics and reliability due to a depression at the lower end of a gate electrode which occurs when forming a gate electrode is prevented. is there.

Another object of the present invention is to cause a depression at the lower end of the gate electrode when a gate electrode is formed via a gate insulating film in a region from which the dummy gate pattern and the dummy insulating film (dummy film) have been removed. It is another object of the present invention to provide a method of manufacturing a semiconductor device in which deterioration of transistor characteristics and reliability are prevented.

Still another object of the present invention is to provide a method of manufacturing a semiconductor device which enables a gate electrode to be formed with good controllability.

[0023]

According to the present invention, there is provided a semiconductor device comprising:
Forming a dummy film and a dummy gate pattern, forming a first sidewall insulating film on a side wall of the dummy gate pattern, and forming a semiconductor around the dummy gate pattern on which the first sidewall insulating film is formed. Forming an interlayer insulating film on the substrate, removing the dummy gate pattern to form a groove, and leaving a portion of the first sidewall insulating film and a portion of the dummy film thereunder. ,
A semiconductor device comprising: a step of removing a dummy film exposed in the groove; a step of forming a gate insulating film on at least a bottom surface of the groove; and a step of forming a gate electrode on the gate insulating film in the groove. And a method for producing the same.

Further, the present invention provides a semiconductor substrate, a gate electrode formed on the semiconductor substrate, a gate insulating film formed between the semiconductor substrate and the gate electrode, and on a side surface of the gate electrode, A first sidewall insulating film formed on a gate insulating film formed on a side surface of the gate electrode;
A second sidewall insulating film formed on the first sidewall insulating film; a residual film formed between the first and second sidewall insulating films and the semiconductor substrate; And a semiconductor device including an interlayer insulating film formed around the gate electrode on which the second sidewall insulating film is formed.

Further, the present invention provides a step of forming a dummy film and a dummy gate pattern in a region where a gate is to be formed on a semiconductor substrate, a step of modifying at least a vicinity of a lower end portion of the dummy gate pattern, Forming an interlayer insulating film on the semiconductor substrate around the pattern, removing the dummy gate pattern so as to leave a modified portion of the dummy gate pattern, and forming a groove; A method of manufacturing a semiconductor device, comprising: removing an exposed dummy film; forming a gate insulating film on at least a bottom surface in the trench; and forming a gate electrode on the gate insulating film in the trench. Provide a way.

Still further, according to the present invention, a dummy film and a dummy gate pattern are formed in a region where a gate is to be formed on a semiconductor substrate, and an impurity is introduced into the dummy film at least near a lower end portion of the dummy gate pattern. Forming an interlayer insulating film around the dummy gate pattern, removing the dummy gate pattern to form a groove so as to leave a portion of the dummy film where impurities are introduced, Removing a dummy film exposed in the groove; forming a gate insulating film on at least a bottom surface of the groove; and forming a gate electrode on the gate insulating film in the groove. A manufacturing method is provided.

Still further, the present invention provides a step of forming a dummy film and a dummy gate pattern in a region where a gate is to be formed on a semiconductor substrate, and removing at least a portion of the dummy film near at least a lower end portion of the dummy gate pattern. Forming an insulating material film in a portion where the dummy film has been removed, forming an interlayer insulating film on the semiconductor substrate around the dummy gate pattern, and leaving the insulating material film. Forming a groove by removing the dummy gate pattern, removing a dummy film exposed in the groove, forming a gate insulating film on at least a bottom surface of the groove, Forming a gate electrode on a gate insulating film.

Further, the present invention provides a semiconductor substrate, a gate electrode formed on the semiconductor substrate, a gate insulating film formed between the semiconductor substrate and the gate electrode, and on a side surface of the gate electrode, An interlayer insulating film formed on the semiconductor substrate around the gate electrode, wherein the thickness of the insulating region including the gate insulating film near the lower end of the gate electrode is lower than the gate in the center of the gate electrode. Provided is a semiconductor device which is thicker than an insulating film.

Further, the present invention provides a semiconductor substrate, a first insulating film selectively formed on the semiconductor substrate, and a semiconductor device on which the first insulating film is not formed. A formed gate insulating film, a gate electrode formed on the gate insulating film, a second insulating film formed on a side surface of the gate electrode, and a second formed on a side surface of the gate electrode. A sidewall insulating film formed on the insulating film,
An interlayer insulating film formed around a gate electrode on which the second insulating film and the sidewall insulating film are formed, wherein the total thickness of the gate insulating film and the second insulating film is A semiconductor device having a thickness larger than the thickness of one insulating film is provided.

Still further, according to the present invention, there is provided a semiconductor substrate, a first insulating film selectively formed on the semiconductor substrate, and a selective insulating film on the semiconductor substrate on which the first insulating film is not formed. A gate insulating film, a gate electrode formed on the gate insulating film, a second insulating film formed on a side surface of the gate electrode, and a second insulating film formed on a side surface of the gate electrode. A sidewall insulating film formed on the insulating film, and an interlayer insulating film formed around a gate electrode on which the second insulating film and the sidewall insulating film are formed. A semiconductor device is provided in which the total thickness of the second insulating film is larger than the distance between the lower end of the sidewall insulating film on the gate electrode side and the semiconductor substrate.

In the method of manufacturing a semiconductor device according to the first aspect of the present invention, a sidewall insulating film is formed on a side surface of a dummy gate pattern, and after removing the dummy gate pattern, removing the dummy film thereunder. The removal of the dummy film is performed so as to leave a part of the first sidewall insulating film and a part of the dummy film thereunder.

According to the method of manufacturing a semiconductor device according to the first aspect of the present invention, the first side wall insulating film is formed on the side wall of the dummy gate pattern. The gate pattern and the dummy film can be removed, and the dimensional controllability of the trench for burying the gate electrode, that is, the dimensional controllability of the gate electrode can be improved.

Further, the dummy film and the first side wall insulating film are
By using a material that can be etched at substantially the same etching rate, the dummy film is left under the first sidewall insulating film on the side surface of the gate electrode when the dummy film is removed, and is formed at the lower end of the gate electrode. Since the formation of the depression can be prevented, deterioration in the characteristics and reliability of the transistor caused by the shape of the lower end portion of the gate electrode can be prevented without post-oxidation.

The method for manufacturing a semiconductor device according to the first aspect of the present invention can be implemented in the following specific modes.

(1) The method further includes a step of forming a second sidewall insulating film on the first sidewall insulating film.

(2) The etching rates of the first sidewall insulating film and the dummy film are substantially equal. (3) The method further includes the step of introducing impurities into the semiconductor substrate using the dummy gate pattern as a mask to form source / drain regions.

(4) The dummy gate pattern is made of amorphous silicon.

(5) The first side wall insulating film is formed by thermal oxidation of the dummy gate pattern.

(6) The dummy gate pattern is formed of an amorphous silicon film.

By forming the dummy gate pattern with an amorphous silicon film having a small grain size, it is possible to reduce the unevenness of the pattern edge of the amorphous silicon film during patterning.

(7) The dummy gate pattern is formed of a silicon film (especially an amorphous silicon film is preferable), and the first sidewall insulating film is obtained by thermally oxidizing this silicon film.

When the first side wall insulating film is made of a thermal silicon oxide film, it is possible to perform etching at substantially the same etching rate as that of the dummy film using the thermal silicon oxide film, so that the lower portion of the gate electrode can be more reliably formed. Depression can be prevented from occurring.

(8) A deposited film (CVD-
SiO ₂ film, CVD-SiON film, CVD-Si ₃ N ₄
Film or a laminated film containing them, a high dielectric film (Ta ₂ O ₅ film, (Ba, Sr) TiO ₃ ) formed by CVD
Film, etc.) or a laminated film containing the same.

In particular, by using a high dielectric film as the gate insulating film, the effective thickness of the gate insulating film can be reduced without increasing the leak current or deteriorating the breakdown voltage.

In the semiconductor device according to the second aspect of the present invention, the first and second sidewall insulating films are formed on the side surfaces of the gate electrode, and the gap between the first and second sidewall insulating films and the semiconductor substrate is formed. Has a residual film.

According to the semiconductor device having such a structure, the side surfaces of the gate electrode are covered with the first and second side wall insulating films and the residual film thereunder. As a result, it is possible to prevent the deterioration of the characteristics and the reliability of the transistor caused by the above.

According to the method of manufacturing a semiconductor device according to the third aspect of the present invention, when the dummy film is removed, the modified portion is left near the lower end of the groove, and the dummy film is thereby removed. Since the recession can be suppressed, it is possible to prevent a depression from being formed at the lower end of the gate electrode when removing the dummy film. Therefore, the insulating film at the lower end of the gate electrode is made thicker,
In addition, the radius of curvature at the lower end of the gate electrode can be increased, preventing deterioration of transistor characteristics and reliability due to the shape of the lower end of the gate electrode, such as deterioration of withstand voltage, without performing a post-oxidation step. can do.

In this method, a silicon film (single crystal silicon film, polycrystalline silicon film, amorphous silicon film) is used as a dummy gate pattern and a silicon oxide film is used as a dummy film, and at least the vicinity of the lower end of the dummy gate pattern is modified. Preferably, the step is thermal oxidation of a silicon film to be a dummy gate pattern. With this configuration, the oxidizing agent diffuses in the gate insulating film, so that the oxidation of the lower end of the dummy gate pattern proceeds from the bottom direction, and the vicinity of the lower end of the dummy gate pattern is converted into an insulator in a simple process. Can be quality.

According to the method of manufacturing a semiconductor device according to the fourth aspect of the present invention, when the dummy film is removed, a portion where the impurity is introduced into the dummy film remains near the lower end of the groove. Thus, since the retreat of the dummy film can be suppressed, it is possible to prevent the lower end of the gate electrode from being dented when the dummy film is removed. Therefore, the thickness of the insulating film at the lower end of the gate electrode can be increased, and the radius of curvature of the lower end of the gate electrode can be increased. As a result, it is possible to prevent the deterioration of the characteristics and the reliability of the transistor caused by the above.

In this method, it is preferable that a silicon oxide film is used as the dummy film, and the step of introducing impurities into the dummy film at least near the lower end of the dummy gate pattern is ion implantation of nitrogen or carbon or thermal nitridation. In this way, when removing the dummy film, the dummy film into which the impurity is introduced near the lower end portion of the dummy gate pattern is left by a simple method with good controllability of etching such as dilute hydrofluoric acid treatment. Can be.

Further, according to the method of manufacturing a semiconductor device according to the fifth aspect of the present invention, when removing the dummy film, the insulating material film is left near the lower end of the groove where the dummy film has been removed. As a result, the retreat of the dummy film can be suppressed, so that it is possible to prevent a depression at the lower end of the gate electrode when the dummy film is removed. Therefore, the thickness of the insulating film at the lower end of the gate electrode can be increased, and the radius of curvature of the lower end of the gate electrode can be increased. As a result, it is possible to prevent the deterioration of the characteristics and the reliability of the transistor caused by the above.

In this method, the step of using a silicon oxide film as a dummy film and forming an insulating material film in a portion near the lower end of the dummy gate pattern where the dummy film has been removed is a step of forming a silicon nitride film. Is preferred. In this manner, when removing the dummy film, the insulating material film near the lower end of the dummy gate pattern can be left by a simple method such as dilute hydrofluoric acid treatment with good controllability of etching.

Preferably, in each of the manufacturing methods, a step of forming a source / drain diffusion layer on the semiconductor substrate on both sides of the dummy gate pattern is preferably provided before the step of removing the dummy gate pattern.

In the semiconductor device according to the sixth aspect of the present invention, the thickness of the insulating region including the gate insulating film near the lower end of the gate electrode is larger than the thickness of the gate insulating film at the lower center of the gate electrode. In this case, it is preferable that the radius of curvature at the lower end of the gate electrode is larger than the thickness of the gate insulating film at the lower center of the gate electrode.

FIG. 12 is a graph showing the ratio of the lower end electric field / plane electric field to the radius of curvature of the lower end of the gate electrode at various plane part film thickness / edge part film thickness ratios. In addition,
The radius of curvature r and the thickness a of the plane portion are as shown in FIG. From the graph of FIG. 12, it can be seen that as the thickness of the lower end portion (edge portion) becomes larger and the radius of curvature of the edge portion becomes larger, the edge portion electric field with respect to the plane portion electric field becomes smaller and the electric field concentration at the edge portion is reduced. I understand.

Therefore, according to the semiconductor device of the sixth aspect of the present invention, the electric field at the lower end of the gate electrode is weakened (electric field concentration is reduced), and the insulation (reliability) at the lower end of the gate electrode is improved. .

In the semiconductor device according to the seventh aspect of the present invention, the total thickness of the gate insulating film and the second insulating film formed on the side surface of the gate electrode is equal to the thickness of the portion other than the gate portion of the semiconductor substrate. The thickness is larger than the thickness of the formed first insulating film.
Alternatively, the sum of the thicknesses of the gate insulating film and the second insulating film formed on the side surface of the gate electrode is larger than the distance between the lower end of the sidewall insulating film on the gate electrode side and the semiconductor substrate.

According to such a structure of the semiconductor device, the lateral groove formed between the surface of the silicon substrate at the gate edge portion and the sidewall insulating film is completely filled with the gate insulating film.
Since the shape of the edge of the gate electrode has a large radius of curvature, a semiconductor device with improved reliability at the gate edge can be obtained.

[0059]

Embodiments of the present invention will be described below with reference to the drawings.

First, a first embodiment of the present invention will be described.

FIG. 1A is a plan view of a semiconductor device according to the first embodiment of the present invention, FIG. 1B is a cross-sectional view taken along the line AA ′ of FIG. ) Is BB ′ in FIG.
The sectional views are respectively shown.

In FIG. 1, the impurity concentration is 1 to 5 × 10 ¹⁵
Element isolation insulating film 1 of p-type silicon substrate 11 of about cm ^-3
The impurity concentration of 5 × 10
^An n-type diffusion region 17 serving as a source / drain region with a diffusion region depth of approximately 0.10 μm and a diffusion region depth of approximately ¹⁹ cm ⁻³ is formed. A p-type channel impurity region (not shown) having an impurity concentration of about 5 × 10 ¹⁷ cm ⁻³ for controlling Vth) is selectively formed mainly only in the channel region.

On the channel region, a gate insulating film 19 made of, for example, an SiO ₂ film having a thickness of about 5 nm is formed. Further, a conductive film (for example, Ti) whose bottom is surrounded by the gate insulating film 19 and whose side is surrounded by a part of the oxide film 15 obtained by oxidizing the gate insulating film 19 and the dummy gate film.
A gate electrode 20 made of an N film, a Ru film, a W film, an Al film, a Cu film, or a laminated film thereof is formed in a self-aligned manner with respect to the source / drain region 17.

The gate width L in the channel length direction is, for example, about 0.15 μm. A wiring 22 is formed on the interlayer insulating film 21, and the wiring 22 is formed on the interlayer insulating film 21.
Are connected to the gate electrode 20 and the source / drain region 17.

2 and 3 (A- of FIG. 1A).
FIG. 1 is a sectional view showing a manufacturing process corresponding to the A ′ section.
The manufacturing process of the transistor shown in FIG.

First, as shown in FIG. 2A, a p-type silicon substrate 11 having an impurity concentration of about 5 × 10 ¹⁵ cm ^-3 (p-type or n-type epitaxial For example, a so-called epitaxial substrate in which a Si layer is grown to a thickness of about 1 μm may be used.
On the 0) plane, a p-well (not shown) is formed in the n-channel transistor formation region, and an n-well (not shown) is formed in the p-channel transistor formation region.

Thereafter, a groove is formed in the Si substrate 11 by, for example, a reactive ion etching (RIE) method, and an insulating film is buried in the groove to form a so-called trench type element isolation layer 12 (trench depth of about 0.2 μm). STI (Shal
low Trench Isolation)). Then, thickness 5
A pad oxide film (dummy insulating film) 13 of about ₂ nm of SiO _{2 is} formed by thermal oxidation.

Next, an amorphous Si film 14 for a dummy gate pattern is deposited on this SiO ₂ film 13 to a thickness of about 300 nm, and this is formed by a RIE method using a resist formed by a usual lithography method as a mask. To form a dummy gate pattern 14 which is removed in a later step to form a gate electrode. The size of the dummy gate pattern 14 at this time is L1.

Since the dummy gate pattern 14 is formed of amorphous Si having a small grain size, the pattern of the amorphous Si film at the time of patterning is reduced.
The edge has a feature that there are few irregularities. In the present embodiment, the dummy gate pattern 14 is made of amorphous Si, but may be made of poly Si having a small grain size. When the dummy gate pattern 14 is made of a Si-based material, the R
Since it is easy to set a high etching selectivity with respect to the SiO ₂ film 13 during IE, the etching (RI
E) Damage can be suppressed.

Next, as shown in FIG. 2B, the surface of the dummy gate pattern 14 made of amorphous Si is thermally oxidized in an oxygen atmosphere at, for example, 850 ° C. to form an oxide film 15 having a thickness of about 10 nm. Form. The thickness of the oxide film 15 is larger than the thickness of the pad oxide film (1.
It is preferable that the thickness is about 5 to 3 times. When the size of the dummy gate pattern 14 after oxidation and L _2, L ₂ is smaller than only L ₁ minute oxidized (L ₂ <L _1).

Next, as shown in FIG.
(Lightly Doped Drain) structure is formed by using the dummy gate pattern 14 and the SiO ₂ film 15 as a mask, and in the case of an n-channel transistor, for example, phosphorus (P ⁺ ) ion implantation is performed at 70 keV and 4 × 10 ¹³ cm. ^-2
The n ^- type diffusion region 17a is formed. Subsequently, after depositing a Si ₃ N ₄ film (or SiO ₂ film) on the entire surface, RIE is performed on the entire surface to form a dummy gate pattern 14.
Of the side wall leaving the Si ₃ N ₄ film (or SiO ₂ film) subjected to so-called "sidewall leaving process", the sidewall insulating film 16 having a thickness of about 20nm on the SiO ₂ film 15 on the sidewall of the dummy gate pattern 14 Form.

Thereafter, using the dummy gate pattern 14 and the side wall film 16 as a mask, for example, arsenic (As ⁺ )
Ion implantation is performed at about 30 keV and about 5 × 10 ¹⁵ cm ⁻² to form an n ⁺ -type diffusion region 17b.
Form the structure. Although the LDD structure is employed here, a so-called single source / drain structure having only the n ⁻ type diffusion region or only the n ⁺ type diffusion region may be employed.

Next, CVD-S to be an interlayer insulating film is formed on the entire surface.
An iO ₂ film 18 is deposited, for example, to a thickness of about 400 nm,
Densification is performed in an N ₂ atmosphere at about 00 ° C. for about 30 minutes. This heat step also serves to activate the source / drain ion implantation regions. To reduce the depth (X _j ) of the diffusion region, the temperature of the densify is lowered to about 750 ° C., and RTA (Rapid Therma) is performed at 950 ° C. for about 10 seconds.
l Anneal) process may be used in combination to activate the ion implantation region.

Thereafter, the entire surface is subjected to CMP (Chemical Mechanical).
Cal Polishing) to expose the surface of the dummy gate pattern 14.

Next, as shown in FIG. 2D, the dummy gate pattern 14 is selectively removed from an oxide film or the like by a CDE (Chemical Dry Etching) method or a wet etching method using a KOH solution. The groove 30 is formed. Thereafter, using a resist pattern (not shown) formed in a desired region, the SiO ₂ film 18 serving as an interlayer insulating film, the sidewall insulating film 16 and the SiO ₂ film 15 as masks,
Channel ion implantation is performed only in a desired channel region. In the case of an n-channel transistor, for example, in order to set a threshold voltage (Vth) of about 0.7 V, for example, boron (B ⁺ ) is ion-implanted at about 10 keV and about 5 × 10 ¹² cm ⁻² into the channel region. Only a p-type channel impurity region (not shown) is selectively formed.

[0076] The ion implantation process may be performed through the SiO ₂ film 13, by peeling off the SiO ₂ film 13 again to form a SiO ₂ film according to the general this newly formed SiO
It may be performed through _two films. After that, activation of the channel impurity region is performed at 800 ° C. for 10
The heat treatment is performed for about a second. After that, since there is no high-temperature heat step, the impurity profile of the channel region can be optimized so that the short channel effect of the transistor can be suppressed.

Next, as shown in FIG. 3E, the pad oxide film 13 at the bottom of the groove is removed. Both the oxide film 15 and the pad oxide film 13 on the trench side wall are thermal oxide films, and are etched at substantially the same etching rate.
Is thicker than the pad oxide film 13, a part of the side wall oxide film 15 remains on the groove side wall even after the pad oxide film 13 is peeled off.

At this time, the groove width L ₃ is larger than L ₂ by the removal of the sidewall oxide film 15 (L ₃ > L ₂ ).
Further, since the sidewall oxide film 15 and the pad oxide film 13 are etched at substantially the same etching rate, a depression is generated due to excessive etching of the pad oxide film 13 under the sidewall oxide film 15 and the sidewall nitride film 16. Can be prevented.

By using such a method, since the side surfaces of the dummy gate pattern 14 are completely covered with the oxide film when the dummy gate pattern 14 is removed, the dummy gate pattern 14 can be formed in a stable and marginal process. Can be peeled. Also, even when the pad oxide film 13 is peeled off, the recession of the sidewall insulating film 16 and the like can be prevented by the oxide film on the side wall of the groove, and the dimension (L ₄ ) of the gate electrode formed in a later step can be controlled. There is a feature that can be. That is, the final gate electrode dimension (L ₄ ) is L
It is determined by the sum of ₃ and twice the thickness (Tox) of the gate insulating film (L ₄ = L ₃ + 2 × Tox). L ₃ is the oxidation amount (oxide film thickness) of the dummy gate pattern 14 and the pad oxide film 13.
Of it can be controlled in peeling amount (over-etching amount), that the L ₄ equal to the width L of the dummy gate patterns, it is possible to reduce.

Next, as shown in FIG.
A gate insulating film 19 made of a VD-SiO ₂ film (thickness is about 3 nm) or a high dielectric film (for example, a Ta ₂ O ₅ film with a thickness of about 20 nm) is deposited. When the gate insulating film 19 is a high dielectric film, a thin (for example, about 1 nm) Si film is formed on the interface so that an interface state or the like is not easily formed between the gate insulating film 19 and the Si interface.
O ₂ film (not shown) or RTP (Rapid Thermal Proc)
ess), a film (not shown) directly nitrided on the Si surface in an NH ₃ gas atmosphere may be formed.

The gate insulating film 19 is formed by CVD
-SiON _x film (oxynitride film) and CVD-S
A stacked film including an i ₃ N ₄ film may be used. In these cases, after film formation, for example, at 1000 ° C. for about 10 seconds, RT
Densification may be performed by performing a heat treatment with P. By doing so, the insulating properties of the insulating film can be improved, for example, the interface state at the Si interface decreases and the leak current decreases.

When a high dielectric film is used for a gate insulating film,
The effective thickness of the gate insulating film can be reduced without increasing a leak current or deteriorating a withstand voltage, so that a short channel effect of a transistor can be suppressed. In addition, it is possible to increase the drain current and the cutoff characteristics.

Next, as shown in FIG. 3 (g), for example, a metal film (Ru film, TiN film, W film, tungsten nitride film (WN _x ), or a W film / TiN film) The gate electrode 20 is deposited on the entire surface. Of course, CVD-SiO ₂ film, CVD
When the -SiON film or the gate insulating film a multilayer film including a CVD-Si ₃ N ₄ film, a polycrystalline Si film doped with impurities may be used as the gate electrode.

Then, after depositing a gate insulating film 19 and a metal electrode 20 on the entire surface, CMP for the metal material is performed.
By performing CMP under the conditions, the gate insulating film 19 and the metal electrode 20 are buried in the trench after removing the dummy gate pattern. At this time, the SiO ₂ film 18 and the gate insulating film 19 serve as stoppers for the CMP of the metal film. The gate insulating film 19 may remain on the SiO ₂ film 18.

The width of the gate electrode (L _{4 in} FIG. 3F) is
The width L ₁ of the dummy gate pattern 14 shown in FIG. 2A can be reduced by twice the thickness of the gate insulating film 19 (L ₁ = L ₃ ). That is, the minimum dimension determined by lithography is L (here, it is assumed to be 0.15 μm), and the thickness of the gate insulating film is 0.1 μm.
Assuming that it is 02 μm, it can be shorter than L by twice the thickness of the gate insulating film (0.02 μm × 2 = 0.04 μm). Therefore, the limit of lithography is 0.1
Despite being 5 μm, a gate electrode width (L ₄ ) of 0.11 μm can be realized. That is, there is a feature that the channel length of the transistor can be made shorter than the dimension determined by lithography.

Of course, in consideration of the fact that this channel length is reduced by twice the thickness of the gate insulating film, the pad oxide film 1
3 and the oxide film 1 of the amorphous Si film 14
By adjusting the film thickness of _{No. 5} , it is also possible to obtain a dimension substantially equal to L1 shown in FIG. In addition, Ta ₂ O
_In the case of a high dielectric film such as ₅ films, the actual film thickness is large,
The length of L ₄ can significantly be shortened.

Next, as shown in FIG.
After depositing an interlayer insulating film 21 of iO ₂ to a thickness of about 200 nm, a contact hole 23 to the source / drain region 17 and the gate electrode 20 is opened, and an Al layer is further deposited to fill the contact hole 23. Then, the wiring 22 is formed by patterning. Thereafter, a passivation film (not shown) is deposited on the entire surface, and a basic structure of the transistor is manufactured.

According to the manufacturing method described above, the dummy gate pattern is made of amorphous Si having a small grain size, so that the amorphous
The unevenness of the pattern edge of the film can be reduced.
Further, since the side surface of the dummy gate pattern is completely covered with the oxide film when the dummy gate pattern is removed, the dummy gate pattern can be peeled off by a stable and marginal process. Thus, the size of the gate electrode formed in a later step can be controlled. Further, even when the pad oxide film is peeled off, the recession of the sidewall insulating film and the like can be prevented by the oxide film on the side wall of the groove, and the dimensions of the gate electrode formed in a later step can be controlled. Further, since the oxide film on the trench side wall and the pad oxide film are etched at substantially the same etching rate, it is possible to prevent the occurrence of a depression due to excessive etching of the pad oxide film under the sidewall oxide film and the sidewall nitride film. .

In addition, since the gate electrode is processed by using CMP without plasma damage, it is possible to avoid damage (such as dielectric breakdown of a gate insulating film) due to a plasma process which easily occurs during RIE. In addition, since a high-temperature heat treatment process such as an ion implantation region activation and a reflow process can be performed before forming a gate insulating film (such as a laminated film including a high-dielectric film), a leak current of the gate insulating film is increased and a withstand voltage is deteriorated. Such deterioration can be avoided. Further, since the side surface of the gate electrode is covered with an amorphous Si oxide film, the breakdown voltage between the gate electrode and the substrate or between the gate electrode and the source / drain can be maintained well without post-oxidation.

Further, the source / drain region is formed before the gate electrode. The gate electrode can be formed in the source / drain region in a self-aligned manner. That is, the gate electrode and the source / drain diffusion region can be formed in a self-aligned manner as in the related art. Further, a channel ion implantation region for adjusting the threshold voltage (Vth) of the transistor can be formed only in the channel region, and junction leakage and junction capacitance between the source and drain can be reduced. In addition, this channel ion implantation region
Since a high-temperature thermal step of activation annealing of the drain region is not performed, an ideal channel impurity profile for suppressing a short channel effect can be formed and maintained.

Further, the channel length of the transistor can be reduced by twice the thickness of a deposited film such as a high dielectric film serving as a gate insulating film to a dimension determined by the limit of lithography. , The performance of the transistor can be improved. Also, by forming a gate insulating film using a deposited film such as CVD, the STI Si
At the corner portion of the surface, a very small depression (a gate insulating film and a gate electrode are formed in the region of the depression, which forms a parasitic transistor at the corner portion and causes a problem such as changing the threshold value of the transistor) is buried. Therefore, formation of a parasitic transistor in a corner portion can be suppressed, and variation in a threshold value can be suppressed.

Next, a second embodiment of the present invention will be described.

First, a first specific example of the second embodiment will be described with reference to the process sectional views shown in FIGS.

First, as shown in FIG. 4A, a 10-nm-thick element is formed on the surface of the Si substrate 61 in the element formation region surrounded by the trench-type element isolation region (Shallow Trench Isolation) 62.
A SiO ₂ film 63 (dummy insulating film) having a thickness of about m is formed, and a polysilicon film 64 for a dummy gate pattern is deposited on the SiO ₂ film 63 to a thickness of about 300 nm.

Next, as shown in FIG. 4B, the poly-Si film 6 is formed by using, for example, lithography and RIE.
4 is processed into a dummy gate pattern shape.

Next, as shown in FIG.
1000 ° C by TO (Rapid Thermal Oxidation)
Thermal oxidation is performed in about 60 seconds, and a dummy gate pattern 64 is formed.
Rounding the edge portion, increasing the thickness of the SiO ₂ film 63 under the edge portion, and increasing the thickness of the Si
An O ₂ film 65 is formed.

Next, as shown in FIG.
Using the film 64 / SiO ₂ film 65 as a mask, for example, phosphorus (P ⁺ ) ion implantation is performed at 70 keV, 4 × 10 ¹³ c
An n ⁻ -type region 67 a is formed at a dose of about m ⁻² .

[0098] Next, as shown in FIG. 4 (e), Si ₃ N
After depositing the ₄ film on the entire surface, RIE is performed on the entire surface, and a so-called “Si ₃ N ₄ side wall remaining” that leaves a Si ₃ N ₄ film on the side wall of the dummy gate pattern 64 is performed. A Si ₃ N ₄ film 66 having a thickness of about 20 nm is formed.

Thereafter, as shown in FIG. 4F, for example, arsenic (As ⁺ ) ions are implanted at 30 keV and 5 × 10 ¹⁵
By performing about cm ⁻² , an n ⁺ -type region 67b is formed to form a so-called LDD structure.

Next, as shown in FIG. 5F, a CVD-SiO ₂ film 68 serving as an interlayer
After depositing to a thickness of about nm and performing densification in an N ₂ atmosphere at about 800 ° C. for about 30 minutes, the entire surface is flattened by CMP to expose the surface of the dummy gate pattern 64.

Next, as shown in FIG. 5H, after the exposed poly-Si film 64 is selectively removed to form the groove 71, a resist pattern (not shown) formed in a desired region is formed. Using the SiO ₂ film 68, the sidewall insulating film Si ₃ N ₄ film 66, and the SiO ₂ film 65 as masks, channel ion implantation is performed only in the channel region. The activation of the channel impurity region 72 is performed, for example, by RTA (Rapid Therma
l Anneal) at 800 ° C. for about 10 seconds.

[0102] Next, FIG. 5 as shown in (i), for example by dilute hydrofluoric acid treatment, SiO ₂ so as to leave only the edge portion
The film 63 and the SiO ₂ film 65 are removed. At this time, since the SiO ₂ film 63 remains at the edge, no depression is formed at the edge. Thereafter, a gate insulating film 69 made of, for example, a high dielectric film (for example, a Ta ₂ O ₅ film) is deposited on the entire surface to a thickness of about 20 nm.

Next, as shown in FIG.
After a metal such as u is deposited on the entire surface, the entire surface is subjected to CMP, and a gate electrode 70 made of a high dielectric gate insulating film 69 and a metal film is formed in the groove after the dummy gate pattern 64 is removed. Embed.

Thereafter, SiO ₂ was used as an interlayer insulating film on the entire surface.
A film (not shown) is deposited to a thickness of about 200 nm, contact holes to the source / drain regions 67 and the gate electrode 70 are opened, and an Al layer (not shown) is formed. The holes are filled and patterned to form wiring. Further, a passivation film (not shown) is deposited on the entire surface to form a basic structure of the transistor.

Next, a second specific example of the second embodiment will be described with reference to the process sectional views shown in FIGS.

First, as shown in FIG. 6A, an SiO ₂ film 63 (dummy insulating film) having a thickness of about 10 nm is formed on the surface of the Si substrate 61 in the element formation region surrounded by the trench type element isolation region 62. Then, a poly-Si film 64 for a dummy gate pattern is formed on the SiO ₂ film 63 to a thickness of 300 nm.
It is deposited to about nm.

Next, as shown in FIG. 6B, the poly-Si film 6 is formed using, for example, lithography and RIE.
4 is processed into a dummy gate pattern shape.

Next, as shown in FIG.
1000 by TN (Rapid Thermal Nitridation)
° C, thermal nitridation for about 60 seconds, or 30 keV, 1 × 10
By performing nitrogen ion implantation of about ¹⁴ cm _-2 (the ions to be implanted may be carbon ions), a nitrogen-containing portion 63a is formed in the SiO ₂ film 63. At this time, as shown in FIG, SiO ₂ edge subordinates of the dummy gate pattern 64
Nitrogen is also introduced into the film 63. Note that a nitrogen-containing portion 64a is also formed in the surface region of the poly-Si film 64.

Next, as shown in FIG.
Using the film 64 (including the nitrogen-containing portion 64a) as a mask, for example, phosphorus (P ⁺ ) ion implantation is performed at 70 keV,
The process is performed at about × 10 ¹³ cm ⁻² to form an n ⁻ type diffusion region 67a.

[0110] Next, as shown in FIG. 6 (e), Si ₃ N
After depositing the ₄ film on the entire surface, RIE is performed on the entire surface, and a so-called “Si ₃ N ₄ side wall remaining” that leaves a Si ₃ N ₄ film on the side wall of the dummy gate pattern 64 is performed. A Si ₃ N ₄ film 66 having a thickness of about 20 nm is formed.

Thereafter, as shown in FIG. 6F, for example, arsenic (As ⁺ ) ions are implanted at 30 keV and 5 × 10 ¹⁵
By performing about cm ⁻² , an n ⁺ -type region 67b is formed to form a so-called LDD structure.

Next, as shown in FIG. 7A, a CVD-SiO ₂ film 68 serving as an interlayer insulating film is
about 3 nm in an N ₂ atmosphere of about 800 ° C.
After performing densification for about 0 minutes, the entire surface is flattened by CMP to expose the surface of the dummy gate pattern 64 (the nitrogen-containing portion 64a).

Next, as shown in FIG. 7H, the exposed dummy gate pattern 64 is selectively removed to form the groove 71.
Is formed, a resist pattern (not shown) formed in a desired region, the SiO ₂ film 68 and the sidewall insulating film Si ₃ N
_{Using the four} films 66 as a mask, channel ion implantation is performed only in the channel region. The activation of the channel impurity region 72 is performed at 800 ° C. for 10
The heat treatment is performed for about a second.

Next, as shown in FIG. 7 (i), for example, a dilute hydrofluoric acid treatment is performed to remove the SiO ₂ so as to leave only the edges.
The film 63 is removed. At this time, the SiO ₂ film 63 at the edge portion
Is formed with a nitrogen-containing portion 63a, so no dent is formed at the edge portion. Thereafter, a gate insulating film 69 made of, for example, a high dielectric film (eg, a Ta ₂ O ₅ film) is deposited on the entire surface to a thickness of about 20 nm.

Next, as shown in FIG. 7 (j), a metal such as Ru is deposited on the entire surface as a gate electrode, and then the entire surface is subjected to CMP to remove the dummy gate pattern 64 from the groove. A high dielectric gate insulating film 69 and a gate electrode 70 made of metal are buried therein.

Thereafter, SiO _{2 is used} as an interlayer insulating film on the entire surface.
A film (not shown) is deposited to a thickness of about 200 nm, a contact hole is opened in the source / drain region 67 and the gate electrode 70, and an Al layer (not shown) is formed. The holes are filled and patterned to form wiring. Further, a passivation film (not shown) is deposited on the entire surface to form a basic structure of the transistor.

Next, a third specific example of the second embodiment will be described with reference to the process sectional views shown in FIGS.

First, as shown in FIG. 8A, a SiO ₂ film 63 (dummy insulating film) having a thickness of about 10 nm is formed on the surface of the Si substrate 61 in the element formation region surrounded by the trench type element isolation region 62. Then, a poly-Si film 64 for a dummy gate pattern is formed on the SiO ₂ film 63 to a thickness of 300 nm.
It is deposited to a film thickness of the order.

Next, as shown in FIG. 8B, the poly-Si film 6 is formed using, for example, lithography and RIE.
4 is processed into a dummy gate pattern shape.

Next, as shown in FIG. 8C, using the poly-Si film 64 of the dummy gate pattern as a mask,
For example, phosphorus (P ⁺ ) ion implantation is performed at 70 keV, 4 × 1
The process is performed at about 0 ¹³ cm ⁻² to form an n ⁻ type region 67a.

Next, as shown in FIG. 8D, the dummy gate insulating film 63 at the edge portion is removed by dilute hydrofluoric acid treatment, and subsequently, a Si ₃ N ₄ film 66a is deposited on the entire surface. At this time, as shown in FIG.
The i ₃ N ₄ film 66a is embedded.

Next, as shown in FIG.
IE is performed, and Si _{3 is formed on} the side wall of the dummy gate pattern.
The so-called “remaining side wall of Si ₃ N ₄ ” is performed to leave the N ₄ film, and a Si ₃ N ₄ film 66 a having a thickness of about 20 nm is formed on the side wall of the dummy gate pattern 64.

Thereafter, as shown in FIG. 8F, for example, arsenic (As ⁺ ) ion implantation is performed at 30 keV and 5 × 10 ¹⁵
By performing about cm ^−2, the n ⁺ -type region 67b is formed to form a so-called LDD structure.

Next, as shown in FIG. 9G, a CVD-SiO ₂ film 68 serving as an interlayer insulating film is
about 3 nm in an N ₂ atmosphere of about 800 ° C.
After performing densification for about 0 minutes, the entire surface is planarized by CMP to expose the dummy gate pattern 64.

Next, as shown in FIG. 9H, the exposed dummy gate pattern 64 is selectively removed to form the groove 71.
Is formed, a resist pattern (not shown) formed in a desired region, a SiO ₂ film 68 and a sidewall insulating film Si ₃ N
_{Using the four} films 66a as a mask, channel ion implantation is performed only in the channel region. The activation of the channel impurity region 72 is performed at 800 ° C.,
The heat treatment is performed for about 0 seconds.

Next, as shown in FIG. 9I, the SiO ₂ film 63 is removed by, for example, dilute hydrofluoric acid treatment so as to leave the Si ₃ N ₄ film 66a at the edge. At this time, since the Si ₃ N ₄ film 66a is formed at the edge, no depression is formed at the edge. Thereafter, a gate insulating film 69 made of, for example, a high dielectric film (for example, Ta ₂ O ₅ film) is formed on the entire surface.
Is deposited to a thickness of about 20 nm.

Next, as shown in FIG.
After depositing a metal such as u on the entire surface, the entire surface is subjected to CMP to bury a high dielectric gate insulating film 69 and a gate electrode 70 made of metal in the trench after the dummy gate pattern is removed.

Thereafter, SiO ₂ was used as an interlayer insulating film on the entire surface.
A film (not shown) is deposited to a thickness of about 200 nm, a contact hole is opened in the source / drain region 67 and the gate electrode 70, and an Al layer (not shown) is formed. The holes are filled and patterned to form wiring. Further, a passivation film (not shown) is deposited on the entire surface to form a basic structure of the transistor.

According to the second embodiment described above, the thickness of the gate insulating film at the edge of the gate electrode is large.
Since the radius of curvature of the gate electrode is increased, the reliability of the gate insulating film at the edge is improved. In addition, since the thickness and rounding of the edge portion are performed in a self-aligned manner with respect to the gate electrode and the source / drain, device characteristics and high reliability with little variation can be realized.

The present invention is not limited to the above embodiments, but can be implemented with various modifications without departing from the spirit thereof.

According to the present invention, it is possible to prevent a dent caused by the lateral etching of the dummy film when removing the dummy film, so that the transistor formed due to the dent at the lower end of the gate electrode can be prevented. Deterioration of characteristics and reliability can be prevented.

Further, since the dummy gate pattern and the dummy film can be removed by a stable process with a margin, the dimensional controllability of the groove for burying the gate electrode, that is, the dimensional controllability of the gate electrode can be improved.

Next, a third embodiment of the present invention will be described.
This will be described with reference to the process cross-sectional views shown in FIGS.

As shown in FIG. 10A, a 5-nm-thick SiO ₂ film 82 is formed on the surface of a transistor forming region of a Si substrate 81 having a trench-type element isolation layer (not shown). _{On the second} film 82, a poly-Si film 83 for a dummy gate pattern is deposited to a thickness of about 300 nm.

Next, as shown in FIG. 10B, the poly-Si film 8 is formed using, for example, lithography and RIE.
3 is processed into a dummy gate pattern. Then, FIG.
As shown in (c), for example, phosphorus ions are implanted at 4 × 10 ¹³ c using the dummy gate pattern 83 as a mask.
This is performed at a dose of about m ⁻² to form n ⁻ type source / drain regions 84.

Next, after depositing a Si ₃ N ₄ film on the entire surface,
The whole surface is etched back to form a Si ₃ N ₄ side wall insulating film 85 on the side surface of the dummy gate pattern 83, and for example, arsenic ion implantation is performed at about 5E15 cm ⁻² to perform n ⁺ type source
A drain region 86 is formed, and the LDD shown in FIG.
Form the structure. After that, annealing at, for example, 1000 ° C. for about 30 seconds is performed to activate the source / drain regions.

Next, as shown in FIG. 10E, a CVD-SiO ₂ film 87 is deposited on the entire surface to a thickness of, for example, 300 nm, and densification is performed for about 30 minutes in an N ₂ atmosphere at, for example, about 800 ° C. After that, the entire surface is flattened by chemical mechanical polishing to expose the upper surface of the dummy gate pattern 83.

After that, as shown in FIG. 10F, the exposed dummy gate pattern 83 is selectively removed, and the SiO ₂ film 82 under the dummy gate pattern 83 is removed.
A groove 88 for forming a gate insulating film and a gate electrode is formed.

Next, the Si substrate 8 is formed using, for example, NO gas.
After a 1.5 nm oxynitride film 89 is formed on the substrate 1, a Ta ₂ O ₅ film 90 having a thickness of, for example, 5 nm and a Ru film 91 having a thickness of, for example, about 300 nm are deposited as a gate electrode. By performing a mechanical polishing method, a gate insulating film composed of an oxynitride film 89 and a Ta ₂ O ₅ film 90 and a gate electrode 91 composed of a Ru film are buried in the trench 88, and FIG.
A transistor structure as shown in FIG. Thereafter, deposition of an interlayer film (not shown), contact opening, and wiring formation are performed.

Here, as shown in FIG. 11H, the thickness t _{3 of the} gate insulating film formed on the bottom surface of the gate electrode 91 is reduced.
Is a 1.5 nm thick oxynitride film 89 and a Ta ₂ O ₅ film 90.
The thickness t ₄ of the Ta ₂ O ₅ film 90 formed on the side surface of the gate electrode is 5 nm, and the thickness t ₁ of the SiO ₂ film 82 is between 5 nm and 5 nm. T ₃
+ T ₄ > t _{1, and} the relationship t ₃ + t ₄ > t ₁ ′ is established using the distance t ₁ ′ between the lower end of the Si ₃ N ₄ film 85 and the surface of the Si substrate 81. I am trying to do it.

[0141] With the configuration described above, as shown in FIG. 11 (i), SiO ₂ under the dummy gate pattern 83
The lateral groove formed when removing the film 82 is filled with the gate insulating film, and the shape of the edge of the gate electrode has a large radius of curvature, realizing a highly reliable transistor structure at the gate edge. did.

As described above, according to the third embodiment of the present invention, the lateral groove formed between the silicon substrate surface at the gate edge portion and the side wall insulating film is completely filled with the gate insulating film, and the gate electrode is formed. Since the shape of the edge has a large radius of curvature, a semiconductor device with improved reliability at the gate edge can be obtained.

[0143]

According to the present invention, when the dummy film is removed, it is possible to prevent the dent caused by the lateral etching of the dummy film. Deterioration of characteristics and reliability of the transistor can be prevented.

Further, since the dummy gate pattern and the dummy film can be removed by a stable process with a margin, the dimensional controllability of the groove for burying the gate electrode, that is, the dimensional controllability of the gate electrode can be improved.

[Brief description of the drawings]

FIG. 1 is a plan view and a sectional view showing a configuration of a semiconductor device according to a first embodiment of the present invention;

FIG. 2 is a sectional view showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention;

FIG. 3 is a sectional view showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention;

FIG. 4 is a sectional view showing a manufacturing process of the semiconductor device according to the first specific example of the second embodiment of the present invention;

FIG. 5 is a sectional view showing a manufacturing process of the semiconductor device according to the first specific example of the second embodiment of the present invention;

FIG. 6 is a sectional view showing a manufacturing process of a semiconductor device according to a second specific example of the second embodiment of the present invention;

FIG. 7 is a sectional view showing a manufacturing process of a semiconductor device according to a second specific example of the second embodiment of the present invention;

FIG. 8 is a sectional view showing a manufacturing process of a semiconductor device according to a third specific example of the second embodiment of the present invention;

FIG. 9 is a sectional view showing a manufacturing process of a semiconductor device according to a third specific example of the second embodiment of the present invention;

FIG. 10 is a sectional view showing a manufacturing step of the semiconductor device according to the third embodiment of the present invention.

FIG. 11 is a sectional view showing a manufacturing step of the semiconductor device according to the third embodiment of the present invention.

FIG. 12 is a characteristic diagram showing the effect of increasing the radius of curvature of the gate edge;

FIG. 13 is an enlarged view showing the vicinity of a gate edge;

14 is a cross-sectional view of a conventional transistor obtained by forming a Si ₃ N ₄ film on a side wall of a dummy gate pattern;

FIG. 15 is a cross-sectional view showing a conventional method of manufacturing a semiconductor device in which the thickness of the gate insulating film is reduced by using a high dielectric film as a part of the gate insulating film;

16 is a cross-sectional view showing a conventional method of manufacturing a semiconductor device in which the thickness of a gate insulating film is reduced by using a high-dielectric film as a part of the gate insulating film;

[Explanation of symbols]

 11, 61, 81, 111 ... silicon substrate 12, 62, 112 ... element isolation region 13, 63, 82, 82 ... silicon oxide film (dummy film) 14, 64, 83, 113 ... dummy gate pattern 15, 65, ... Silicon oxide film (first side wall oxide film) 16, 66 ... silicon nitride film (second side wall oxide film) 17, 67 ... source / drain diffusion layer 18, 68 ... interlayer insulating film 19, 69 ... gate insulating film 20 , 70 gate electrode 30, 71 groove 63a impurity-containing portion 66a silicon nitride film

 ──────────────────────────────────────────────────の Continued on the front page (72) Inventor Tetsuro Matsuda 8 Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa Inside Toshiba Yokohama Office

Claims (8)

[Claims] A step of forming a dummy film and a dummy gate pattern in a region where a gate is to be formed on a semiconductor substrate; a step of forming a first side wall insulating film on a side wall of the dummy gate pattern; Forming an interlayer insulating film on the semiconductor substrate around the dummy gate pattern on which the sidewall insulating film is formed; removing the dummy gate pattern to form a groove; Removing the dummy film exposed in the groove so as to leave a part and the part of the dummy film thereunder; forming a gate insulating film on at least a bottom surface of the groove; and forming the gate in the groove. Forming a gate electrode on the insulating film. 2. A semiconductor substrate; a gate electrode formed on the semiconductor substrate; a gate insulating film formed between the semiconductor substrate and the gate electrode and on a side surface of the gate electrode; A first sidewall insulating film formed on a gate insulating film formed on a side surface, a second sidewall insulating film formed on the first sidewall insulating film, and the first and second sidewall insulating films A semiconductor device comprising: a residual film formed between a film and the semiconductor substrate; and an interlayer insulating film formed around a gate electrode on which the first and second sidewall insulating films are formed. 3. A step of forming a dummy film and a dummy gate pattern in an area where a gate is to be formed on a semiconductor substrate, a step of modifying at least a lower end portion of the dummy gate pattern, and a step of modifying the periphery of the dummy gate pattern. Forming an interlayer insulating film on the semiconductor substrate; removing the dummy gate pattern so as to leave a modified portion of the dummy gate pattern to form a groove; and a dummy film exposed to the groove. A method of forming a gate insulating film on at least a bottom surface in the groove; and a step of forming a gate electrode on the gate insulating film in the groove. 4. A step of forming a dummy film and a dummy gate pattern in a region where a gate is to be formed on a semiconductor substrate; a step of introducing an impurity into the dummy film at least near a lower end of the dummy gate pattern; Forming an interlayer insulating film around the gate pattern, and leaving a portion of the dummy film into which the impurity is introduced,
Removing the dummy gate pattern to form a groove; removing the dummy film exposed in the groove; forming a gate insulating film on at least a bottom surface of the groove; and forming the gate insulating film in the groove. Forming a gate electrode on the film. 5. A step of forming a dummy film and a dummy gate pattern in a region where a gate is to be formed on a semiconductor substrate; a step of removing at least a portion of the dummy film near a lower end of the dummy gate pattern; Forming an insulating material film on a portion where the dummy film has been removed; forming an interlayer insulating film on the semiconductor substrate around the dummy gate pattern; and forming the dummy gate film so as to leave the insulating material film. Forming a groove by removing a pattern; removing a dummy film exposed in the groove; forming a gate insulating film on at least a bottom surface of the groove; and forming a gate insulating film on the gate insulating film in the groove. Forming a gate electrode. 6. A semiconductor substrate; a gate electrode formed on the semiconductor substrate; a gate insulating film formed between the semiconductor substrate and the gate electrode and on a side surface of the gate electrode; And a thickness of an insulating region including a gate insulating film near a lower end portion of the gate electrode, wherein a thickness of a gate insulating film at a lower center of the gate electrode is provided. A semiconductor device that is thicker. 7. A semiconductor substrate, a first insulating film selectively formed on the semiconductor substrate, and a gate selectively formed on the semiconductor substrate on which the first insulating film is not formed. An insulating film, a gate electrode formed on the gate insulating film, a second insulating film formed on a side surface of the gate electrode, and a second insulating film formed on a side surface of the gate electrode. A gate insulating film, comprising: a formed sidewall insulating film; and an interlayer insulating film formed around a gate electrode on which the second insulating film and the sidewall insulating film are formed. The gate insulating film and the second insulating film The total thickness of
A semiconductor device having a thickness greater than a thickness of the first insulating film. 8. A semiconductor substrate, a first insulating film selectively formed on the semiconductor substrate, and a gate selectively formed on the semiconductor substrate on which the first insulating film is not formed. An insulating film, a gate electrode formed on the gate insulating film, a second insulating film formed on a side surface of the gate electrode, and a second insulating film formed on a side surface of the gate electrode. A gate insulating film, comprising: a formed sidewall insulating film; and an interlayer insulating film formed around a gate electrode on which the second insulating film and the sidewall insulating film are formed. The gate insulating film and the second insulating film The total thickness of
A semiconductor device having a distance greater than a distance between a lower end of the sidewall insulating film on the gate electrode side and the semiconductor substrate.