JP3937894B2 - Semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device, and more particularly to a trench gate type semiconductor device in which a buried gate electrode is provided in a trench on a substrate surface.
[0002]
[Prior art]
In recent years, with the demand for higher integration and higher functionality of semiconductor devices, element structures have been miniaturized. Under such circumstances, in a semiconductor device (a so-called MOS transistor transistor) in which a buried gate electrode is provided on a semiconductor substrate via a gate insulating film, a short channel effect (for example, a punch-through phenomenon) that becomes conspicuous by miniaturization, Limitation by increasing the impurity concentration or reducing the thickness of the gate insulating film has become a limit.
[0003]
Therefore, as disclosed in Japanese Patent Laid-Open No. 7-38095, a semiconductor device having a trench gate type in which a buried gate electrode is buried in a trench formed in a surface layer of a substrate has been proposed. In the trench gate type semiconductor device, as shown in FIG. 5, the inner wall of the trench 3 a formed in the surface layer of the substrate 3 is covered with the gate insulating film 5, and the trench 3 a is buried via the gate insulating film 5. A buried gate electrode 7 is provided. The buried gate electrode 7 is buried at a position lower than the surface of the substrate 3, and source / drain diffusion layers (S / D layers) 9a, 9b are provided on the surface layer of the substrate 3 on both sides of the groove 3a. It has been.
[0004]
Further, an insulating side wall 11 made of silicon oxide or silicon nitride is provided on the inner wall of the groove 3a on the embedded gate electrode 7, and the side wall 11 is sufficient for the S / D layers 9a and 9b. A silicide layer 13 is provided on the surface of the buried gate electrode 7 while being insulated from each other.
[0005]
In the semiconductor device 1 having such a configuration, the S / D layers 9a and 9b are formed shallower than the depth H of the groove 3a while the line width Lg of the buried gate electrode 7 is reduced. The distance between the layer 9a and the S / D layer 9b, that is, the channel length La can be ensured. Therefore, it is possible to reduce the element structure while maintaining a stable threshold voltage while suppressing the short channel effect due to the extension of the depletion layer from the S / D layers 9a and 9b. For this reason, it is effectively used as a circuit element requiring miniaturization, such as a cell transistor of a DRAM.
[0006]
[Problems to be solved by the invention]
However, when the above-described trench gate type semiconductor device is used as a DRAM cell transistor, the following problems arise. That is, since the DRAM cell transistor is required to have charge retention characteristics, the concentration of impurities (for example, P) in the S / D layer is reduced to reduce the electric field between the S / D layer and the channel region. It is necessary to keep it down. However, when the impurity concentration of the S / D layer is suppressed to a low concentration, the parasitic resistance of the S / D layer is increased, which causes a problem that current drive capability cannot be obtained. Therefore, when the trench gate type semiconductor device having the above structure is used as a cell transistor of a DRAM, a reduction in yield due to a write failure is caused if an attempt is made to secure charge retention characteristics.
[0007]
Therefore, the present invention can be suitably used as a circuit element that requires charge retention characteristics, such as a cell transistor of a DRAM, by improving the current driving capability without increasing the impurity concentration of the S / D layer. An object is to provide a trench gate type semiconductor device.
[0008]
[Means for Solving the Problems]
In order to achieve such an object, a semiconductor device of the present invention includes a gate insulating film that covers an inner wall of a groove formed in a surface layer of a substrate. In the trench covered with the gate insulating film, a buried gate electrode is provided at a height lower than the upper surface of the substrate. Further, a source / drain diffusion layer shallower than the groove is provided on the surface layer of the substrate on both sides of the groove. In particular, an insulating film made of a material having a dielectric constant higher than that of silicon nitride is provided on the buried gate electrode in a state facing the source / drain diffusion layer through the gate insulating film. It is characterized by.
[0009]
In the semiconductor device having such a configuration, when a voltage is applied to the buried gate electrode, the dielectric polarization of the insulating film made of a material having a dielectric constant higher than that of silicon nitride provided on the buried gate electrode. The carrier concentration at the interface portion of the source / drain diffusion layer at the position facing the insulating film is sufficiently increased, and the resistance at the groove side interface of the source / drain diffusion layer is reduced. Therefore, if the impurity concentration of the source / drain diffusion layer is approximately the same, the current driving capability can be improved as compared with the case where silicon nitride or silicon oxide is used for this insulating film.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of a semiconductor device of the present invention will be described in detail with reference to the drawings.
[0011]
FIG. 1 is a cross-sectional view illustrating a configuration of a semiconductor device according to an embodiment. The difference between the semiconductor device 100 shown in this figure and the conventional semiconductor device described with reference to FIG. 5 is that the sidewall 101 covering the sidewall of the groove 3a above the embedded gate electrode 7 has a dielectric constant higher than that of silicon nitride. This is because it is made of a highly insulating material.
[0012]
As such an insulating material, a metal oxide film can be used. Specifically, oxides such as Al, Ti, Ta, Zr, Hf, In, Sr, Pb, Ba, Pa, and the like can be used. Oxide mixed crystals are used. Of these, in particular, HfO _{2 ,} Ta ₂ O ₅ , Al ₂ O ₃ , ZrO _2, etc., as well as PZT [Pb (Zr, Ti) O ₃ ], BST [mixed crystal of BaTiO ₃ and SrTiO ₃ ] are used. be able to.
[0013]
Hereinafter, a more detailed configuration of the semiconductor device 100 will be described with reference to FIG.
[0014]
First, as shown in FIG. 2A, an insulating protective film 4 such as silicon oxide is formed on a substrate 3 made of, for example, p-type single crystal silicon. Then, a groove 3 a is formed in the substrate 3 by pattern etching the substrate 3 from above the protective film 4. The groove 3 a is formed with a predetermined depth H with respect to the surface of the substrate 3. Thereafter, an impurity for adjusting the threshold voltage is introduced into the inner wall of the groove 3a as necessary by ion implantation.
[0015]
Next, the gate insulating film 5 made of silicon oxide is formed on the surface of the substrate 3 including the inner wall of the groove 3a by, for example, thermal oxidation. Thereafter, a buried gate electrode 7 is formed by embedding a gate material in the groove 3 a covered with the gate insulating film 5 so as to be lower than the surface of the substrate 3. In the case of forming the buried gate electrode 7, for example, a polysilicon film is formed on the substrate 3 in a state in which the trench 3a is buried, and the polysilicon film is etched back so that the polysilicon is formed only in the trench 3a. It is obtained by leaving the silicon film.
[0016]
Next, as shown in FIG. 2B, impurities are introduced into the surface layer of the substrate 3 and the buried gate electrode 7 by ion implantation to form S / D layers 9a and 9b in the surface layer of the substrate 3. At the same time, the conductivity of the buried gate electrode 7 is ensured. At this time, for example, the S / D layers 9 a and 9 b are shallower than the depth H of the groove 3 a and have a predetermined depth with respect to the height of the buried gate electrode 7. It is important to set the implantation energy for ion implantation so as to have a predetermined overlap S in the vertical direction. Here, an n-type impurity such as P (phosphorus) is introduced into the p-type substrate 3. In addition, when the semiconductor device 100 formed here is used as a circuit element that requires charge retention characteristics such as a DRAM cell transistor, the impurity concentration of the S / D layers 9a and 9b can be kept as low as possible. And
[0017]
Next, as shown in FIG. 2 (3), the sidewall of the trench 3a above the buried gate electrode 7 is made of an insulating material made of a material having a dielectric constant higher than that of silicon nitride, which is a feature of the present invention. Sidewall 101 is formed. In the case of forming the sidewall 101, first, a material film (for example, a metal oxide film) of the insulating material described above is formed by a MOCVD (metal organic-chemical vapor deposition) method, a plasma CVD method, a sputtering method, or the like. The film is formed so that the groove 3a is completely filled by the film method. Thereafter, the entire material film is etched back to leave the material film only on the inner wall of the groove 3a, thereby forming the sidewall 101. The sidewall 101 only needs to have a height that covers the side wall of the groove 3a formed in the substrate 3a, and has a height that also covers the side wall of the protective film 4 on the substrate 3 as shown in the figure. It's okay.
[0018]
Thereafter, the surface layer of the buried gate electrode 7 exposed from the sidewall 101 is silicided to form the low resistance layer 13. In the case of forming the low resistance layer 13, first, a metal film (for example, a refractory metal such as Co, Ni, Ti, Pt or the like) is formed so as to cover the sidewalls 101 and the inner walls of the grooves 3 a. Next, a silicidation reaction is advanced at the interface between the buried gate electrode 7 and the metal film by performing heat treatment. As a result, the low resistance layer 13 made of metal silicide insulated from the S / D layers 9 a and 9 b by the sidewall 101 is formed on the surface layer of the buried gate electrode 7 in a self-aligned manner. And after this silicidation reaction, the process of removing the unreacted part of a metal film is performed.
[0019]
After the above, as shown in FIG. 1, the insulating stopper layer 15 is formed so as to cover the low resistance layer 13 and the sidewall 101. The stopper layer 15 is a film that serves as an etching stopper in the etching in the case where the connection hole is formed in the subsequent process, and is formed of, for example, silicon nitride. Thereafter, a planarization insulating film 17 made of, for example, silicon oxide is formed on the stopper layer 15, and the planarization insulating film 17, the stopper layer 15, and the protective film 4 are sequentially subjected to pattern etching, whereby the S / D layer 9b. Is formed. In this pattern etching, the stopper layer 15 stops etching at one end to prevent the S / D layer 9b from being etched excessively. Thereafter, the plug 21 reaching the S / D layer 9 b is embedded in the connection hole 19. When the semiconductor device 100 is provided as a DRAM cell transistor, the plug serves as a bit contact.
[0020]
In the semiconductor device 100 having the configuration obtained according to the manufacturing procedure as described above, the sidewall 101 that covers the sidewall of the groove 3a above the embedded gate electrode 7 is made of a material having a dielectric constant higher than that of silicon nitride. . Therefore, when a gate voltage is applied to the buried gate electrode 7, the carrier concentration at the interface portion between the S / D layers 9 a and 9 b at the position facing the sidewall 101 is sufficiently increased due to the dielectric polarization of the sidewall 101. Can be increased. That is, by effectively using the fringe electric field when the gate voltage is applied, the resistance at the groove side interface of the S / D layers 9a and 9b can be reduced, and the current driving capability can be improved. .
[0021]
Furthermore, since the current drive capability can be improved without reducing the gate length, that is, in a state in which the threshold voltage is secured and the short channel effect is suppressed, it becomes possible to secure an operation margin of the semiconductor device, It becomes possible to further reduce the size of the device structure by reducing the gate width.
[0022]
Since the current drive capability can be improved without increasing the impurity concentration of the S / D layers 9a and 9b, that is, while maintaining the charge retention characteristic, the semiconductor device 100 is used as a cell transistor of a DRAM, for example. If there is, it becomes possible to suppress defective writing. In addition, if the current driving capability is made constant, the impurity concentration of the S / D layers 9a and 9b can be lowered, so that the charge retention characteristics can be improved. Therefore, a trench gate type semiconductor device can be suitably used as a circuit element such as a DRAM cell transistor.
[0023]
FIG. 3 shows a simulation result of the current driving capability with respect to the dielectric constant of the sidewall. FIG. 4 shows the simulation result of the threshold voltage with respect to the dielectric constant of the sidewall. In each simulation, the design value of each structural part was set as follows.
Gate length Lg: 0.14 μm
Gate oxide film thickness: 5 nm
P-type impurity concentration of substrate: 5 × 10 ¹⁶ / cm ³
N-type impurity (P) concentration in the S / D layer: 10 ¹⁸ / cm ³
[0024]
From these simulation results, compared to the case where silicon oxide (SiO ₂ : dielectric constant 3.9) or silicon nitride (Si ₃ N ₄ : dielectric constant 7) is used for the sidewall, By using a material having a dielectric constant higher than that of silicon nitride such as hafnium oxide (HfO ₂ : dielectric constant 25) and tantalum oxide (Ta ₂ O ₅ : dielectric constant 30), the current can be changed without changing the threshold voltage. It can be seen that the driving ability is improved. Specifically, by changing the sidewall from silicon oxide to hafnium oxide (HfO ₂ ), the current driving capability can be increased by 3%.
[0025]
In the above-described embodiment, the side wall 101 is provided on the side wall of the groove 3a above the buried gate electrode 7, and the side wall 101 is made of a material having a dielectric constant higher than that of silicon nitride. However, the present invention is not limited to such a configuration. For example, when an insulating film is embedded without forming a sidewall in the groove 3a above the embedded gate electrode 7, the insulating film portion embedded in the groove 3a is made of a material having a dielectric constant higher than that of silicon nitride. It is good also as a structure. In such a configuration, an insulating film portion having a dielectric constant higher than that of silicon nitride is disposed on the side wall portion of the groove 3a in which the S / D layers 9a and 9b are disposed via the gate insulating film 5. The same effects as those of the above-described embodiment can be obtained. However, such an insulating film is preferably arranged at a position close to the S / D layers 9a and 9b via the gate insulating film 5, and a higher effect can be obtained.
[0026]
The present invention can be widely applied to semiconductor devices having a trench gate structure. For example, the structure of the groove is not limited to the configuration having corners at the bottom as shown in the figure, and the same effect can be obtained even with a configuration having a curved bottom without corners.
[0027]
【The invention's effect】
As described above, according to the trench gate type semiconductor device of the present invention, the dielectric constant is higher than that of silicon nitride in the state where the trench sidewall on the buried gate electrode is opposed to the S / D through the gate insulating film. By providing an insulating film made of a material with a high resistance, when a gate voltage is applied to the buried gate electrode, the carrier concentration at the interface portion of the S / D layer is sufficiently increased by the dielectric polarization of the insulating film to reduce the resistance. Can be achieved. Therefore, the current driving capability can be improved without increasing the gate length and the impurity concentration of the S / D layer, that is, while ensuring the threshold voltage and the charge retention characteristics. As a result, the trench gate type semiconductor device can be used as a fine element such as a DRAM that requires charge retention characteristics.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view illustrating a structural example of a semiconductor device of the present invention.
2 is a cross-sectional process diagram illustrating a method of manufacturing the semiconductor device of FIG. 1; FIG.
FIG. 3 is a diagram illustrating a simulation result of current drive capability with respect to a dielectric constant of a sidewall in a semiconductor device.
FIG. 4 is a diagram illustrating a simulation result of a threshold voltage with respect to a dielectric constant of a sidewall in a semiconductor device.
FIG. 5 is a cross-sectional view showing a configuration of a conventional trench gate type semiconductor device.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 100 ... Semiconductor device, 3 ... Substrate, 3a ... Groove, 5 ... Gate insulating film, 7 ... Embedded gate electrode, 9a, 9b ... S / D layer (source / drain diffusion layer), 13 ... Low resistance layer, 101 ... Sidewall (insulating film)

Claims (2)

A gate insulating film covering an inner wall of the groove formed in the surface layer of the substrate; a buried gate electrode embedded in the groove covered with the gate insulating film at a height lower than the upper surface of the substrate; and the groove A source / drain diffusion layer shallower than the groove provided in the surface layer of the substrate on both sides of the substrate,
An insulating film made of a material having a dielectric constant higher than that of silicon nitride is provided on the buried gate electrode in a state facing the source / drain diffusion layer through the gate insulating film. A semiconductor device characterized by the above. The semiconductor device according to claim 1,
The insulating film is provided as a sidewall covering the sidewall of the groove;
A semiconductor device characterized in that a low resistance layer is formed on a surface layer of the buried gate electrode exposed from the sidewall.

Images