JP2003298048A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a groove gate type semiconductor device, in which current drive capability is improved without increasing the impurity concentration of an S/D layer. <P>SOLUTION: A semiconductor device 100 comprises a gate insulation film 5 covering an inner wall of a groove 3a formed in a surface layer of a substrate 3, an embedded gate electrode 7 embedded in the groove 3a covered with the gate insulation film 5 at a level which is lower than the top surface of the substrate, and S/D layers (source/drain diffusion layers) 9a and 9b, that are provided on the surface layer of the substrate 3 on both sides of the groove 3a and shallower than the groove 3a. In a state of facing the semiconductor device 100, and insulation film (sidewall 101) constituting a material of a dielectric constant higher than that of silicon nitride is provided on the embedded gate electrode 7 while facing the S/D layers 9a and 9b with the gate insulation film 5 in between. On the surface layer of the embedded gate electrode 7 exposed from the side wall 101, a resistance lowering layer 13 is formed. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a trench gate type semiconductor device in which a buried gate electrode is provided in a trench on the surface of a substrate.

[0002]

2. Description of the Related Art In recent years, with the demand for higher integration and higher functionality of semiconductor devices, the miniaturization of element structures has been advanced. In such a situation, in a semiconductor device (so-called MOS transistor transistor) in which a buried gate electrode is provided on a semiconductor substrate via a gate insulating film, a short channel effect (for example, punch through phenomenon) which becomes remarkable due to miniaturization is Suppression is becoming the limit due to the increase of the impurity concentration and the thinning of the gate insulating film.

Therefore, as disclosed in Japanese Patent Laid-Open No. 7-38095, there is proposed a semiconductor device having a trench gate type in which a buried gate electrode is buried in a trench formed in a surface layer of a substrate. In the trench gate type semiconductor device, as shown in FIG. 5, the inner wall of the trench 3a formed in the surface layer of the substrate 3 is covered with the gate insulating film 5, and the trench 3a is buried via the gate insulating film 5. Embedded gate electrode 7 is provided. The buried gate electrode 7 is buried in a position lower than the surface of the substrate 3, and source / drain diffusion layers (S / D layers) 9a and 9b are provided on the surface layers of the substrate 3 on both sides of the groove 3a. Has been.

An insulating side wall 11 made of silicon oxide or silicon nitride is provided on the inner wall of the groove 3a on the buried gate electrode 7, and the side wall 11 is formed.
Of the silicide layer 13 on the surface of the buried gate electrode 7 while being sufficiently insulated from the S / D layers 9a and 9b.
Is provided.

In the semiconductor device 1 having such a structure, the line width Lg of the buried gate electrode 7 is made finer and S
By forming the / D layers 9a and 9b shallower than the depth H of the groove 3a, the distance between the S / D layer 9a and the S / D layer 9b, that is, the channel length La can be secured. For this reason, it is possible to suppress the short channel effect due to the extension of the depletion layer from the S / D layers 9a and 9b, maintain a stable threshold voltage, and miniaturize the element structure. Therefore, D
It is effectively used as a circuit element that requires miniaturization, such as a cell transistor of RAM.

[0006]

However, when the groove gate type semiconductor device described above is used as a cell transistor of a DRAM, the following problems occur. That is, since the DRAM cell transistor is required to have charge retention characteristics, the concentration of impurities (for example, P) in the S / D layer should be low to reduce the electric field between the S / D layer and the channel region. Need to be kept to. However, when the impurity concentration of the S / D layer is suppressed to a low concentration, the parasitic resistance of the S / D layer becomes large, which causes a problem that the current driving capability cannot be obtained. Therefore, when the groove gate type semiconductor device having the above structure is used as a cell transistor of a DRAM, an attempt to secure charge retention characteristics causes a decrease in yield due to a write error.

Therefore, the present invention improves the current drive capability without increasing the impurity concentration of the S / D layer, and
It is an object of the present invention to provide a groove gate type semiconductor device which can be suitably used as a circuit element such as a cell transistor of a RAM which is required to retain electric charges.

[0008]

A semiconductor device of the present invention for achieving the above object comprises a gate insulating film for covering an inner wall of a groove formed in a surface layer of a substrate. Then, in the groove covered with the gate insulating film, a buried gate electrode is provided at a height lower than that of the upper surface of the substrate. Also,
Source / drain diffusion layers shallower than the groove are provided on the surface layer of the substrate on both sides of the groove. And, in particular, the source / source is formed above the buried gate electrode via the gate insulating film.
It is characterized in that an insulating film made of a material having a higher dielectric constant than silicon nitride is provided in a state of being opposed to the drain diffusion layer.

In the semiconductor device having such a structure, when a voltage is applied to the buried gate electrode, an insulating film made of a material having a higher dielectric constant than silicon nitride provided on the buried gate electrode is formed. Due to the dielectric polarization, the carrier concentration of the interface portion of the source / drain diffusion layer at the position facing the insulating film is sufficiently increased, and the resistance of the groove-side interface of the source / drain diffusion layer is reduced. Therefore, if the impurity concentration of the source / drain diffusion layers is about the same, compared to the case of using silicon nitride or silicon oxide for this insulating film,
The current drive capability can be improved.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a semiconductor device of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a sectional view showing the structure of the semiconductor device of the embodiment. The difference between the semiconductor device 100 shown in this figure and the conventional semiconductor device described with reference to FIG. 5 is that the side wall 101 covering the side wall of the groove 3a above the buried gate electrode 7 has a dielectric constant higher than that of silicon nitride. It is composed of a highly insulating material.

As such an insulating material, a metal oxide film can be used. Specifically, Al, Ti,
Oxides such as Ta, Zr, Hf, In, Sr, Pb, Ba and Pa, and mixed crystals of these oxides are used. Among these, especially, HfO _2, Ta ₂ O ₅ , Al ₂ O ₃ and ZrO
_2nd grade, PZT [Pb (Zr, Ti) O ₃ ], BS
T [mixed crystal of BaTiO ₃ and SrTiO ₃ ] can be used.

A more detailed structure of the semiconductor device 100 will be described below with reference to FIG. 2 together with its manufacturing procedure.

First, as shown in FIG. 2A, for example, p
An insulative protective film 4 such as silicon oxide is formed on a substrate 3 made of mold single crystal silicon. Then, the substrate 3 is pattern-etched from above the protective film 4 to form the groove 3 a in the substrate 3. The groove 3a is formed with a predetermined depth H on the surface of the substrate 3.
After that, an impurity for adjusting the threshold voltage is introduced into the inner wall of the groove 3a by ion implantation, if necessary.

Next, a gate insulating film 5 made of silicon oxide is formed on the surface of the substrate 3 including the inner wall of the groove 3a by, for example, thermal oxidation. Then, in the groove 3a covered with the gate insulating film 5, a buried gate electrode 7 is formed by burying a gate material so as to have a height lower than that of the surface of the substrate 3. When forming the buried gate electrode 7, for example, a polysilicon film is formed on the substrate 3 in a state of filling the groove 3a, and the polysilicon film is etched back to form a polysilicon film only in the groove 3a. Obtained by leaving a silicon film.

Next, as shown in FIG. 2 (2), impurities are introduced into the surface layer of the substrate 3 and the buried gate electrode 7 by ion implantation, and the S / D layers 9 a and 9 b are introduced into the surface layer of the substrate 3.
And the conductivity of the buried gate electrode 7 is secured. At this time, for example, the S / D layers 9a and 9b are shallower than the depth H of the groove 3a and have a predetermined depth with respect to the height of the embedded gate electrode 7, and the height is higher than that of the embedded gate electrode 7, for example. It is important to set the implantation energy of ion implantation so as to have a predetermined overlap S in the depth direction. In addition, here
An n-type impurity such as P (phosphorus) is introduced into the p-type substrate 3. Further, when the semiconductor device 100 formed here is used as a circuit element such as a cell transistor of a DRAM that requires charge retention characteristics, the impurity concentration of the S / D layers 9a and 9b should be suppressed as low as possible. And

Next, as shown in FIG. 2C, the insulating property of the material having a higher dielectric constant than silicon nitride, which is a feature of the present invention, is formed on the sidewall of the groove 3a above the buried gate electrode 7. A sidewall 101 made of a material is formed.
When forming the sidewall 101, first,
A material film (for example, a metal oxide film) of the insulating material described above is
MOCVD (metal organic-chemical vapor depositio
n) method, plasma CVD method, or sputtering method is used to form a film in a state where the groove 3a is completely filled. Then, the material film is etched back over the entire surface to leave the material film only on the inner walls of the trenches 3a and form the sidewalls 101. The side wall 101 has only to have a height that covers the side wall of the groove 3a formed in the substrate 3a, and has a height that also covers the side wall of the protective film 4 on the substrate 3 as illustrated. You can

After the above, the surface layer of the buried gate electrode 7 exposed from the sidewall 101 is silicidized to form the low resistance layer 13. When forming the low resistance layer 13, first, the sidewall 101 and the groove 3 are formed.
While covering the inner wall of a, a metal film (for example, Co, Ni, T
i, a refractory metal such as Pt) is deposited. Next, heat treatment is performed to advance the silicidation reaction at the interface between the buried gate electrode 7 and the metal film. As a result, the resistance lowering layer 13 made of metal silicide, which is insulated from the S / D layers 9a and 9b by the sidewall 101, is formed in a self-aligned manner on the surface layer of the buried gate electrode 7. Then, after the silicidation reaction, a step of removing the unreacted portion of the metal film is performed.

After the above, as shown in FIG. 1, an insulating stopper layer 15 is formed in a state of covering the low resistance layer 13 and the side wall 101. This stopper layer 15
Is a film that serves as an etching stopper in the etching for forming the connection hole in the subsequent steps, and is formed of, for example, silicon nitride. After that, a flattening insulating film 17 made of, for example, silicon oxide is formed on the stopper layer 15, and the flattening insulating film 17, the stopper layer 15, and the protective film 4 are sequentially pattern-etched, whereby the S / D layer 9 is formed.
A connection hole 19 reaching b is formed. In this pattern etching, the S / D layer 9b is prevented from being excessively etched by stopping the etching once with the stopper layer 15. Then, in this connection hole 19, S /
The plug 21 reaching the D layer 9b is embedded. When the semiconductor device 100 is provided as a cell transistor of DRAM, this plug serves as a bit contact.

In the semiconductor device 100 having the structure obtained according to the manufacturing procedure as described above, the side wall 101 covering the side wall of the groove 3a above the buried gate electrode 7 is made of a material having a higher dielectric constant than silicon nitride. Has been done. Therefore, when a gate voltage is applied to the buried gate electrode 7, the S / D layers 9a and 9a at the positions facing the sidewall 101 due to the dielectric polarization of the sidewall 101.
The carrier concentration in the interface portion of b can be sufficiently increased. That is, by effectively utilizing the fringe electric field when the gate voltage is applied, the resistance of the groove-side interface of the S / D layers 9a and 9b can be reduced, and the current driving capability can be improved. .

Further, without shortening the gate length,
That is, since the current driving capability can be improved in the state where the threshold voltage is secured and the short channel effect is suppressed, it is possible to secure the operation margin of the semiconductor device and reduce the gate width to further increase the device structure. It also becomes possible to miniaturize.

Since the current driving capability can be improved without increasing the impurity concentration of the S / D layers 9a and 9b, that is, in the state where the charge retention characteristics are secured, this semiconductor device is used as a cell transistor of a DRAM, for example. 10
When 0 is used, it becomes possible to suppress writing defects. Moreover, if the current drive capacity is constant, S / D
Since the impurity concentration of the layers 9a and 9b can be reduced, it is possible to improve the charge retention characteristics. Therefore, a groove gate type semiconductor device can be preferably used as a circuit element such as a cell transistor of a DRAM.

FIG. 3 shows a simulation result of the current driving ability with respect to the dielectric constant of the sidewall. Also,
FIG. 4 shows the simulation result of the threshold voltage with respect to the sidewall dielectric constant. In each simulation, the design value of each structural portion was set as follows. Gate length Lg: 0.14 μm Gate oxide film thickness: 5 nm Substrate p-type impurity concentration: 5 × 10 ¹⁶ / cm ³ S / D layer n-type impurity (P) concentration: 10 ¹⁸ / cm ³

From the results of these simulations, it was found that the sidewalls were made of silicon oxide (SiO ₂ : dielectric constant 3.
9) or silicon nitride (Si ₃ N ₄ : dielectric constant 7) is used, hafnium oxide (HfO ₂ : dielectric constant 25) or tantalum oxide (Ta) as in the above embodiment is used.
It can be seen that by using a material having a higher dielectric constant than silicon nitride such as ₂ O ₅ : dielectric constant 30), the current driving capability can be improved without changing the threshold voltage. Specifically, the current driving capability can be increased by 3% by changing the sidewall from silicon oxide to hafnium oxide (HfO ₂ ).

In the above-described embodiment, the sidewall 101 is provided on the sidewall of the groove 3a above the buried gate electrode 7, and the sidewall 101 is made of a material having a higher dielectric constant than silicon nitride. did.
However, the present invention is not limited to such a configuration. For example, when the insulating film is buried in the trench 3a above the buried gate electrode 7 without forming a sidewall,
The insulating film portion embedded in the groove 3a may be made of a material having a higher dielectric constant than silicon nitride. In such a configuration, the insulating film portion having a higher dielectric constant than silicon nitride is arranged via the gate insulating film 5 on the side wall portion of the groove 3a in which the S / D layers 9a and 9b are arranged. The same effects as those of the above-described embodiment can be obtained. However, such an insulating film is preferably arranged at a position close to the S / D layers 9a and 9b with the gate insulating film 5 interposed therebetween, and a higher effect can be obtained.

Further, the present invention is widely applicable to semiconductor devices having a trench gate structure. For example, the structure of the groove is not limited to the configuration having the corner portion at the bottom as illustrated, and the same effect can be obtained even if the configuration has the curved bottom portion without the corner portion.

[0027]

As described above, according to the trench gate type semiconductor device of the present invention, the trench side wall on the buried gate electrode is
By providing an insulating film made of a material having a higher dielectric constant than silicon nitride in a state of facing the S / D via the gate insulating film, the insulating film can be formed when a gate voltage is applied to the embedded gate electrode. It is possible to sufficiently increase the carrier concentration in the interface portion of the S / D layer and reduce the resistance by the dielectric polarization. Therefore, the current driving capability can be improved without increasing the gate length and the impurity concentration of the S / D layer, that is, while ensuring the threshold voltage and charge retention characteristics. As a result, the trench gate type semiconductor device is
It can be used as an element such as AM that requires a fine and charge retention characteristic.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a configuration example of a semiconductor device of the present invention.

2A to 2D are cross-sectional process diagrams showing a method of manufacturing the semiconductor device of FIG.

FIG. 3 is a diagram showing a simulation result of a current driving capability with respect to a sidewall dielectric constant in a semiconductor device.

FIG. 4 is a diagram showing a simulation result of a threshold voltage with respect to a sidewall dielectric constant in a semiconductor device.

FIG. 5 is a cross-sectional view showing a configuration of a conventional trench gate type semiconductor device.

[Description of Reference Signs] 100 ... Semiconductor device, 3 ... Substrate, 3a ... Trench, 5 ... Gate insulating film, 7 ... Buried gate electrode, 9a, 9b ... S / D layer (source / drain diffusion layer), 13 ... Low Resistance layer, 10
1 ... Sidewall (insulating film)

   ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 5F083 AD04 JA02 JA06 JA14 JA15                       JA35 JA39 MA06 MA20                 5F140 AA05 AA10 AA21 AC32 BA01                       BB03 BB04 BB06 BC06 BE03                       BE07 BF04 BF11 BF18 BF43                       BG36 BG44 BJ08 BJ11 BJ27                       BK34 CC03 CE02 CE20 CF04                       CF07 DB07

Claims (2)

[Claims] 1. A gate insulating film covering an inner wall of a groove formed in a surface layer of a substrate, and a buried gate embedded in the groove covered with the gate insulating film at a height lower than an upper surface of the substrate. In a semiconductor device comprising an electrode and a source / drain diffusion layer provided on the surface layer of the substrate on both sides of the groove, the source / drain diffusion layer being shallower than the groove, the buried gate electrode is provided with the gate insulating film interposed therebetween. And a source / drain diffusion layer facing each other, an insulating film made of a material having a higher dielectric constant than silicon nitride is provided. 2. The semiconductor device according to claim 1, wherein the insulating film is provided as a sidewall that covers a sidewall of the trench, and a surface layer of the buried gate electrode exposed from the sidewall has a low resistance. A semiconductor device having a resistance layer.