KR20080069037A - Method of fabricating semiconductor device having metallic gate on a active fins and semiconductor device fabricated thereby - Google Patents

Abstract

A semiconductor device with a metal gate formed on active fins and a method for manufacturing the same are provided to form a metal gate pattern without voids by reducing an aspect ratio of a gap between active fins. A method for manufacturing a semiconductor device includes: forming active fins(104) on a semiconductor substrate(100) extending in a cross direction; forming a silicon pattern(132) in a lower region of a gap between the active fins; forming a metal layer(134) on the semiconductor substrate having a silicon pattern; patterning the metal pattern to form a metal gate pattern intersecting lower surfaces of the active fins on a upper region of the gap; and patterning the silicon pattern to form a silicon gate pattern on a lower region of the gate overlapping with the metal gate pattern.

Description

A method of manufacturing a semiconductor device having a metal gate on the active fins and a semiconductor device manufactured thereby

1A is a plan view of a conventional flash memory cell.

1B and 1C are cross-sectional views taken along lines II ′ and II-II ′ of FIG. 1A, respectively.

2 is a plan view of a flash memory cell according to an embodiment of the present invention.

3A through 5A are cross-sectional views taken along the line III-III ′ of FIG. 2.

3B to 5B are cross-sectional views taken along the line IV-IV ′ of FIG. 2.

6 is a plan view of a flash memory cell according to another exemplary embodiment of the present invention.

7A and 8A are cross-sectional views taken along the line VV ′ of FIG. 6.

7B and 8B are cross-sectional views taken along the line VI-VI ′ of FIG. 6.

The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device manufactured thereby, and more particularly, to a semiconductor device having a metal gate on the active fins and a semiconductor device manufactured thereby.

Recently, a semiconductor device has a design rule of sub-micron or less and can replace a conventional planar transistor in order to improve electrical characteristics. A fin-FET having gates on both sides of the channel can be effectively controlled. ) Structure has been proposed. The finpet structure effectively improves the current drive capability while using existing semiconductor process technology. In a semiconductor device in which fin fin structures are arranged with regularity, such as a cell region of a semiconductor memory device, the fin-pet structures are insulated by a device isolation film formed by using a trench isolation technique. It can be formed in the active fins. The finFET structure can be applied not only to MOS transistors but also to various semiconductor memory devices, and can be adopted, for example, in flash memory cells.

On the other hand, as semiconductor devices require high integration density per unit area, fast operation speed, and low power consumption, the gate electrode and source / drain junctions of the finpet device are designed to be reduced to the extent possible. . However, various problems are caused by the shrinking of the pinpet element. For example, as the gate electrode shrinks, the electrical resistance of the gate electrode is increased, thereby delaying the transmission speed of the electrical signal applied to the gate electrode. Further, when the polysilicon film is used as the material of the gate electrode, the depletion region is increased in the lower region of the polysilicon gate electrode, that is, the region adjacent to the gate insulating film. This may increase the electrical equivalent thickness of the gate insulating layer, thereby reducing the effective gate voltage of the polysilicon gate electrode. Recently, attempts have been made to use a metal film as a material of the gate electrode to overcome this problem.

1A is a plan view of a conventional flash memory cell. 1B and 1C are cross-sectional views taken along lines II ′ and II-II ′ of FIG. 1A, respectively.

1A to 1C, active fins 14 defined in the semiconductor substrate 10 may be formed by device isolation trenches (not shown). An isolation layer 12 may be formed in the lower region of the isolation trench. As a result, the active fins 14 may have a portion protruding from the device isolation layer 12. The tunnel insulating layer 22 may be formed on the protruding active fins 14.

A charge storage layer and a charge blocking layer may be sequentially stacked on the entire surface of the semiconductor substrate 10 having the active fins 14. The charge storage layer may be formed of a silicon nitride layer, and the charge blocking layer may be formed of a silicon oxide layer. Subsequently, a control gate electrode film is deposited on the charge blocking film using physical vapor deposition (PVD). The control gate electrode film may be formed of a tungsten film. In this case, as in FIG. 1B, the tungsten film has an overhang at the upper edges of the active fins 14. In addition, a thinning phenomenon of thinning of the tungsten film occurs at the lower edge of the gap between the active fins 14. That is, the tungsten film has poor step coverage due to the high aspect ratio of the gap.

Mask patterns (not shown) that cross the active fins 14 are formed on the tungsten film. As a result of etching the tungsten film, the charge blocking film, the charge storage film, and the tunnel insulating film sequentially using the mask patterns as an etching mask, the tunnel insulating film pattern 22, the charge storage pattern 24, and the charge blocking pattern 26 which are sequentially stacked ) And control gate electrodes 30. In this case, as shown in FIG. 1B, the control gate electrode 30 has a thin portion T at a lower edge of the gap overlapping with the control gate electrode 30 due to poor step coverage of the tungsten film. Have As a result, in the subsequent etching process, the thin portion T may be damaged and disconnected. In addition, the mask patterns are spaced apart at predetermined intervals to expose the tungsten film between the mask patterns. However, due to the overhang, the mask patterns remain in the tungsten film formed at the lower edge of the gap between the active fins 14. As a result, when the tungsten film is etched, the tungsten film B under the remaining mask pattern may remain without being etched. Accordingly, the remaining tungsten film B may cause a bridge between the control gate electrodes 30.

An object of the present invention is to provide a method of manufacturing a semiconductor device to form a metal gate pattern by lowering the aspect ratio of the gap between the active fins.

Another object of the present invention is to provide a semiconductor device having a metal gate pattern partially filling a gap between active fins.

According to one aspect of the present invention for achieving the above technical problem, a method for manufacturing a semiconductor device is provided. The method of manufacturing the semiconductor device includes forming active fins extending in one direction on a semiconductor substrate. A silicon pattern is formed in a lower region of the gap between the active fins. A metal film is formed on the semiconductor substrate having the silicon pattern. The metal layer is patterned to form a metal gate pattern crossing the upper surface of the active fins. The metal gate pattern is formed in an upper region of the gap. The silicon pattern is patterned to form a silicon gate pattern. The silicon gate pattern is formed in a lower region of the gap overlapping the metal gate pattern.

In some embodiments of the present invention, the silicon pattern may be formed of a polysilicon film. Forming the silicon pattern may include forming a polysilicon film on an entire surface of the semiconductor substrate having the active fins. An etching gas containing chlorine or hydrogen bromide may be used to etch back the polysilicon layer.

In other embodiments, the metal film may be formed of a tungsten film.

In some embodiments, before forming the silicon pattern, a metal nitride layer may be formed to cover the semiconductor substrate between the active fins along with upper and sidewalls of the active fins. After forming the silicon gate pattern, the metal nitride layer may be etched to form a nitride gate pattern.

In other embodiments, before forming the silicon pattern, a gate insulating layer may be formed to cover upper surfaces and sidewalls of the active fins.

In still other embodiments, before forming the silicon pattern. A first insulating layer may be formed to cover upper surfaces and sidewalls of the active fins. A charge storage layer may be formed on the first insulating layer. A second insulating layer may be formed on the charge storage layer. The charge storage layer may be formed of a silicon nitride layer or a high dielectric layer. In addition, the charge storage layer may be a floating gate layer. The charge storage layer may be formed of a doped polysilicon layer. The first insulating film may be a silicon oxide film, and the second insulating film may be formed of a silicon oxide film, a high dielectric film, or a combination thereof.

According to another aspect of the present invention for achieving the above technical problem, a semiconductor device is provided. The semiconductor device has active fins extending in one direction on a semiconductor substrate. A metal gate pattern is provided across the top surface of the active fins and disposed in an upper region of the gap between the active fins. A silicon gate pattern disposed in a lower region of the gap overlapping the gate patterns is provided.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed subject matter is thorough and complete, and that the scope of the invention to those skilled in the art will fully convey. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Like numbers refer to like elements throughout the specification. Also, an element or layer is referred to as "on" or "on" of another element or layer by interposing another layer or other element in the middle as well as directly above the other element or layer. Include all cases.

First, a method of manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. 2 to 5B. This embodiment is described taking a flash memory device using an insulating film as a charge trap layer as an example. 2 is a plan view of a flash memory cell according to an exemplary embodiment of the present invention, FIGS. 3A to 5A are cross-sectional views taken along line III-III ′ of FIG. 2, and FIGS. 3B to 5B are IVs of FIG. 2. Process cross-sections cut along the line -IV '.

Referring to FIGS. 2, 3A, and 3B, an isolation trench (not shown) may be formed in the semiconductor substrate 100 to define active fins extending in one direction. The device isolation trench may be formed using a known patterning technique. The semiconductor substrate 100 may be a silicon wafer or a silicon on insulator (SOI) wafer.

An insulating layer may be formed to fill the device isolation trench and cover the semiconductor substrate 100. The isolation layer 102 may be formed by recessing the insulating layer to partially fill the isolation trench. That is, the device isolation layer 102 may remain in the lower region of the device isolation trench. Recessing the insulating film may include an etch-back process, a chemical mechanical polishing (CMP) process, or a combination thereof. As a result, the active fins 104 may protrude and be exposed with respect to the device isolation layer 102. The device isolation layer 102 may be formed of an insulating layer such as a silicon oxide layer.

Subsequently, first insulating layers 122 may be formed on the exposed surfaces of the active fins 104. The first insulating layers 122 may be formed along upper surfaces and sidewalls of the active fins 104. As in the present exemplary embodiment, in the case of a flash memory device using an insulating layer as a charge trap layer, the first insulating layers 122 may be adopted as tunnel dielectric layers. The tunnel dielectric layers 122 may be formed of a silicon oxide layer such as a thermal oxide layer. Next, a second insulating layer 124 may be formed on the entire surface of the semiconductor substrate 100 having the tunnel dielectric layers 122. The second insulating layer 124 may be formed to cover the surfaces of the tunnel insulating layers 122 and the upper surface of the device isolation layer 102. In the present embodiment, the second insulating layer 124 may be adopted as a charge storage layer. The charge storage layer 124 may be formed of silicon nitride or high-k dielectrics. The high dielectric layer may be formed of an aluminum oxide layer (AlO), a hafnium oxide layer (HfO), a hafnium aluminum oxide layer (HfAlO), or a combination thereof. For example, the silicon nitride film may be formed using a low pressure chemical vapor deposition (LPCVD) process. Subsequently, a third insulating layer 126 may be formed on the semiconductor substrate 100 having the charge storage layer 124 along the charge storage layer 124. In this embodiment, the third insulating film 126 may be adopted as a charge blocking film. The charge blocking layer 126 may be formed of a silicon oxide layer or a high dielectric layer.

The metal nitride layer 130 may be formed on the entire surface of the semiconductor substrate 100 having the charge blocking layer 126 along the charge blocking layer 126. The metal nitride layer 130 may be formed of a tantalum nitride layer (TaN) or a titanium nitride layer (TiN). The metal nitride film may be formed using a physical vapor deposition (PVD) process.

A silicon film may be formed on the entire surface of the semiconductor substrate 100 having the metal nitride film 130. The silicon layer may be formed to cover top surfaces of the active fins 104. For example, the silicon film may be a polysilicon film, and the polysilicon film may be formed to be doped with N-type impurities. The polysilicon film may be formed using a low pressure chemical vapor deposition (LPCVD) process. In addition, after the N-type impurity is injected in-situ or the polysilicon film is formed during the deposition process, the N-type impurity may be injected into the polysilicon film. In this embodiment, the polysilicon film has a good filling ability (gap) can be formed without a void (void). Subsequently, the polysilicon layer is recessed to form silicon patterns 132 that fill the lower regions of the gaps between the active fins 104, as shown in FIGS. 3A and 3B. The silicon patterns 132 may be formed in a direction parallel to the active fins 104. The recess process for the silicon layer may use an etchback process, and the etchback process may be performed by dry etching using an etching gas containing chlorine or hydrogen bromide (HBr).

2, 4A, and 4B, a metal film 134 is formed on the entire surface of the semiconductor substrate 100 having the silicon patterns 132. In detail, the metal layer 134 may be formed to cover an upper surface of the metal nitride layer 130 and an upper region of a gap between the active fins 104. The metal film 134 may be formed of a tungsten film. The tungsten film may be formed using a physical vapor deposition process. The silicon patterns 132 may be formed to have an appropriate range of heights so that the tungsten layer may fill the upper region of the gap. That is, the aspect ratio of the gap is reduced due to the presence of the silicon patterns 132 so that the tungsten film may fill the upper region of the gap. Meanwhile, the metal nitride film 130 interposed between the metal film 134 and the charge storage film 124 is formed to form the metal film at the interface between the metal film 134 and the charge storage film 124. It is possible to prevent the oxidation of the 134 and to prevent the deterioration of the charge storage layer 124 caused by this.

A mask pattern 140 may be formed on the metal layer 134 to cross the active fins 104. The mask pattern 140 may be formed of a silicon nitride layer.

2, 5A, and 5B, the metal layer 134, the silicon patterns 132, and the metal nitride layer 130 are sequentially etched using the mask pattern 140 as an etch mask. When the silicon patterns 132 are polysilicon layers, the polysilicon layers may be etched using an etching gas containing chlorine or hydrogen bromide. As a result, the metal gate pattern 134a crossing the upper surfaces of the active fins 104 and filling the upper region of the gap, and the silicon gate patterns filling the lower region of the gap overlapping the metal gate pattern 134a ( 132a) is formed. In addition, a nitride film gate pattern 130a may be formed between the metal gate pattern 134a and the upper portions of the active fins 104 along the extending direction of the metal gate pattern 134a. The nitride gate pattern 130a may extend to the lower portion of the silicon gate patterns 132a to be interposed between the silicon gate patterns 132a and the lower portion of the active fins 104. That is, gate patterns including the metal gate pattern 134a, the silicon gate patterns 132a, and the nitride film gate pattern 130a may be formed. In the present embodiment, the gate patterns may be adopted as the transfer gate electrode 136. In another embodiment, when a semiconductor device having a finFET structure is used as a metal oxide semiconductor (MOS) transistor, the gate pattern 136 may serve as a gate electrode.

Subsequently, the charge insulation layer 126, the charge storage layer 124, and the tunnel insulation layers 122 are sequentially etched using the mask pattern 140 as an etching mask to sequentially stack the tunnel insulation layer patterns 122a. ), The charge storage pattern 124a and the charge blocking pattern 126a may be formed. Subsequently, the mask pattern 140 may be removed or removed and used as a capping layer pattern. In another embodiment, when the semiconductor device having a finFET structure is used as a metal oxide semiconductor (MOS) transistor, the first insulating film 122, the second insulating film 124, the third insulating film 126, or a combination thereof An insulating film pattern patterned with an insulating film composed of a combination film may serve as a gate insulating film. Next, source / drain regions (not shown) may be formed by implanting impurities into the semiconductor substrate 100 adjacent to both sides of the transfer gate electrode 136.

When manufactured according to an embodiment of the present invention, the metal film (see 134 of FIG. 4) and the silicon film (see 132 of FIG. 4) are filled in the upper and lower regions of the gap, respectively, as shown in FIG. 5A. As described above, the metal gate pattern 134a and the silicon gate patterns 132a may be formed without voids. In addition, since the metal layer 134 fills the upper region of the gap, the metal gate pattern 134a may be formed without disconnection in a subsequent etching process. In addition, as shown in FIG. 5B, the metal layer 134 and the silicon layer 132 exposed by the mask pattern (refer to 140 of FIG. 4) may also fill the upper and lower regions of the gap. In the etching process for the film 134 and the silicon film 132, the metal film 134 and the silicon film 132 are removed without remaining. As a result, the metal gate pattern 134a may prevent a short circuit with the adjacent metal gate pattern.

Hereinafter, a semiconductor device according to an exemplary embodiment of the present invention will be described with reference to FIGS. 2 and 5A.

Active fins 104 that are limited to the semiconductor substrate 100 and extend in one direction may be provided by device isolation trenches (not shown). An isolation layer 102 may be provided to partially fill the isolation trench between the active fins 104. That is, the active fins 104 may have a portion protruding from the device isolation layer 102.

First insulating layer patterns, for example, tunnel insulating layer patterns 122a may be disposed on upper surfaces and sidewalls of the active fins 104. The tunnel insulating layers 122a may be thermal oxide layers. Second and third insulating layer patterns 124a and 126a sequentially stacked on the tunnel insulating layer patterns 122a may be disposed. In example embodiments, the second and third insulating layer patterns may be a charge storage layer pattern 124a and a charge blocking layer pattern 126a. The charge storage layer pattern 124a may be a silicon nitride layer or a high dielectric layer.

A gate pattern 136 crossing the upper portion of the active fins 104 is disposed on the charge blocking layer pattern 126a. In the present embodiment, the gate pattern 136 may serve as a control gate electrode. The control gate electrode 136 extends to fill the gap between the active fins 104. In this embodiment, the control gate electrode 136 may serve as word lines. The control gate electrode 136 is disposed in the metal gate pattern 134a covering the upper surfaces of the active fins 104 and the upper region of the gap, and in the lower region of the gap overlapping the metal gate pattern 134a. Silicon gate patterns 132a. In addition, the control gate electrode 136 may further include a nitride film gate pattern 130a interposed between the metal gate pattern 134a and the charge blocking pattern 126a. The nitride gate pattern 130a may extend to the lower portion of the silicon gate patterns 132a to be interposed between the silicon gate patterns 132a and the charge blocking pattern 126a. The metal gate pattern 134a may be a tungsten film, and the silicon gate patterns 132a may be a polysilicon film. The nitride gate pattern 130a may be a tantalum nitride layer or a titanium nitride layer.

Source / drain regions (not shown) may be disposed in the active fins 104 adjacent to both sides of the control gate electrode 136. The source / drain regions may be high concentration impurity regions.

When a semiconductor device having a finFET structure is used as a metal oxide semiconductor (MOS) transistor, the gate pattern 136 is adopted as a gate electrode, and the first to third insulating film patterns 122a, 124a, and 126a or The insulating film pattern composed of these combination films can be adopted as the gate insulating film.

6 to 8B, a method of manufacturing a semiconductor device according to another embodiment of the present invention will be described. Another embodiment of the semiconductor device is a flash memory cell having a floating gate. 6 is a plan view of a flash memory cell according to another exemplary embodiment of the present invention, and FIGS. 7A and 8A are cross-sectional views taken along the line VV ′ of FIG. 6, and FIGS. 7B and 8B are VI of FIG. 6. Process cross-sectional views cut along the line 'VI'.

6, 7A, and 7B, an isolation trench (not shown) may be formed in the semiconductor substrate 200 to define active fins 204 extending in one direction. An insulating layer may be formed to fill the device isolation trench and cover the semiconductor substrate 200. The isolation layer 202 may be formed by recessing the insulating layer to partially fill the isolation trench.

The first insulating layer 222 may be formed on the semiconductor substrate 200 having the active fins 204. The first insulating layer 222 may be formed to cover top surfaces and sidewalls of the active fins 204. In another embodiment, the first insulating layer 222 may be adopted as a tunnel insulating layer. The first insulating layer 222 may be formed of a silicon oxide layer such as a thermal oxide layer. Next, a charge storage layer 224 is formed on the first insulating layer 222. The charge storage layer 224 may be adopted as a floating gate layer and formed as a doped polysilicon layer. The floating gate layer 224 may be formed to cover top surfaces and sidewalls of the active fins 204. The second insulating layer 226 may be formed on the semiconductor substrate 200 having the floating gate layer 224. The second insulating layer 226 may be formed of a silicon oxide film, a silicon nitride film, a high dielectric film, or a combination thereof.

Subsequently, the metal nitride layer 230 and the silicon patterns 232 are sequentially formed on the semiconductor substrate 200 having the second insulating layer 226. The silicon patterns 232 are formed to fill the lower region of the gap between the active fins 204. Since the formation process thereof has been described above with reference to FIGS. 3A and 3B, description thereof will be omitted. Subsequently, a metal film 234 is formed on the entire surface of the semiconductor substrate 200 having the silicon patterns 232. In detail, the metal layer 234 may be formed to cover an upper region of the metal nitride layer 230 and an upper region of a gap between the active fins 204. Since the formation process thereof has been described above with reference to FIGS. 4A and 4B, description thereof will be omitted.

Subsequently, a mask pattern 240 may be formed on the metal layer 234 to cross the active fins 204.

6, 8A, and 8B, the metal layer 234, the silicon patterns 232, and the metal nitride layer 230 are sequentially etched using the mask pattern 240 as an etch mask. As a result, the metal gate pattern 234a crossing the upper surfaces of the active fins 204 and filling the upper region of the gap, and the silicon gate patterns filling the lower region of the gap overlapping the metal gate pattern 234a ( 232a) is formed. In addition, a nitride film gate pattern 230a may be formed between the metal gate pattern 234a and the upper portions of the active fins 204 along the extending direction of the metal gate pattern 234a. The nitride gate pattern 230a may extend below the silicon gate patterns 232a and be interposed between the silicon gate patterns 232a and the lower portions of the active fins 204. That is, gate patterns including the metal gate pattern 234a, the silicon gate patterns 232a, and the nitride film gate pattern 230a may be formed. In the present embodiment, the gate patterns may be adopted as the transfer gate electrode 236.

Subsequently, the second insulating layer 226, the floating gate layer 224, and the first insulating layer 222 may be sequentially etched using the mask pattern 240 as an etching mask. As a result, the first insulating film pattern 222a, the floating gate 224a, and the second insulating film pattern 226a that are sequentially stacked are formed. The floating gate 224a may be formed to be self-aligned.

The mask pattern 240 may be used as a capping layer pattern without removing or removing the mask pattern 240. Subsequently, source / drain regions (not shown) may be formed by implanting impurities into the semiconductor substrate 200 adjacent to both sides of the transfer gate electrode 236.

A flash memory cell manufactured by another embodiment of the present invention is also formed without disconnection of the transfer gate electrode 236 in the gap between the active fins 204, as shown in Figure 8a. As shown in FIG. 8B, the metal gate pattern 234a may be formed without a short circuit with an adjacent metal gate pattern to improve reliability of the flash memory cell.

As described above, according to the present invention, a silicon film is formed in the lower region of the gap between the active fins to reduce the aspect ratio of the gap. As a result, the metal film filling the upper region of the gap can be well formed without voids or thinning phenomenon. Thus, the metal gate pattern can be formed without voids. In addition, in the subsequent etching process, the metal gate pattern may be formed without disconnection. In addition, the metal film may not remain in the etching process for the metal film. As a result, the metal gate pattern may prevent a short circuit with an adjacent metal gate pattern.

Claims (18)

Forming active fins extending in one direction on the semiconductor substrate, Forming a silicon pattern in a lower region of the gap between the active fins, Forming a metal film on the semiconductor substrate having the silicon pattern, Patterning the metal layer to form a metal gate pattern crossing the upper surfaces of the active fins, wherein the metal gate pattern is formed in an upper region of the gap; Forming a silicon gate pattern by patterning the silicon pattern, wherein the silicon gate pattern is formed in a lower region of the gap overlapping the metal gate pattern. According to claim 1, The silicon pattern is a method of manufacturing a semiconductor device formed of a polysilicon film. The method of claim 2, Forming the silicon pattern forms a polysilicon film on the entire surface of the semiconductor substrate having the active fins,  A method of manufacturing a semiconductor device comprising etching back the polysilicon layer using an etching gas containing chlorine or hydrogen bromide. According to claim 1, And the metal film is formed of a tungsten film. According to claim 1, Before forming the silicon pattern, a metal nitride film covering the semiconductor substrate between the active fins is formed together with the upper surfaces and the sidewalls of the active fins, After forming the silicon gate pattern, etching the metal nitride layer to form a nitride layer gate pattern. According to claim 1, Before forming the silicon pattern, forming a gate insulating film covering upper surfaces and sidewalls of the active fins. According to claim 1, Before forming the silicon pattern. Forming a first insulating film covering upper surfaces and sidewalls of the active fins, A charge storage layer is formed on the first insulating layer, And forming a second insulating film on the charge storage film. The method of claim 7, wherein The charge storage layer is a method of manufacturing a semiconductor device formed of a silicon nitride film or a high dielectric film. The method of claim 7, wherein And the charge storage layer is a floating gate layer, and the charge storage layer is formed of a doped polysilicon layer. The method of claim 7, wherein And the first insulating film is a silicon oxide film, and the second insulating film is formed of a silicon oxide film, a high dielectric film, or a combination thereof. Active fins extending in one direction on the semiconductor substrate; A metal gate pattern crossing the top surface of the active fins and provided in an upper region of a gap between the active fins; And And a silicon gate pattern provided in a lower region of the gap overlapping the metal gate pattern. The method of claim 11, wherein The silicon gate pattern is a polysilicon film, and the metal film is a tungsten film. The method of claim 11, wherein The semiconductor device may further include a nitride gate pattern provided along an elongated direction of the metal gate pattern, wherein the nitride gate pattern is a metal nitride layer, interposed between the metal gate pattern and an upper portion of the active fins, and a lower portion of the silicon gate pattern. A semiconductor device interposed between the silicon gate pattern and a lower portion of the active fins. The method of claim 11, wherein And a gate insulating layer pattern interposed between the metal gate pattern and the upper portion of the active fins and interposed between the silicon gate pattern and the lower portion of the active fins. The method of claim 11, wherein A first insulating layer pattern interposed between the metal gate pattern and the upper portion of the active fins and between the silicon gate pattern and the lower portion of the active fins; A charge storage pattern positioned on the first insulating layer pattern; And And a second insulating film pattern positioned on the charge storage pattern. The method of claim 15, The charge storage pattern is a semiconductor device or a silicon nitride film. The method of claim 15, And the charge storage pattern is a floating gate, and the charge storage pattern is a doped polysilicon layer. The method of claim 15, The first insulating film pattern is a silicon oxide film, and the second insulating film pattern is a silicon oxide film, a high dielectric film or a combination thereof.

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