KR20070077969A - Mehtods of forming non-volatile memory device having floating gate - Google Patents

Abstract

A method for forming a nonvolatile memory device having a floating gate is provided to prevent the damage of the floating gate due to a trench etching process by forming a trench using a spacer made of a trap-free insulating material. A tunnel insulating layer(102a), a first floating gate layer(104a) and a hard mask layer are sequentially formed on a substrate(100). A first opening for exposing the tunnel insulating layer to the outside is formed by patterning selectively the first floating gate layer and the hard mask layer. A spacer layer is formed along an upper surface of the resultant structure. The spacer layer is made of a trap-free insulating material. A spacer(110a') is formed at both sidewalls of the first opening by performing an anisotropic etching process on the spacer layer and the tunnel insulating layer until the substrate is exposed to the outside. A trench(112) for defining an active region is formed by etching the exposed portion of the substrate. An isolation pattern(114') for filling the trench and the first opening is formed thereon.

Description

A method of forming a nonvolatile memory device having a floating gate {MEHTODS OF FORMING NON-VOLATILE MEMORY DEVICE HAVING FLOATING GATE}

1 to 4 are cross-sectional views illustrating a method of forming a flash memory device according to the prior art.

5 through 16 are cross-sectional views illustrating a method of forming a nonvolatile memory device in accordance with an embodiment of the present invention.

17 is a cross-sectional view taken along the line II ′ of FIG. 16.

The present invention relates to a method of forming a semiconductor device, and more particularly, to a method of forming a nonvolatile memory device having a floating gate.

The nonvolatile memory device retains stored data even when power supply is interrupted. Currently, a representative nonvolatile memory device may be a flash memory device having a floating gate. Depending on the presence or absence of charges in the electrically isolated floating gate, the flash memory element may store data of logic "1" or logic "0".

In flash memory devices, the alignment between the floating gate and the active region where the channel region is defined is very important. Conventionally, after the active region is formed, the tunnel oxide layer and the floating gate layer are sequentially formed, and the floating gate layer is patterned to align the floating gate and the active region. However, due to the high integration of semiconductor devices, the alignment margin between the floating gate and the active region is reduced, and a new method for aligning the floating gate and the active region is required.

Recently, a method of aligning the floating gate and the active region by a self-aligning method has been proposed. This will be described with reference to the drawings.

1 to 4 are cross-sectional views illustrating a method of forming a flash memory device according to the prior art.

Referring to FIG. 1, a tunnel oxide film 2, a first floating gate film 3, and a hard mask film 4 are sequentially formed on a semiconductor substrate 1. The first floating gate layer 3 is formed of polysilicon, and the hard mask layer 4 is formed to include a silicon nitride layer.

Referring to FIG. 2, the hard mask layer 4, the first floating gate layer 3, the tunnel oxide layer 2, and the semiconductor substrate 1 are successively patterned to form an active region in the semiconductor substrate 1. The defining trench 5 is formed. In this case, the tunnel oxide pattern 2a, the first floating gate pattern 3a, and the hard mask pattern 4a, which are sequentially stacked on the active region, are formed. The first floating gate pattern 3a and the trench 5 are formed by one photolithography process. That is, the trench 5 and the first floating gate pattern 3a are self aligned. Accordingly, the first floating gate pattern 3a is self-aligned to the active region.

Referring to FIG. 3, a device isolation film filling the trench 5 is formed on the entire surface of the semiconductor substrate 1, and the device isolation film is planarized until the hard mask pattern 4a is exposed to form the device isolation film 6. do. Subsequently, the exposed hard mask pattern 4a is removed to expose the first floating gate pattern 3a. The device isolation layer 6 may be recessed by a cleaning process or the like, and may be formed to have a height close to an upper surface of the first floating gate pattern 3a.

Next, a second floating gate film 7 is formed over the entire surface of the semiconductor substrate 1. The second floating gate layer 7 is in contact with the first floating gate pattern 3a. The second floating gate layer 7 is formed of a polysilicon layer.

Referring to FIG. 4, the second floating gate layer 7 is patterned to form a second floating gate pattern 7a on the first floating gate pattern 3a. The first and second floating gate patterns 3a and 7a constitute a preliminary floating gate 8. An ONO film 9 (Oxide-Nitride-Oxide) and a control gate conductive film 10 are sequentially formed on the semiconductor substrate 1. Thereafter, the control gate conductive film 10, the ONO film 9, and the preliminary floating gate 8 are successively patterned to form a floating gate, an ONO pattern, and a control gate electrode which are sequentially stacked.

According to the above-described method of forming a flash memory device, the first floating gate pattern 3a and the active region formed in the lower portion of the floating gate are self-aligned. As a result, misalignment between the floating gate and the active region can be prevented.

However, the sidewalls of the first floating gate pattern 3a are exposed while the semiconductor substrate 1 is etched to form the trench 5. Accordingly, etch damage of the lower sidewall of the floating gate adjacent to the device isolation pattern 7 may be deepened. As a result, many defects may be generated in the lower sidewall of the floating gate, thereby deteriorating electrical characteristics of the floating gate. As the floating gate becomes smaller due to higher integration, the above-described deterioration of electrical characteristics may be further intensified. In addition, the floating gate covers an edge of the active region. As a result, an electric field may be concentrated on the edge of the active region, thereby deteriorating the characteristics of the flash memory device. For example, even if a voltage lower than a threshold voltage is induced in the floating gate, a channel of a region where the electric field is concentrated may be turned on. Therefore, leakage current or the like can be generated to deteriorate the characteristics of the flash memory device.

In addition, the second floating gate pattern 7a is formed by patterning the second floating gate layer 7. Thus, the size of the flash memory device may be due to a gap for the photolithography process between the second floating gate patterns 7a and / or an alignment margin between the second and first floating gate patterns 7a and 3a. Reducing may be limited. As a result, it may be difficult to highly integrate the flash memory device.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above-mentioned general problems, and a technical object of the present invention is to provide a method of forming a nonvolatile memory device suitable for high integration.

Another object of the present invention is to provide a method of forming a nonvolatile memory device for forming a floating gate having excellent electrical characteristics.

Another object of the present invention is to provide a method of forming a nonvolatile memory device suitable for high integration as well as excellent electrical characteristics of a floating gate.

To provide a method of forming a nonvolatile memory device for solving the above technical problem. This method includes the following steps. A tunnel insulating film, a first floating gate film, and a hard mask film are sequentially formed on the substrate. The hard mask layer and the first floating gate layer may be patterned to form a first floating gate pattern and a hard mask pattern sequentially stacked to form a first opening exposing the tunnel insulating layer and sidewalls of the first opening. A spacer film is conformally formed on the substrate, and the spacer film is formed of an insulating material without traps. The spacer layer and the tunnel insulating layer are anisotropically etched until the substrate is exposed to form spacers on both sidewalls of the first opening. The exposed substrate is etched to form a trench defining an active region. An isolation pattern is formed to fill the trench and the first opening. The hard mask pattern is removed to form a second opening exposing the first floating gate pattern. A second floating gate pattern is formed to fill the second opening.

In detail, the first and second floating gate patterns may form a preliminary floating gate. The method may further include: recessing the device isolation pattern to expose sidewalls of the second floating gate pattern; Sequentially forming a blocking insulating film and a control gate conductive film on the substrate; And sequentially patterning the control gate conductive layer, the blocking insulating layer, and the preliminary floating gate to form a floating gate, a blocking insulating pattern, and a control gate electrode which are sequentially stacked. The method may further include implanting dopant ions using the control gate electrode as a mask to form a dopant doped region in the active region on both sides of the control gate electrode. The blocking insulating layer may be formed to include a high dielectric material having a higher dielectric constant than the tunnel insulating layer. The forming of the second floating gate pattern may include forming a second floating gate layer on the entire surface of the semiconductor substrate, the second floating gate layer filling the second opening; And planarizing the second floating gate layer until the device isolation pattern is exposed to form the second floating gate pattern. The width of the second opening may be larger than the width of the first floating gate pattern, and a lower surface of the second floating gate pattern may be wider than an upper surface of the first floating gate pattern.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided so that the disclosed contents may be thorough and complete, and to fully convey the spirit of the present invention to those skilled in the art. In the drawings, the thicknesses of layers (or films) and regions are exaggerated for clarity. In addition, where it is said that a layer (or film) is "on" another layer (or film) or substrate, it may be formed directly on another layer (or film) or substrate or a third layer between them. (Or membrane) may be interposed. Portions denoted by like reference numerals denote like elements throughout the specification.

5 to 16 are cross-sectional views illustrating a method of forming a nonvolatile memory device according to an embodiment of the present invention, and FIG. 17 is a cross-sectional view taken along the line II ′ of FIG. 16.

Referring to FIG. 5, a tunnel insulating film 102, a first floating gate film 104, and a hard mask film 106 are sequentially formed on a semiconductor substrate 100 (hereinafter, referred to as a substrate). The tunnel insulation layer 102 may be formed of a silicon oxide layer, in particular, a thermal oxide layer. The substrate 100 may be a silicon substrate. The first floating gate layer 104 may be formed of doped polysilicon. The hard mask layer 106 may include a material having an etch selectivity with respect to the floating gate layer 104 and the substrate 100. For example, the hard mask layer 106 may include a silicon nitride layer. In addition, the hard mask layer 106 may further include a buffer oxide layer interposed between the silicon nitride layer and the first floating gate layer 104. The buffer oxide layer may function to buffer stress between the silicon nitride layer and the first floating gate layer 104.

Referring to FIG. 6, the hard mask layer 106 and the first floating gate layer 104 are successively patterned to form a first opening 108 exposing the tunnel insulating layer 102. In this case, a first floating gate pattern 104a and a hard mask pattern 106a forming sidewalls of the first opening 108 are formed. The first floating gate pattern 104a and the hard mask pattern 106a are sequentially stacked. During the etching process for the first opening 108, the tunnel insulating layer 102 may serve as an etch stop layer to protect the etching damage on the surface of the substrate 100 under the first opening 108. .

Referring to FIG. 7, the spacer layer 110 is conformally formed on the entire surface of the substrate 100. The spacer layer 110 may be formed of an insulating material having no traps. For example, the spacer layer 110 may be formed of a silicon oxide layer.

Referring to FIG. 8, the spacer layer 110 and the tunnel insulating layer 102 are anisotropically etched until the substrate 100 is exposed. As a result, spacers 110a are formed on both sidewalls of the first opening 108. That is, the spacer 110a is formed on both sidewalls of the first floating gate pattern 104a and the hard mask pattern 106a. In addition, a tunnel insulation pattern 102a is formed under the spacer 110a and the first floating gate pattern 104a. As shown, the width of the tunnel insulation pattern 102a is wider than the width of the first floating gate pattern 104a.

As described above, the spacers 110a are formed on both sidewalls of the first openings 108, and the substrate 100 under the first openings 108 between the spacers 110a is exposed. When the spacer 110a is formed, the top surface of the hard mask pattern 106a is exposed together with the substrate 100 under the first opening 108.

Referring to FIG. 9, the trench 112 is formed by etching the exposed substrate 100 using the hard mask pattern 106a and the spacer 110a as an etching mask. The trench 112 defines an active region.

In an etching process for forming the trench 112, sidewalls adjacent to the trench 112 of the first floating gate pattern 104a are protected by the spacer 110a. Accordingly, the etching damage of the sidewall of the first floating gate pattern 104a may be prevented when the trench 112 is etched. As a result, it is possible to form the first floating gate pattern 104a in which defects are minimized.

Referring to FIG. 10, a thermal oxidation process is performed to etch damage of the trench 112. The sidewall oxide layer 113 is formed on the bottom and sidewalls of the trench 112 by the thermal oxidation process. In the thermal oxidation process, the first floating gate pattern 104a is protected by the hard mask pattern 106a and the spacer 110a and thus is not oxidized.

Subsequently, a device isolation insulating film filling the trench 112 and the first opening 108 is formed on the entire surface of the substrate 100, and the device isolation insulating film is planarized until the hard mask pattern 106a is exposed. Separation pattern 114 is formed. The device isolation insulating film may be formed of a silicon oxide film such as a USG (Undoped Silicate Glass) film formed by a chemical vapor deposition method (CVD). The process of planarizing the device isolation insulating layer may be performed by an etch-back or a chemical mechanical polishing process.

11 and 12, the hard mask pattern 106a is removed to form a second opening 116 exposing the first floating gate pattern 104a. In this case, the spacer 110a may form a sidewall of the second opening 116.

The sidewalls of the second openings 116 may be etched by an isotropic etching process (eg, wet etching). Accordingly, the width of the isotropically etched second opening 116a is wider than the width of the first floating gate pattern 104a.

The hard mask pattern 106a may include the same material as the spacer 110a. That is, the hard mask pattern 106a may include the buffer oxide layer as described above. The buffer oxide layer may be formed of a silicon oxide layer. In this case, the hard mask pattern 106a may be removed by isotropic etching. When the hard mask pattern 106a is removed by isotropic etching, at least the spacers 110a may be isotropically etched to form the isotropically etched second openings 116a. When the hard mask pattern 106a is removed by isotropic etching, the device isolation pattern 114 may also be isotropically etched. Reference numeral "114 '" denotes an isotropic etched device isolation pattern 114'.

Alternatively, after the hard mask pattern 106a is removed to form the second opening 116, the process of isotropically etching at least the spacer 110a is performed to further perform the isotropically etched second opening ( 116a) may be formed. Even in this case, the device isolation pattern 114 may be isotropically etched.

A residue 110a ′ of the spacer may be exposed on the bottom surface of the isotropically etched second opening 116a and the second floating gate pattern 104a.

Referring to FIG. 13, a second floating gate layer 118 filling the isotropically etched second opening 116a is formed on the entire surface of the substrate 100. The second floating gate layer 118 is in contact with the first floating gate pattern 104a. The second floating gate layer 118 may be formed of doped polysilicon.

Referring to FIG. 14, the second floating gate pattern 118a is planarized until the device isolation pattern 114 ′ is exposed to fill the isotropically etched second opening 116a. To form. The first and second floating gate patterns 104a and 118a constitute the preliminary floating gate 120. The process of planarizing the second floating gate layer 118 may be performed by an etch back or a chemical mechanical polishing process.

Referring to FIG. 15, the device isolation pattern 114 ′ is recessed to expose sidewalls of the second floating gate pattern 118a. An upper surface of the recessed device isolation pattern 114a may be formed to have a height close to a lower surface of the second floating gate pattern 118a.

Alternatively, the sidewalls of the first floating gate pattern 104a may be further exposed by recessing the device isolation pattern 114 ′ and the residue 110a ′ of the spacer by isotropic etching.

A blocking insulating layer 122 is conformally formed on the substrate 100 having the recessed device isolation pattern 114a, and a control gate conductive layer 124 is formed on the blocking insulating layer 122. The control gate conductive layer 124 covers the exposed surface of the preliminary floating gate 120 (that is, at least the top surface and sidewalls of the second floating gate pattern 118a) through the blocking insulating layer 122. .

The blocking insulating layer 122 may be formed of an ON-Nitride-Oxide layer. In contrast, the blocking insulating layer 122 may include a high dielectric insulating layer having a higher dielectric constant than the tunnel insulating pattern 102a. For example, the blocking insulating layer 122 may be formed of an insulating metal oxide layer such as a hafnium oxide layer or an aluminum oxide layer. The control gate conductive layer 124 may include a doped polysilicon layer, a metal layer (eg, tungsten or molybdenum, etc.), a conductive metal nitride layer (eg, titanium nitride or tantalum nitride layer, etc.) and a metal silicide layer (ex, tungsten silicide layer). Or a cobalt silicide film or the like).

Although not illustrated, a capping insulating layer may be formed on the control gate conductive layer 124. The capping insulating layer may be formed of at least one selected from a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

16 and 17, the control gate conductive layer 124, the blocking insulating layer 122, and the preliminary floating gate 120 are successively patterned to sequentially stack the floating gate 120a and the blocking insulating pattern 122a. And the control gate electrode 124a. The floating gate 120a includes lower and upper gates 104b and 118b which are sequentially stacked. The lower gate 104b is a portion of the first floating gate pattern 104a and the upper gate 118b is a portion of the second floating gate pattern 118a.

Subsequently, dopant ions are implanted using the control gate electrode 124 as a mask to form dopant doped regions 126 in the active regions on both sides of the control gate electrode 124. The dopant doped region 126 corresponds to a source / drain region of a nonvolatile memory cell.

According to the method of forming the nonvolatile memory device described above, during the etching process for forming the trench 122, the spacer 110a protects sidewalls of the first floating gate pattern 104a. As a result, etching damage may be minimized on sidewalls of the lower gate 104b of the floating gate 120a. As a result, the floating gate 120a having excellent characteristics can be formed.

In addition, the trench 112 may be etched using the spacer 110a and the hard mask pattern 106a as a mask. Accordingly, the edge of the active region and the edge of the lower gate 104b are spaced apart from each other. More specifically, due to the spacer 110a, the floating gate 120a and the active region are formed in self-alignment, and the edge of the active region and the edge of the lower gate 104b are spaced apart from each other. As a result, it is possible to implement a nonvolatile memory device having excellent characteristics and optimized for high integration by preventing a conventional electric field concentration phenomenon.

In addition, the second floating gate pattern 118a is formed in the second opening portion 116a formed by removing the hard mask pattern 106a self-aligned to the first floating gate pattern 104a. Accordingly, the first and second floating gate patterns 104a and 118a are formed to be self aligned with each other. In addition, a photolithography process is not required when forming the second floating gate pattern 118a. As a result, an alignment margin between the first and second floating gate patterns 104a and 118a is not required, and a minimum spacing for the photolithography process between the second floating gate patterns 118a is not required. . This makes it possible to form a nonvolatile memory device which is much more highly integrated than in the prior art.

Furthermore, the spacer 110a that may remain next to the lower gate 104b of the floating gate 120a is formed of an insulating material in which traps do not exist. Accordingly, the electrical characteristics of the floating gate 120a are improved.

If an insulating material having traps such as a silicon nitride film is formed around the lower portion of the floating gate, charges may be stored in the traps to deteriorate electrical characteristics of the nonvolatile memory cell. In contrast, in the method of forming the nonvolatile memory device according to the present invention, as described above, the spacers 110a are formed of an insulating material having no traps, so that traps exist around the lower gate 104b. I never do that. In addition, the device isolation pattern 114 is also formed of a silicon oxide film without traps. Accordingly, no traps exist around the upper gate 118b. In addition, in the present invention, a liner formed of a silicon nitride film well known in the art is not formed at all. As a result, there are no traps around the floating gate 120a to form a nonvolatile memory device having excellent electrical characteristics.

As described above, according to the present invention, trenches are formed using spacers formed of an insulating material in which no traps are present. As a result, when etching the trench, the etching damage of the first floating gate pattern formed as the lower portion of the floating gate may be prevented. In addition, an edge of the first floating gate pattern is spaced apart from an edge of an active region due to the spacer, and the first floating gate pattern and the active region are self-aligned. As a result, the conventional electric field concentration phenomenon can be prevented. In addition, due to the spacer, since there are no traps around the floating gate, a nonvolatile memory cell having excellent electrical characteristics can be formed.

The second floating gate pattern formed above the floating gate is self-aligned with the first floating gate pattern so that alignment margin of the photolithography process between the first and second floating gate patterns is not required. In addition, a photolithography process is not required to form the second floating gate pattern. As a result, the minimum line width for the photolithography process between the second floating gate patterns is not required. As a result, it is possible to form a nonvolatile memory device which is much more highly integrated than in the prior art.

Claims (11)

Sequentially forming a tunnel insulating film, a first floating gate film, and a hard mask film on the substrate; Patterning the hard mask layer and the first floating gate layer to form a first floating gate pattern and a hard mask pattern sequentially stacked to form a first opening exposing the tunnel insulating layer and sidewalls of the first opening; Forming a spacer film conformally on the substrate, wherein the spacer film is formed of an insulating material having no traps; Anisotropically etching the spacer film and the tunnel insulating film until the substrate is exposed to form spacers on both sidewalls of the first opening; Etching the exposed substrate to form a trench defining an active region; Forming a device isolation pattern filling the trench and the first opening; Removing the hard mask pattern to form a second opening exposing the first floating gate pattern; And And forming a second floating gate pattern filling the second opening. The method of claim 1, The first and second floating gate patterns constitute a preliminary floating gate, Recessing the device isolation pattern to expose sidewalls of the second floating gate pattern; Sequentially forming a blocking insulating film and a control gate conductive film on the substrate; And And patterning the control gate conductive film, the blocking insulating film, and the preliminary floating gate in succession to form a floating gate, a blocking insulating pattern, and a control gate electrode which are sequentially stacked. The method of claim 2, And implanting dopant ions using the control gate electrode as a mask to form a dopant doped region in the active region on both sides of the control gate electrode. The method of claim 2, And the blocking insulating film is formed to include a high dielectric material having a higher dielectric constant than the tunnel insulating film. The method of claim 1, Forming the second floating gate pattern, Forming a second floating gate layer over the semiconductor substrate, the second floating gate layer filling the second opening; And And planarizing the second floating gate layer until the device isolation pattern is exposed to form the second floating gate pattern. The method of claim 1, The width of the second opening is greater than the width of the first floating gate pattern so that the bottom surface of the second floating gate pattern is wider than the top surface of the first floating gate pattern. Way. The method of claim 6, The hard mask pattern includes at least the same material as the spacers, and the hard mask pattern is removed by isotropic etching, And removing the hard mask pattern by isotropic etching, wherein at least the spacers are isotropically etched to form a wide width of the second opening. The method of claim 6, Before forming the second floating gate pattern, And at least isotropically etching the spacers to widen the width of the second openings. The method of claim 1, And the spacer is formed of a silicon oxide film. The method of claim 1, And the first and second floating gate patterns are formed of doped polysilicon. The method of claim 1, Before forming the device isolation pattern, And performing a thermal oxidation process on sidewalls and bottom surfaces of the trench.

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