KR100825789B1 - Non-volatile memory device and method of fabricating the same - Google Patents

Abstract

A non-volatile memory device and a method for manufacturing the same are provided to suppress loss of an active region in an edge of a peripheral region by forming sequentially gate electrodes of a MOS transistor. A cell region and a peripheral region are defined on a semiconductor substrate(105). A memory transistor includes a storage node layer(125a) of the cell region and a control gate electrode of the storage node layer. A MOS transistor includes a first gate electrode(145b) of the peripheral region and a second gate electrode(170a,170b) connected electrically to the first gate electrode. The control gate electrode of the memory transistor and the second gate electrode of the MOS transistor are formed with the same material. The control gate electrode is arranged to surround a sidewall of the storage node layer along a word line direction.

Description

Non-volatile memory device and method of manufacturing the same {Non-volatile memory device and method of fabricating the same}

1 is a cross-sectional view illustrating a step of forming an isolation layer in a nonvolatile memory device and a method of manufacturing the same according to an embodiment of the present invention;

2 and 3 are cross-sectional views illustrating a step of forming a storage node layer in a nonvolatile memory device and a method of manufacturing the same according to an embodiment of the present invention;

4 and 5 are cross-sectional views illustrating a step of forming a first gate electrode in a nonvolatile memory device and a method of manufacturing the same according to an embodiment of the present invention;

6 and 7 are cross-sectional views illustrating a step of forming a blocking insulating film in a nonvolatile memory device and a method of manufacturing the same according to an embodiment of the present invention; And

8 is a cross-sectional view illustrating a process of forming a control gate electrode and a second gate electrode in a nonvolatile memory device and a method of manufacturing the same according to an embodiment of the present invention.

The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a nonvolatile memory device and a method for manufacturing the same.

A memory transistor of a nonvolatile memory device, such as a flash memory device, has a stacked structure of a floating gate and a control gate electrode. On the other hand, a MOS transistor having a single gate electrode is formed in the peripheral region of the flash memory device. Therefore, a step may occur between the memory transistor and the MOS transistor.

This step can cause various problems in the manufacturing step. First, it is difficult to simultaneously form the control gate electrode of the memory transistor and the gate electrode of the MOS transistor. Because the step is large between the control gate electrode and the gate electrode, defects are likely to occur at the boundary portion in the etching step for patterning. For example, a bridge may be generated by stringer generation, which may act as a foreign material at a later stage of manufacture.

Furthermore, even if the control gate electrode and the gate electrode are formed separately, the distribution of the critical dimension (CD) of the control gate electrode or the gate electrode may worsen because of the step. This dispersion may occur due to a thickness failure of the photoresist pattern in the control gate electrode or gate electrode patterning step. Such a poor dispersion of the control gate electrode or the critical dimension of the gate electrode can greatly reduce the reliability of the nonvolatile memory device.

An object of the present invention is to provide a nonvolatile memory device capable of reducing the step difference between a memory transistor and a MOS transistor to increase its reliability.

Another object of the present invention is to provide a method of manufacturing a nonvolatile memory device capable of reducing the step difference between a memory transistor and a MOS transistor to increase its reliability.

A nonvolatile memory device of one embodiment of the present invention for achieving the above technical problem includes a semiconductor substrate in which a cell region and a peripheral region are defined. The memory transistor includes a storage node layer on the cell region and a control gate electrode on the storage node layer. The MOS transistor includes a first gate electrode on the peripheral region and a second gate electrode electrically connected to the first gate electrode on the first gate electrode. The control gate electrode of the memory transistor and the second gate electrode of the MOS transistor are formed of the same material.

According to an aspect of the present invention, the height difference between the control gate electrode of the memory transistor and the second gate electrode of the MOS transistor may be within 500 mW.

According to another aspect of the present invention, the first gate electrode and the second gate electrode of the MOS transistor may be in direct contact.

A method for manufacturing a nonvolatile memory device of one embodiment of the present invention for achieving the above another technical problem is provided. A storage node layer is formed on the cell region of the semiconductor substrate in which a cell region and a peripheral region are defined. A first gate electrode is formed on the peripheral region. A control gate electrode is formed on the storage node layer of the cell region. A second gate electrode is formed on the first gate electrode of the peripheral area, the second gate electrode being electrically connected to the first gate electrode. The control gate electrode and the second gate electrode are simultaneously formed.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention and to those skilled in the art to fully understand the scope of the invention. It is provided to inform you. In the accompanying drawings, the thicknesses of the various films and regions are highlighted for clarity.

In embodiments of the present invention, the nonvolatile memory device may include a flash memory device having a storage node layer of a floating gate type or a charge trap type. A flash memory device having a charge trap type storage node layer may be referred to as a SONOS memory device. However, the present invention is not limited in scope by these names.

Referring to FIG. 8, a nonvolatile memory device according to an embodiment of the present invention will be described. 8 exemplarily illustrates a cross section in the word line direction of a nonvolatile memory device having a NAND structure. However, the present invention is not limited to this NAND structure.

Referring to FIG. 8, a cell region and a peripheral region are defined in the semiconductor substrate 105. For example, the cell region may be a region in which a memory transistor is formed, and the peripheral region may be a region in which a MOS transistor used for a driving element is formed. It is difficult to physically divide the boundary between the cell region and the peripheral region, but wide device isolation layers 115a and 115b may be formed at the boundary portion. The device isolation layers 115a and 115b define active regions (not shown) of the cell region and the peripheral region, respectively.

The memory transistor of the cell region includes a storage node layer 125a and a control gate electrode 170a. The storage node layer 125a is used to store charge, and the control gate electrode 170a controls the charge storage of the storage node layer 125a. The storage node layer 125a is insulated from the semiconductor substrate 105, and the control gate electrode 170a is insulated from the storage node layer 125a.

The MOS transistor in the peripheral area is used as a switching element and includes a first gate electrode 145b and a second gate electrode 170b. The first and second gate electrodes 145b and 170b are electrically connected to serve as one gate electrode. The first gate electrode 145b is insulated from the semiconductor substrate 105. For example, the first and second gate electrodes 145b and 170b may be in direct contact. That is, the bottom surface of the second gate electrode 170b may directly contact the top surface of the first gate electrode 145b. A gate insulating layer 140b may be interposed between the first gate electrode 145b and the semiconductor substrate 105.

For example, a tunneling insulating layer 120a may be interposed between the storage node layer 125a and the semiconductor substrate 105. The charge may move between the semiconductor substrate 105 and the storage node layer 125a through the tunneling insulating layer 120a. For example, the tunneling insulating film 120a may include an oxide film, a nitride film, or a high dielectric constant film. The storage node layer 125a may include a polysilicon layer, a silicon nitride film, a dot of metal or silicon, or a nanocrystal of metal or silicon. The polysilicon layer may be used as a floating gate type, and the silicon nitride film, dot, or nanocrystal may be used as a charge trap type.

A blocking insulating layer 160a may be interposed between the storage node layer 125a and the control gate electrode 170a. The blocking insulating layer 160a may prevent reverse tunneling of the charge between the storage node layer 130a and the control gate electrode 170a. For example, the blocking insulating layer 160a may include one or a stacked structure of an oxide film, a nitride film, and a high dielectric constant film, for example, a stacked structure of an oxide film / nitride film / oxide film.

 In this embodiment, the MOS transistor and the memory transistor have a similar stacked structure. That is, the memory transistor has a stacked structure of the storage node layer 125a and the control gate electrode 170a, and the MOS transistor has a stacked structure of the first and second gate electrodes 145b and 170b. The storage node layer 125a and the control gate electrode 170a are insulated by the blocking insulating layer 160a, but the first and second gate electrodes 145b and 170b are in contact with each other and electrically connected to each other.

Therefore, the height difference between the control gate electrode 170a and the second gate electrode 170b is not large. For example, when the height of the blocking insulating layer 160a is taken into consideration, the height difference between the control gate electrode 170a and the second gate electrode 170b may be within 500 kV. Therefore, the control gate electrode 170a and the second gate electrode 170b may be simultaneously formed of the same material. Similarly, the heights of the storage node layer 125a and the first gate electrode 145b may be similar. For example, the height difference between the storage node layer 125a and the first gate electrode 145b may be within 500 μs.

Meanwhile, in the NAND nonvolatile memory device, the blocking insulating film 160a and the control gate electrode 170a extend in the word line direction. In this case, the bottom surface of the blocking insulating layer 160a and the control gate electrode 170a on the device isolation layer 115a around the storage node layer 125a may be lower than the storage node layer 130a. This structure may serve to increase the strength of the electric field between the storage node layer 125a and the semiconductor substrate 105 by adjusting the coupling ratio between the storage node layer 125a and the control gate electrode 170a.

A method of manufacturing a nonvolatile memory device according to an embodiment of the present invention will be described with reference to FIGS. 1 to 8.

1 is a cross-sectional view illustrating a step of forming an isolation layer in a nonvolatile memory device and a method of manufacturing the same according to an embodiment of the present invention.

Referring to FIG. 1, device isolation layers 115a and 115b are formed in a cell region and a peripheral region of a semiconductor substrate 105 to define an active region. For example, the semiconductor substrate 105 is etched using the first mask pattern 110b as an etch protective film to form a trench (not shown), and the trench is embedded with an insulating film (not shown) and planarized to form the device isolation film 115a. , 115b). For example, the first mask pattern 110b may include a silicon nitride film.

2 and 3 are cross-sectional views illustrating a step of forming a storage node layer in a nonvolatile memory device and a method of manufacturing the same according to an embodiment of the present invention.

Referring to FIG. 2, the first mask pattern 110b is removed, and the tunneling insulating layers 120a and 120b are formed on the semiconductor substrate 105. For example, the tunneling insulating layers 120a and 120b may be formed using a thermal oxide film or chemical vapor deposition (CVD). Optionally, before forming the tunneling insulating layers 120a and 120b, the device isolation layers 115a and 115b may be isotropically etched to increase the width of the portion where the first mask pattern 110b is removed.

Subsequently, the storage node layers 125a and 12b are formed on the tunneling insulating layers 120a and 120b. For example, the storage node layers 125a and 125b may be formed by depositing, planarizing, and patterning a material layer using chemical vapor deposition (CVD). Accordingly, the storage node layers 125a and 125b may be formed to be aligned between the device isolation layers 115a and 115b.

Referring to FIG. 3, the tunneling insulating layer 120b and the storage node layer 125b on the peripheral area are selectively removed. For example, the second mask pattern 135a may be formed on the cell region, and the tunneling insulating layer 120b and the storage node layer 125b on the peripheral region may be selectively removed using the second mask pattern 135a as an etch protective layer. For example, the second mask pattern 135a may include a photoresist layer.

Optionally, before forming the second mask pattern 135a, an interlayer insulating layer 130a may be formed on the storage node layer 125a of the cell region. The interlayer insulating layer 130a may serve to separate and protect the storage node layer 125a from other layers in a later step.

4 and 5 are cross-sectional views illustrating a step of forming a first gate electrode in a nonvolatile memory device and a method of manufacturing the same according to an embodiment of the present invention.

Referring to FIG. 4, the second mask pattern 135a is removed and a gate insulating layer 140b is formed on the semiconductor substrate 105 in the peripheral region. Subsequently, first gate electrodes 145a and 145b are formed on the interlayer insulating layer 130a in the cell region and the gate insulating layer 140b in the peripheral region. Alternatively, the buffer insulating layer 150a may be formed on the first gate electrodes 145a and 145b. For example, the buffer insulating layers 150a and 150b may include an oxide film. The first gate electrode 145a and the storage node layer 125a of the cell region may be separated by the interlayer insulating layer 130a.

Referring to FIG. 5, the first gate electrode 145a, the buffer insulating layer 150a, and the interlayer insulating layer 130a of the cell region are formed by using the third mask pattern 155b on the buffer insulating layer 150b in the peripheral region as an etch protection layer. ) Is removed to expose the device isolation film 115a.

In some embodiments, the exposed device isolation layer 115a may be etched to make the upper height of the device isolation layer 115a lower than that of the storage node layer 125a. For example, etching of the exposed device isolation layer 115a may be performed by a blanket etch method without a separate mask pattern.

As shown in FIG. 5, the first gate electrode 145a in the peripheral region and the storage node layer 125a in the cell region may be disposed at substantially similar heights.

6 and 7 are cross-sectional views illustrating a step of forming a blocking insulating layer in a nonvolatile memory device and a method of manufacturing the same according to an embodiment of the present invention.

Referring to FIG. 6, the buffer insulating layers 150b on the peripheral region are removed, and blocking insulating layers 160a and 160b are formed on the storage node layer 125a of the cell region and the first gate electrode 145b of the peripheral region. . The height of the blocking insulating layer 160a on the device isolation layer 115a in the cell region may be lower than that of the storage node layer 125a.

Referring to FIG. 7, the blocking insulating layer 160b of the peripheral region is removed by using the fourth mask pattern 165a on the blocking insulating layer 160a of the cell region as an etch protection layer. Accordingly, the first gate electrode 145b of the peripheral area is exposed.

8 is a cross-sectional view illustrating a process of forming a control gate electrode and a second gate electrode in a nonvolatile memory device and a method of manufacturing the same according to an embodiment of the present invention.

Referring to FIG. 8, the fourth mask pattern 165a is removed, the control gate electrode 170a is formed on the blocking insulating layer 160a of the cell region, and at the same time, on the first gate electrode 145b of the peripheral region. The second gate electrode 170b is formed on the substrate. For example, the control gate electrode 170a and the second gate electrode 170b may be formed of the same material and formed at the same time. For example, the control gate electrode 170a and the second gate electrode 170b may include a polysilicon layer, a metal layer, or a metal silicide layer.

The second gate electrode 170b may be electrically connected by directly contacting the first gate electrode 145b. Accordingly, the second gate electrode 170b and the first gate electrode 145b may serve as gates of the MOS transistors.

As described above, in the manufacturing method of the nonvolatile memory device according to the embodiment of the present invention, the height difference between the control gate electrode 170a in the cell region and the second gate electrode 170b in the peripheral region is very small compared to the prior art. Therefore, it can form simultaneously without forming a defect. Accordingly, uniformity of critical dimensions of the control gate electrode 170a and the second gate electrode 170b may also be increased. In addition, the gate structure of the peripheral region may be separately formed as a double structure of the first and second gate electrodes 145b and 170b, thereby preventing the problem of the active region being etched and lost at the edge of the peripheral region. Therefore, the reliability of the nonvolatile memory device can be increased.

The foregoing descriptions of specific embodiments of the present invention have been presented for purposes of illustration and description. The present invention is not limited to the above embodiments, and various modifications and changes can be made by those skilled in the art within the technical spirit of the present invention.

According to the nonvolatile memory device and the manufacturing method thereof according to the present invention, the step difference between the memory transistor in the cell region and the MOS transistor in the peripheral region can be reduced. Therefore, the distribution of the critical dimensions of the memory transistor and the MOS transistor can be reduced, and defect formation can be suppressed. In addition, the gate electrode of the MOS transistor is separated and formed twice so that the problem that the active region is etched and lost at the edge of the peripheral region can be suppressed. Therefore, the reliability of the nonvolatile memory device can be improved.

Claims (16)

A semiconductor substrate in which a cell region and a peripheral region are defined; A memory transistor comprising a storage node layer on the cell region and a control gate electrode on the storage node layer; And A MOS transistor including a first gate electrode on the peripheral region and a second gate electrode electrically connected to the first gate electrode on the first gate electrode, The control gate electrode of the memory transistor and the second gate electrode of the MOS transistor are formed of the same material, And the control gate electrode is disposed to surround sidewalls of the storage node layer in a word line direction. The nonvolatile memory device of claim 1, wherein a bottom surface of the control gate electrode portion surrounding a sidewall of the storage node layer is lower than a bottom surface of the storage node layer. The nonvolatile memory device of claim 2, wherein a height difference between the storage node layer of the memory transistor and the first gate electrode of the MOS transistor is within 500 μs. The nonvolatile memory device of claim 1, wherein the first gate electrode and the second gate electrode of the MOS transistor are in direct contact with each other. The nonvolatile memory device of claim 2, wherein a height difference between the control gate electrode of the memory transistor and the second gate electrode of the MOS transistor is within 500 μs. The memory transistor of claim 2, wherein the memory transistor comprises: A tunneling insulating layer interposed between the cell region and the storage node layer; And a blocking insulating layer interposed between the storage node layer and the control gate electrode. The nonvolatile memory device of claim 2, wherein the storage node layer comprises any one of a polysilicon layer, a silicon nitride film, a metal dot, a silicon dot, a metal nanocrystal, and a silicon nanocrystal. Forming a storage node layer on the cell region of the semiconductor substrate in which a cell region and a peripheral region are defined; Forming a first gate electrode on the peripheral region; Forming a control gate electrode on the storage node layer in the cell region; And Forming a second gate electrode electrically connected to the first gate electrode on the first gate electrode in the peripheral region, The control gate electrode and the second gate electrode are simultaneously formed; The semiconductor substrate further comprises a device isolation layer disposed around the storage node layer, and further comprising etching the device isolation layer before forming the blocking insulating layer. The method of claim 8, wherein a height difference between the control gate electrode and the second gate electrode is within 500 μs. The method of claim 9, wherein a height difference between the storage node layer and the first gate electrode is within 500 μs. The method of claim 8, wherein the first gate electrode and the second gate electrode are formed to be in direct contact with each other. 9. The nonvolatile memory as in claim 8, further comprising forming an interlayer insulating film on the storage node layer before forming the first gate electrode, wherein the interlayer insulating film is removed before forming the control gate. Method of manufacturing the device. 10. The method of claim 8, further comprising forming a buffer insulating film on the first gate electrode after the formation of the first gate electrode, wherein the buffer insulating film is removed before forming the second gate electrode. Method of manufacturing a nonvolatile memory device. The nonvolatile memory device of claim 8, further comprising forming a blocking insulating layer on the storage node electrode before forming the control gate electrode, wherein the control gate electrode is formed on the blocking insulating layer. Method of preparation. 15. The method of claim 14, wherein a height of a bottom surface of the blocking insulating layer and the control gate electrode on the device isolation layer is lower than a bottom surface of the storage node layer. The method of claim 8, wherein the storage node layer comprises one of a polysilicon layer, a silicon nitride film, a metal dot, a silicon dot, a metal nanocrystal, and a silicon nanocrystal.

Images