JP2007294945A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device having a large gate width and high resistance accuracy by forming two of MOSFETs having different gate insulating films in a damascene gate process. <P>SOLUTION: A semiconductor device has: a high-voltage MOSFET part receiving relatively high voltage supply and comprising an N<SP>-</SP>MOSn<SP>-</SP>layer 12 for high voltage and a P<SP>-</SP>MOSp<SP>-</SP>layer 13 for high voltage; and a low-voltage MOSFET part comprising an N<SP>-</SP>MOSn<SP>-</SP>layer 14 for low voltage and a P<SP>-</SP>MOSp<SP>-</SP>layer 15 for low voltage on the same substrate. The semiconductor device comprises: a first insulating film layer formed in a gate region in the high voltage MOSFET part with relatively small capacitance per unit area and comprising a two-layer structure of a buffer oxide film 2a and a polysilicon layer; and a second insulating film layer formed in the gate region in the low-voltage MOSFET part with relatively large capacitance per unit area and comprising an No oxide film 24 and a Ta<SB>2</SB>O<SB>5</SB>film 25. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a large gate width and high resistance accuracy in a damascene gate transistor structure.

  In general, in a semiconductor device, the power supply voltage tends to decrease with miniaturization. For this purpose, it is necessary to increase the gate capacitance of the MOSFET used.

  In order to increase the gate capacitance, it is essential to reduce the thickness of the gate insulating film. However, as long as an oxide film is used as the gate insulating film, it is expected that the direct tunnel current will increase as the thickness is reduced. For this reason, the present inventor independently considers that application of a new insulating film, for example, a high dielectric insulating film, which is different from the silicon oxide film which has been used so far, is essential.

  On the other hand, a general semiconductor device tends to use two or more power supply voltages from the viewpoint of consistency with an external power supply voltage.

  However, a MOSFET such as a DRAM has a problem that even if miniaturization progresses, the power supply voltage itself is not scaled as compared with a normal logic circuit.

  For this reason, in the case of a semiconductor device having a plurality of types of power supply voltages, it is required to apply a plurality of gate insulating films having different gate capacitances to MOSFETs used in the semiconductor device.

  In order to give different capacities to the gate insulating film, it is only necessary to form the gate insulating film with different film thicknesses. However, if high dielectric films with different film thicknesses are to be formed, the number of steps increases significantly. In order to carry out stable film formation, ensuring reliability is a major issue.

  On the other hand, a damascene process is usually used in the process of forming the high dielectric insulating film. This is a process in which a dummy pattern is etched back, a metal is embedded in the dummy pattern, and this is cut out. However, such a process is considered to be indispensable in view of the heat resistance of the high dielectric film.

Now, in general, in the damascene gate transistor structure, as shown in the sectional view of FIG. 37, between the n ⁺ layer 31, the metal 33 is disposed as a gate electrode. In this case, since the gate electrode is formed using the CMP technique, if the gate width W is long, dicing is caused, so that the maximum gate width W is limited.

  On the other hand, as shown in the cross-sectional view of FIG. 38, when the silicon oxide film 34 is used as the field oxide film and the metal 33 is disposed between the BPSG layers 35 and 36, the metal 33 portion cannot realize a highly accurate resistance. There is a problem.

  Further, when two types of gate insulating films that are absolutely necessary are formed, a thick insulating film should be formed after forming a high-dielectric film 37 having a small Teff, as shown in the cross-sectional view of FIG. Then, in the thermal process when forming a thick insulating film, the high dielectric film 37 does not have heat resistance, and therefore, there is a problem in that it causes a problem in integration as shown in FIG.

  As described above, in the conventional semiconductor device and the manufacturing method thereof, a new oxide film is formed in place of the thermal oxide film because it is necessary to increase the gate capacity by reducing the gate insulating film as the power supply voltage decreases. The inventor believes that this is necessary. At the same time, in order to cope with a plurality of types of power supply voltages, in a damascene gate process, a plurality of high dielectric insulating films having different gate capacitances can be stably formed with high reliability without increasing the number of steps. I think it is necessary.

  Accordingly, the present invention has been made in view of the above points. In a damascene gate process, some MOSFETs have different gate insulating films by forming silicide without peeling polysilicon. An object of the present invention is to provide a method for manufacturing a semiconductor device, which can form two types of MOSFETs and can realize an LSI having a plurality of types of high-dielectric insulating films that can cope with a damascene gate process.

The method of manufacturing a semiconductor device according to the present invention includes a first MOSFET and a second MOSFET to which a power supply voltage lower than the first MOSFET is supplied, and the first gate insulating film in the first MOSFET is provided in the first MOSFET. In the method of manufacturing a semiconductor device in which the thickness is thicker and the capacitance is smaller than the second gate insulating film in the MOSFET 2,
On the semiconductor substrate, a dummy polysilicon gate electrode used as a mask at the time of ion implantation for forming a diffusion layer is formed in a state sandwiched between sidewalls,
On the first MOSFET side, the dummy polysilicon gate electrode is left and finally used as a gate electrode,
On the second MOSFET side, the dummy polysilicon gate electrode is removed while leaving the sidewall, a high dielectric film is formed in the sidewall, and this high dielectric film is used as a gate electrode.
The present invention provides a method for manufacturing a semiconductor device.
Furthermore, the manufacturing method of the semiconductor device of the present invention is as follows:
In a method for manufacturing a semiconductor device, a first region and a second region are formed on a semiconductor substrate with an element isolation region interposed therebetween, and a MOSFET is formed in each region.
Forming a relatively thin silicon oxide film and a relatively thick polysilicon film on the gate regions of the MOSFET formed in the first region and the MOSFET formed in the second region; A process of forming a silicon nitride film thereon;
Masking a second region and removing the silicon nitride film in the first region;
The mask in the second region is removed, a silicon nitride film is formed on the sidewalls of the polysilicon film in the first region and the second region, and a gate electrode material is sputtered using the silicon nitride film as a mask. , Forming a gate electrode corresponding to the first region by silicidating the same and overlaying the polysilicon film of the first region;
A process of depositing an interlayer film on the whole and polishing it until the gate electrode portion of the first region and the silicon nitride film of the second region are exposed;
The silicon nitride film in the second region is selectively removed to expose the underlying polysilicon layer, and then the polysilicon layer is removed to expose the underlying silicon oxide film. A process of forming a silicon oxide film or nitrogen oxide film containing nitrogen by treating with a reactive gas;
Forming a high dielectric film on the whole and depositing a gate electrode material corresponding to the second region on top of the high dielectric film;
Polishing the gate electrode material and the high dielectric film until the gate electrode in the first region and the entire interlayer film formed between the first region and the second region are exposed; ,
Forming a contact hole in the first region and the second region and performing wiring;
A method for manufacturing a semiconductor device is provided.

Furthermore, the method for manufacturing a semiconductor device according to the present invention includes a first MOSFET and a second MOSFET to which a lower power supply voltage is supplied, and the first gate insulating film in the first MOSFET is provided. In the method of manufacturing a semiconductor device in which the thickness is larger and the capacitance is smaller than the gate insulating film in the second MOSFET,
When a dummy polysilicon gate electrode used as a mask for ion implantation for forming a diffusion layer is formed on a semiconductor substrate so as to be sandwiched between sidewalls, the first MOSFET has the second Formed through an oxide film thicker than the MOSFET,
In the first and second MOSFETs, the dummy polysilicon gate electrode is removed while leaving a sidewall, and a high dielectric film is formed in the sidewall. The high dielectric film is formed on the first and second MOSFETs. In the two MOSFETs, a gate electrode formed through a thick gate oxide film and a thin gate oxide film, respectively,
It is an object of the present invention to provide a method for manufacturing a semiconductor device.
Furthermore, the manufacturing method of the semiconductor device of the present invention is as follows:
A first region and a second region are formed on a semiconductor substrate with an element isolation region interposed therebetween, and a MOSFET having a thick silicon oxide film as a gate insulating film is formed in the first region, In the second region, in the method of manufacturing a semiconductor device in which a MOSFET having a thin silicon oxide film as a gate insulating film is formed,
A process of forming a relatively thick polysilicon film on the whole and further forming a silicon nitride film thereon;
A process of patterning a gate portion of the first region and the second region with a mask and removing a polysilicon film and a silicon nitride film in other portions;
Removing the mask and forming a silicon nitride film on the sidewalls of the polysilicon film in the first region and the second region;
A process of depositing an interlayer film on the entire surface and polishing it until the silicon nitride films in the first region and the second region are exposed;
A process of stripping and removing the silicon nitride film in the first region and the second region, and subsequently stripping and removing the underlying polysilicon layer;
Etching the entire surface, leaving a silicon oxide film in the first region and leaving no silicon oxide film in the second region;
A process of forming a high dielectric film on the whole and depositing a gate electrode material thereon;
Polishing the gate electrode material and the high dielectric film until the entire interlayer film formed between the first region and the second region is exposed;
Forming a contact hole in the first region and the second region and performing wiring;
The present invention intends to provide a method for manufacturing a semiconductor device comprising:

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

Embodiment 1
1 to 21 are process explanatory views for explaining the semiconductor device manufacturing method according to the first embodiment of the present invention step by step in accordance with the CMOS circuit manufacturing method.

  In manufacturing a semiconductor device, an element isolation region is formed on a semiconductor substrate using a well-known process. In this case, the substrate may be P-type or N-type. In the first embodiment, a P-type substrate is used.

  As a method for forming an element isolation region, a so-called selective post-oxidation method in which the element isolation region is selectively oxidized while the element region is covered with a silicon nitride film may be used. A silicon groove is formed only in the element isolation region. Then, a so-called shallow trench isolation method may be used in which the trench is filled with an insulating film to form an element isolation region.

  Here, an embodiment of the present invention will be described based on a method for forming an element isolation region by a Sharon trench isolation method.

  First, as shown in FIG. 1, a buffer oxide film 2 is formed on a P-type substrate 1, and a silicon nitride film 3 is formed thereon. On this, a resist 4 is formed in order to form an element isolation region.

  This process will be described in more detail.

  On the P-type substrate 1 having a resistivity of 1 to 5 Ω · cm formed by the CZ method, a thermal oxide film having a thickness of about 20 Å to about 200 Å is formed as the buffer oxide film 2 by the thermal oxidation method.

  Thereafter, a silicon nitride film 3 is formed to about 1000 angstroms by LPCVD.

  On the structure in which the P-type substrate 1, the buffer oxide film 2, and the silicon nitride film 3 are laminated in this way, a resist 4 having a pattern that covers the element region with a photoresist and exposes the element isolation region by photolithography. Form.

  Subsequently, as shown in FIG. 2, the resist 4 is etched using the resist 4 as a mask, and the resist 4 is removed. Thereafter, oxidation is performed while being covered with the silicon nitride film 3. As a result, a continuous buffer oxide film 2 is formed on the P-type substrate 1.

This process will be described in more detail.
Using the resist 4 pattern as a mask, the silicon nitride film 3 and the buffer oxide film 2 are etched away by a reactive ion etching method (RIE method), then the resist pattern is removed, and the silicon nitride film 3 is used as a mask material. A 3000 angstrom silicon trench is formed. The depth of the silicon groove is set to a depth of about 1 to 2 times the design rule.

  Thus, after forming the silicon trench, the inner wall of the silicon trench is oxidized in an oxygen atmosphere of about 50 Å to about 150 Å at 1000 ° C. to form a buffer oxide film 2 made of a silicon oxide film.

  Here, the buffer oxide film 2 is formed by the thermal oxidation method, but actually, it is not always necessary to oxidize here.

  Next, as shown in FIG. 3, a buried oxide film 5 is formed only in the element isolation region by a so-called selective post-oxidation method including an oxidation step. At this time, the buffer oxide film 2 is also thickened.

  Then, the whole is etched to remove a part of the buried oxide film 5 and the silicon nitride film 3.

  This process will be described in more detail.

  In order to fill the inside of the groove formed in the silicon with an insulating film, a silicon oxide film is deposited to form the buried oxide film 5 by using, for example, LPCVD. The film thickness to be deposited here is about the sum of the depth of the silicon groove and the thickness of the silicon nitride film 3 serving as a mask material.

  Here, as a method for depositing the insulating film, an HDP method, that is, an insulating film deposition method using high-density plasma may be used.

  In the subsequent process, as shown in FIG. 4, the embedded insulating film is polished and planarized by a chemical mechanical polishing method (CMP method).

  Next, a P well 6 and an N well 7 are formed in the P-type substrate 1 by ion implantation. At the same time, the P channel layer 8 and the N channel layer 9 are formed by ion implantation.

  This process will be described in more detail.

  When the polishing is completed from the state of FIG. 3, the cross-sectional shape is such that the buried oxide film 5 still remains in the active region.

  Therefore, by removing the buried oxide film 5 covering the active region using, for example, hot phosphoric acid, a complete element isolation structure is formed.

  Thereafter, after the buffer oxide film 2 covering the element region is peeled off with an NHF solution, the silicon surface is changed to an oxide film 2a of about 100 angstroms by a thermal oxidation method.

Subsequently, ions are implanted into the P well 6 region and the N well 7 region.
Regarding the P-well region, at an acceleration voltage 350KeV from 250KeV with boron, is ion implanted at a dose of about 2 × 10 ¹³ cm ^-2 from 5 × 10 ^12.
In order to adjust the threshold voltage of the high-voltage nMOSFET, channel ion implantation is performed. Here, the threshold voltage was adjusted by implanting 5 × 10 ¹² cm ^{−2 of} boron at 20 KeV.

On the other hand, for the N well, phosphorus is ion-implanted with a dose of about 5 × 10 ¹² to 2 × 10 ¹³ cm ⁻² using an acceleration voltage of about 300 KeV to 500 KeV.

In order to adjust the threshold voltage of the high-voltage pMOSFET, As is ion-implanted at a dose of about 5 × 10 ¹² cm ⁻² at 60 KeV.

  Thereafter, after the formed dummy gate oxide film is peeled off using a dilute HF solution, gate oxidation is first performed to form a gate oxide film for a MOSFET that requires a high power supply voltage. The gate oxide film thickness is about 20 angstroms to 60 angstroms. By using a vertical diffusion furnace and annealing in an oxygen atmosphere at about 750 ° C., an oxide film of about 20 Å to 60 Å can be formed in the element region.

  Alternatively, it may be formed in an oxygen atmosphere at a high temperature of about 1000 ° C. using a fast temperature rising and high temperature furnace (RTO apparatus). Alternatively, a nitride film can be used as the gate insulating film.

  As described above, the P channel layer 8 and the N channel layer 9 are formed.

  Next, as shown in FIG. 5, a polysilicon layer 10 and a silicon nitride film 11 are sequentially formed on the entire surface, and a resist 30 is patterned thereon.

This process will be described in more detail.
After the gate insulating film is formed, a polysilicon layer 10 of about 1000 to 3000 angstroms of polysilicon or amorphous silicon is deposited by LPCVD, for example, and then a silicon nitride film 11 is deposited to about 500 angstroms.
On top of that, a patterned resist 30 is formed by photolithography.

  Subsequently, as shown in FIG. 6, the resist 30 is removed by etching using the resist 30 as a mask. As a result, the silicon nitride film 11 and the polysilicon layer 10 remain.

From this, ion implantation is performed to generate a high voltage N ⁻ MOSn ⁻ layer 12, a high voltage P ⁻ MOSp ⁻ layer 13, a low voltage N ⁻ MOSn ⁻ layer 14, and a low voltage P ⁻ MOSp ⁻ layer 15. To do.

  The size of the gate formed at this time is about 0.25 to 0.1 microns.

  This process will be described in more detail.

  Thereafter, a gate structure in which the silicon nitride film 11 and the polysilicon layer 10 are deposited is formed by an RIE method using a halide as an etching gas using the pattern of the resist 30 as a mask.

  Thereafter, after removing the resist 30, the surface of the polysilicon layer 10 and the surface of the silicon nitride film 11 are improved from 10 angstroms to 50 angstroms as necessary in order to improve the breakdown voltage of the silicon insulating film by using a thermal oxidation method. Angstrom oxidation.

  This post-oxidation step can be omitted.

Thereafter, As or phos is introduced into the NMOS region by ion implantation, and the high-voltage N ⁻ MOSn ⁻ layer 12 and the high-voltage P ⁻ MOSp are formed immediately below the portion of the source and drain regions where the side wall will be formed later. ^- the layer 13, for low-voltage ^N - MOSn ^- layer 14, the low-voltage ^P - forming a layer 15 ^- MOSP.

Here, as the N ⁻ MOSn ⁻ layer 12 for high voltage, for example, As is dosed at 5 × 10 ¹⁴ cm ⁻² at 20 KeV to form an N ⁻ layer.

Further, ions are implanted into the low-voltage N ⁻ MOSn ⁻ layer 14 at 4 × 10 ¹⁴ cm ⁻² at 3 KeV by As.

On the other hand, in order to form the P ⁻ MOSp ⁻ layer 13 for high voltage and the P ⁻ MOSp ⁻ layer 15 for low voltage, a dose amount of 1 × 10 ¹⁴ to 1 × 10 ¹⁵ cm ⁻ is used using BF ₂ or B. Inject ² or so.

In addition, about 5 × 10 ¹⁴ cm ^{−2 of} BF ₂ is implanted into the high voltage MOSFET at an acceleration voltage of 20 KeV.

  Thereafter, an activation process is performed to remove ion implantation damage.

  Next, as shown in FIG. 7, a silicon oxide film layer 16 of about 200 angstroms is deposited on the entire surface by CVD, leaving the silicon oxide film layer 16 with a uniform thickness throughout.

  Subsequently, the entire surface is covered with a photoresist 17, which is patterned by a photolithography method to cover only the low voltage MOSFET portion.

Subsequently, as shown in FIG. 8, the deposited silicon oxide film layer 16 is etched back by the reactive ion etching method using the photoresist 17 as a mask.
Further, as shown in FIG. 9, the photoresist 17 is peeled off, and thereafter, overetching is performed using hot phosphoric acid to remove the silicon nitride film 11 deposited on the polysilicon in the MOSFET portion for high voltage.

  Subsequently, as shown in FIG. 10, the remaining silicon oxide film layer 16 is removed.

  Next, as shown in FIG. 11, a silicon nitride film is deposited on the entire surface by LPCVD or plasma CVD, and RIE (reactive ion etching) is performed on the silicon nitride film, thereby forming a silicon oxide film only on the side wall portion. Alternatively, the silicon nitride film is left to form the silicon nitride film side wall 18. In this case, a typical silicon nitride film has a thickness of about 600 angstroms.

Subsequently, as shown in FIG. 12, ion implantation is performed to generate the p ⁺ layer 19 and the n ⁺ layer 20.
This step is a step of performing ion implantation using As and B into the nMOSFET region and the pMOSFET region for high voltage and low voltage, respectively, using the ion implantation method.

Here, as for As, ion implantation is performed at a dose of about 4 × 10 ¹⁵ cm ⁻² at 25 KeV to 60 KeV.

On the other hand, for B, ion implantation is performed at an acceleration voltage of 5 KeV and a dose of about 4 × 10 ¹⁵ cm ⁻² .

  After that, activation at about 1000 ° C. for 10 seconds is performed with a lamp heating device. In this way, the gate can be activated.

  In more detail, the gate electrode is obtained by implanting As and B into the nMOSFET region and the pMOSFET region, respectively, in the structure in which the silicon nitride film is formed on the sidewall to form the silicon nitride sidewall 18. Impurities are introduced into the portion and the diffusion layer portion.

  Typical acceleration voltages are 10 KeV to 50 KeV for As and 3 KeV to 10 KeV for B.

The dose is about 1 × 10 ¹⁵ cm ^{−2 to} about 7 × 10 ¹⁵ cm ⁻² .
In order to activate the impurities introduced thereafter, a heat treatment is performed at 1000 ° C. for about 10 seconds, for example, by a rapid temperature rising and high temperature method (RTA method).

  By this heat treatment, the impurity introduced into the gate electrode can be activated at the same time, and depletion of the gate electrode can be suppressed.

At this time, the N ⁺ layer portion of the gate layer and the polysilicon gate portion of the P ⁺ layer portion of the high voltage MOSFET are also doped.

  Then, as shown in FIG. 13, as a pretreatment, after a dilute HF treatment, Co is sputtered for about 150 Å, and then a heat treatment is performed in a nitrogen atmosphere at 500 ° C. for 60 seconds to obtain a cobalt silicide layer 21. And a cobalt silicide layer 22 on the gate is formed.

  At that time, the silicidation reaction was performed by stripping unreacted Co with a mixed solution of hydrogen peroxide and sulfuric acid after the heat treatment.

  Thereafter, an attempt was made to lower the resistance of the high resistance layer by annealing at 750 ° C. for about 60 seconds.

  In this step, the on-gate cobalt silicide layer 22 was not formed at this time because the silicon nitride film 11 was present on the gate electrode of the low-voltage MOSFET portion.

  Subsequently, as shown in FIG. 14, a silicon oxide film 23 as an interlayer insulating film is deposited by LPCVD or HDP.

  Thereafter, as shown in FIG. 15, the silicon oxide film 23 is polished by passing a CMP process to expose the cobalt silicide layer 22 on the gate and the silicon nitride film 11, which are the upper surface portions of the gate electrode.

  Next, as shown in FIG. 16, the silicon nitride film 11 is removed, and the polysilicon layer 10 is exposed.

  In this step, the silicon nitride film 11 is removed by reactive RIE etching using conditions having a selectivity with respect to the oxide film and the silicide film.

  Note that the silicon nitride film 11 may be selectively removed by using hot phosphoric acid.

  Further, as shown in FIG. 17, the polysilicon layer 10 is selectively removed by CDE (Chemical Dry Etching).

  Then, after removing the polysilicon film, the exposed silicon surface is treated at 750 ° C. for about 10 seconds by an RTO method using an NO gas, so that the silicon oxide film containing nitrogen is oxidized on the surface. A film 24 is formed. The film thickness is about 6 angstroms.

  Subsequently, as shown in FIG. 18, a tantalum oxide film is formed by a well-known CVD method. The film thickness at this time was 40 Å.

  Thus, after forming tantalum oxide, a TiN film is formed by a CVD method.

As a result, the Ta ₂ O ₅ film 25 is entirely covered, and the titanium nitride film 26 is entirely placed thereon.

Next, as shown in FIG. 19, the titanium nitride film 26 and the Ta ₂ O ₅ film 25 are removed, and a TiN electrode made of the Ta ₂ O ₅ film 25 is subjected to CMP by a CMP method. In this way, the gate electrode can be embedded by CMP.

  Subsequently, as shown in FIG. 20, a silicon oxide film 27 is deposited on the whole as an interlayer film at about 3000 angstroms.

  Finally, as shown in FIG. 21, after opening the contact hole, Ti / TiN is sputtered, and then heat treatment is performed, W is embedded using the CVD method, and etch back is performed using the CMP method. Attach D contact C.

  Subsequently, the process proceeds to a wiring layer process.

Embodiment 2. FIG.
22 to 33 are process explanatory views for explaining the steps of the semiconductor device and the manufacturing method thereof according to the second embodiment of the present invention step by step in accordance with the CMOS circuit manufacturing method.

  FIG. 22 corresponds to FIG. 4, but differs from FIG. 1 in that when forming the gate insulating film, a thick insulating film is formed for the high-voltage MOSFET, and the low-voltage The MOSFET has a structure having a thin gate insulating film.

  As a result, the thickness of the buffer oxide film 2 on the P channel layer 8 and the N channel layer 9 is about 70 angstroms, which is slightly thicker than 30 angstroms in other portions.

  Next, as shown in FIG. 23, a polysilicon layer 10 and a silicon nitride film 11 are sequentially deposited on the entire surface, and a resist 30 is patterned thereon.

  Subsequently, as shown in FIG. 24, the resist 30 is removed by etching using the resist 30 as a mask. As a result, the silicon nitride film 11 and the polysilicon layer 10 remain.

From this, ion implantation is performed, and a high voltage N ⁻ MOSn ⁻ layer 12, a high voltage P ⁻ MOSp ⁻ layer 13, a low voltage N ⁻ MOSn ⁻ layer 14, and a low voltage P ⁻ MOSp ⁻ layer 15 are formed. Generate.

  Next, as shown in FIG. 25, a silicon nitride film is formed on the entire surface, and this is etched to leave a part to form silicon nitride film side walls 18.

Subsequently, as shown in FIG. 26, ion implantation is performed on the diffusion layer region of the MOSFET using the side wall 18 of the silicon nitride film as a mask to generate a p ⁺ layer 19 and an n ⁺ layer 20. Thereafter, activation RTA is performed to form a diffusion layer.

  After that, as shown in FIG. 27, Co is sputtered to perform silicidation RTA, and subsequently, second activation RTA is performed to form Co disilicide, thereby forming cobalt silicide layer 21. Form.

  Subsequently, as shown in FIG. 28, a silicon oxide film 23 serving as an interlayer film is deposited over the entire surface.

  Subsequently, as shown in FIG. 29, CMP (Chemical Mechanical Polishing) is performed to polish the silicon oxide film 23 until the silicon nitride film 11 on the polysilicon layer 10 is exposed.

  Next, as shown in FIG. 30, the silicon nitride film 11 is peeled and removed, and then the polysilicon layer 10 is peeled and removed.

  Further, as shown in FIG. 31, etching is performed with a diluted HF solution, and the buffer oxide film 2 is peeled off. At this time, however, the oxide film still remains in the portion where the thick oxide film is formed.

Subsequently, as shown in FIG. 32, a Ta ₂ O ₅ film 25 after being entirely oxidized is covered, and then a titanium nitride film 26 serving as an electrode is placed on the whole.

Next, as shown in FIG. 33, the titanium nitride film 26 and the Ta ₂ O ₅ film 25 are polished by CMP to form a double structure of the Ta ₂ O ₅ film 25 and the titanium nitride film 26 at the gate portion. .

  Subsequently, an S / D contact is attached through the same steps as in FIGS.

  Through the process as described above, two types of MOSFETs having effectively different gate capacitances can be formed in the high voltage portion and the low voltage portion.

  Through the processes of the first and second embodiments as described above, as shown in the cross-sectional view of FIG. 34, the gate having the double structure of the polysilicon layer 10 and the cobalt silicide layer 22 on the gate is changed to the high voltage portion. Can be formed in the MOSFET. According to such a structure, a MOSFET having a wide gate width can be realized.

Further, through the processes of the first and second embodiments, a gate having a double structure of a Ta ₂ O ₅ film 25 and a titanium nitride film 26 which are high dielectric films as shown in the sectional view of FIG. It can be realized in a voltage MOSFET.

  Further, as shown in the sectional view of FIG. 36, the double structure of the polysilicon layer 10 and the on-gate cobalt silicide layer 22 can provide a highly accurate resistance value.

[The invention's effect]
As described above, according to the present invention, two types of gate insulating films can be stably realized in a relatively simple process, and a portion having a thick insulating film is a silicide that is a normal polysilicon electrode. Since the structure is adopted, a MOSFET having a wide gate width can be realized, two kinds of gate insulating films can be easily realized, and a high-precision resistor can be realized as a resistor.

FIG. 6 is an explanatory diagram of one process showing the method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 6 is an explanatory diagram of one process showing the method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 6 is an explanatory diagram of one process showing the method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 6 is an explanatory diagram of one process showing the method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 6 is an explanatory diagram of one process showing the method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 6 is an explanatory diagram of one process showing the method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 6 is an explanatory diagram of one process showing the method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 6 is an explanatory diagram of one process showing the method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 6 is an explanatory diagram of one process showing the method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 6 is an explanatory diagram of one process showing the method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 6 is an explanatory diagram of one process showing the method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 6 is an explanatory diagram of one process showing the method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 6 is an explanatory diagram of one process showing the method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 6 is an explanatory diagram of one process showing the method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 6 is an explanatory diagram of one process showing the method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 6 is an explanatory diagram of one process showing the method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 6 is an explanatory diagram of one process showing the method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 6 is an explanatory diagram of one process showing the method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 6 is an explanatory diagram of one process showing the method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 6 is an explanatory diagram of one process showing the method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 6 is an explanatory diagram of one process showing the method for manufacturing the semiconductor device according to the first embodiment of the present invention. One process explanatory drawing which shows the manufacturing method of the semiconductor device of Embodiment 2 of this invention. One process explanatory drawing which shows the manufacturing method of the semiconductor device of Embodiment 2 of this invention. One process explanatory drawing which shows the manufacturing method of the semiconductor device of Embodiment 2 of this invention. One process explanatory drawing which shows the manufacturing method of the semiconductor device of Embodiment 2 of this invention. One process explanatory drawing which shows the manufacturing method of the semiconductor device of Embodiment 2 of this invention. One process explanatory drawing which shows the manufacturing method of the semiconductor device of Embodiment 2 of this invention. One process explanatory drawing which shows the manufacturing method of the semiconductor device of Embodiment 2 of this invention. One process explanatory drawing which shows the manufacturing method of the semiconductor device of Embodiment 2 of this invention. One process explanatory drawing which shows the manufacturing method of the semiconductor device of Embodiment 2 of this invention. One process explanatory drawing which shows the manufacturing method of the semiconductor device of Embodiment 2 of this invention. One process explanatory drawing which shows the manufacturing method of the semiconductor device of Embodiment 2 of this invention. One process explanatory drawing which shows the manufacturing method of the semiconductor device of Embodiment 2 of this invention. Sectional drawing which shows an example of the gate structure of the semiconductor device implement | achieved by the manufacturing method of the semiconductor device of this invention. Sectional drawing which shows the other example of the gate structure of the semiconductor device implement | achieved by the manufacturing method of the semiconductor device of this invention. Sectional drawing which shows an example of the structure of a resistor of the semiconductor device implement | achieved by the manufacturing method of the semiconductor device of this invention. Sectional drawing which shows one example of the gate structure of the semiconductor device implement | achieved by the manufacturing method of the conventional semiconductor device. Sectional drawing which shows another example of the gate structure of the semiconductor device implement | achieved by the manufacturing method of the conventional semiconductor device. Sectional drawing explaining the film-forming process by the manufacturing method of the conventional semiconductor device. Sectional drawing explaining the film-forming process by the manufacturing method of the conventional semiconductor device.

Explanation of symbols

1 P-type substrate 2 Buffer oxide film 3 Silicon nitride film 4 Resist 5 Embedded oxide film 6 P well 7 N well 8 P channel layer 9 N channel layer 10 Polysilicon layer 11 Silicon nitride film 12 High voltage N ⁻ MOSn ⁻ layer 13 High voltage P ^- MOSp ^- layer 14 Low voltage N ^- MOSn ^- layer 15 Low voltage P ^- MOSp ^- layer 16 Silicon oxide film layer 17 Photoresist 18 Silicon nitride sidewall 19 p ⁺ layer 20 n ⁺ layer 21 Cobalt silicide Layer 22 Cobalt silicide layer on gate 23 Silicon oxide film 24 No oxide film 25 Ta ₂ O ₅ film 26 Titanium nitride film 27 Silicon oxide film 30 Resist

Claims (4)

A first MOSFET and a second MOSFET to which a lower power supply voltage is supplied, and the first gate insulating film in the first MOSFET is replaced with the second gate insulating film in the second MOSFET. In a method for manufacturing a semiconductor device having a larger thickness and a smaller capacitance,
On the semiconductor substrate, a dummy polysilicon gate electrode used as a mask at the time of ion implantation for forming a diffusion layer is formed in a state sandwiched between sidewalls,
On the first MOSFET side, the dummy polysilicon gate electrode is left and finally used as a gate electrode,
On the second MOSFET side, the dummy polysilicon gate electrode is removed while leaving the sidewall, a high dielectric film is formed in the sidewall, and this high dielectric film is used as a gate electrode.
A method for manufacturing a semiconductor device. In a method for manufacturing a semiconductor device, a first region and a second region are formed on a semiconductor substrate with an element isolation region interposed therebetween, and a MOSFET is formed in each region.
Forming a relatively thin silicon oxide film and a relatively thick polysilicon film on the gate regions of the MOSFET formed in the first region and the MOSFET formed in the second region; A process of forming a silicon nitride film thereon;
Masking a second region and removing the silicon nitride film in the first region;
The mask in the second region is removed, a silicon nitride film is formed on the sidewalls of the polysilicon film in the first region and the second region, and a gate electrode material is sputtered using the silicon nitride film as a mask. , Forming a gate electrode corresponding to the first region by silicidating the same and overlaying the polysilicon film of the first region;
A process of depositing an interlayer film on the whole and polishing it until the gate electrode portion of the first region and the silicon nitride film of the second region are exposed;
The silicon nitride film in the second region is selectively removed to expose the underlying polysilicon layer, and then the polysilicon layer is removed to expose the underlying silicon oxide film. A process of forming a silicon oxide film or nitrogen oxide film containing nitrogen by treating with a reactive gas;
Forming a high dielectric film on the whole and depositing a gate electrode material corresponding to the second region on top of the high dielectric film;
Polishing the gate electrode material and the high dielectric film until the gate electrode in the first region and the entire interlayer film formed between the first region and the second region are exposed; ,
Forming a contact hole in the first region and the second region and performing wiring;
A method for manufacturing a semiconductor device, comprising: A first MOSFET and a second MOSFET to which a lower power supply voltage is supplied, and the first gate insulating film in the first MOSFET is made more than the gate insulating film in the second MOSFET. In the method of manufacturing a semiconductor device in which the thickness is large and the capacitance is small,
When a dummy polysilicon gate electrode used as a mask for ion implantation for forming a diffusion layer is formed on a semiconductor substrate so as to be sandwiched between sidewalls, the first MOSFET has the second Formed through an oxide film thicker than the MOSFET,
In the first and second MOSFETs, the dummy polysilicon gate electrode is removed while leaving a sidewall, and a high dielectric film is formed in the sidewall. The high dielectric film is formed on the first and second MOSFETs. In the two MOSFETs, a gate electrode formed through a thick gate oxide film and a thin gate oxide film, respectively,
A method for manufacturing a semiconductor device. A first region and a second region are formed on a semiconductor substrate with an element isolation region interposed therebetween, and a MOSFET having a thick silicon oxide film as a gate insulating film is formed in the first region, In the second region, in the method of manufacturing a semiconductor device in which a MOSFET having a thin silicon oxide film as a gate insulating film is formed,
A process of forming a relatively thick polysilicon film on the whole and further forming a silicon nitride film thereon;
A process of patterning a gate portion of the first region and the second region with a mask and removing a polysilicon film and a silicon nitride film in other portions;
Removing the mask and forming a silicon nitride film on the sidewalls of the polysilicon film in the first region and the second region;
A process of depositing an interlayer film on the entire surface and polishing it until the silicon nitride films in the first region and the second region are exposed;
A process of stripping and removing the silicon nitride film in the first region and the second region, and subsequently stripping and removing the underlying polysilicon layer;
Etching the entire surface, leaving a silicon oxide film in the first region and leaving no silicon oxide film in the second region;
A process of forming a high dielectric film on the whole and depositing a gate electrode material thereon;
Polishing the gate electrode material and the high dielectric film until the entire interlayer film formed between the first region and the second region is exposed;
Forming a contact hole in the first region and the second region and performing wiring;
A method for manufacturing a semiconductor device, comprising:

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