JP2001168322A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which is restrained from varying in Vth due to a short channel effect or a lack of uniformity in characteristics induced in a manufacturing process. SOLUTION: A first conductivity-type first semiconductor region is provided inside a semiconductor, and a second conductivity-type second semiconductor region is provided between the first semiconductor region and the surface of the semiconductor so as to make first conductivity-type impurities contained in the semiconductor 1/4 or below as low in concentration as the first conductivity-type impurities contained in the first conductivity-type first semiconductor region. An insulating film and a conductor are provided above the second semiconductor region, and a second conductivity-type third semiconductor region and a fourth semiconductor region are provided coming into contact with the surface of the semiconductor and the side of the second semiconductor region. By this setup, a semiconductor device of this constitution can be set more uniform in net impurity concentration.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device such as a metal / insulator / semiconductor / field effect transistor (MISFET) for suppressing variations in threshold voltage (Vth) due to short channel effects and manufacturing variations, and a method of manufacturing the same. In particular, the present invention relates to the shape of an impurity profile such as a channel impurity profile and a counter impurity profile of a MISFET.

[0002]

2. Description of the Related Art Conventionally, with the miniaturization of MISFETs, the variation in channel impurity profile giving to Vth has increased, and a warning has been issued about a failure to give circuit characteristics.

[0003] Complementary metal / oxide / semiconductor (CMO)
S) In the case of a pMOSFET used in a circuit, when an n + polysilicon gate is used, counter doping is performed on the channel surface. With this doping, an impurity layer of a conductivity type different from the channel impurity is provided in the channel region, and a buried channel is formed. n + polysilicon gate pMOS
The FET buried channel is strongly affected by the short channel effect unless a shallow counter-doped layer is used. Here, when the gate length is reduced to the limit of lithography control due to miniaturization, the ratio of variation in gate length to gate length increases. In addition, variations in electrical characteristics due to the short channel effect occur, causing a decrease in the yield of CMOS circuits. There is also a demand for lowering the power supply voltage with miniaturization. V to reduce the power supply voltage
th may be reduced. However, it is effective to increase the substrate concentration in order to suppress the short channel effect. Generally, when a high substrate concentration is used, Vth increases. In this case, high-quality electrical characteristics cannot be obtained even if the size is reduced.

Therefore, by increasing the concentration of the counter-doped layer on the surface of the substrate, the concentration of the substrate is increased, and the effect of suppressing the short channel effect is maintained, while the buried channel pMO is removed.
In order to reduce the Vth of the SFET, a highly doped counter-doped layer must be formed extremely shallow. However, since the gate insulating film is subjected to thermal diffusion during a high-temperature step such as impurity activation annealing, it is difficult to form a highly doped counter-doped layer extremely shallow.

In order to form a buried channel by counter-doping a channel impurity layer and to provide an impurity layer of the opposite conductivity type, a p-type impurity is applied to the n-type impurity distribution having a gentle profile so as to eliminate the surface portion. Efforts have been made to introduce it shallowly (IC Kizilly
alli et al., n + -Polysilicon Gate
PMOSFET's with Indium Do
ped Burried-Channels, IEEE
Electron Device Letters, V
ol. 17, pp 46-49, 1996). When a shallow net p-type region is formed by introducing a shallow p-type impurity as a counter dopant, a channel is formed closer to the surface than when deeply introduced, and an increase in the effective thickness of the gate insulating film or This is because characteristic deterioration such as deterioration of the short channel effect can be prevented. For this purpose, the concentration of the n-type impurity, which is the channel impurity near the pn junction position, is high, and a high p-type impurity concentration is required to eliminate this. But,
It is known that Vth has a large variation in a MOSFET having a buried channel structure, such as a pMOSFET having a buried channel formed by an n ⁺ polysilicon gate electrode.

[0006] Further, even in the case of an nMOSFET, a low Vth is required as the power supply voltage is lowered, and a low Vth can be obtained by using counter doping even under a high channel impurity concentration. In particular, development has been promoted for the purpose of eliminating the drawbacks of poly gates, such as reducing gate resistance in response to miniaturization. In case of metal gate using mold material for gate electrode, nMOSFET
, The desired low V under the high channel impurity concentration that withstands the short channel effect due to the high work function.
embedded channel structures have been used to implement the A. Chatterjee et al., CMOS
Metal ReplacementGate Tra
nsistors using Tantalum P
entoxide Gate Insulator, I
EDM 98, pp777-780, 1998). However, few examples of realizing a low Vth with a metal gate have been reported, and there is an assertion that a surface channel should be used even with a metal gate because the Vth variation is generally large in a buried channel. Channel profile is a major issue.

[0007]

As described above, it is known that the MOSFET having the buried channel structure has a large variation in Vth, but the cause of the variation has not always been clarified. Therefore, the inventors have
We decided to clarify the cause of the variation.

FIG. 1 shows an nMO for forming a buried channel.
FIG. 4 is a schematic diagram of a typical impurity profile in a semiconductor immediately below a gate oxide film of an SFET. The horizontal axis represents the distance from the interface between the gate oxide film and the semiconductor, and the vertical axis represents the impurity concentration. The channel impurity profile 1 representing the p + region of the channel impurity can be considered to be constant at a high concentration from the semiconductor interface to the inside. Also, the counter impurity profile 2 representing the n + impurity layer of the different conductivity type subjected to the counter doping exists to a depth of 10 nm from the semiconductor interface, and the concentration can be considered to be constant at a higher concentration than the p-type impurity concentration of the channel impurity. In this way, the following Vth and its variation were simulated by considering the impurity profile.

FIG. 2 shows a simulation result of Vth with respect to the counter impurity concentration and Vth variation due to the variation of the counter impurity profile when a typical buried channel structure is used for a metal gate. Assuming a power supply voltage of 1 V, Vth was obtained by applying 1 V to the drain electrode. Here, the concentration of the channel impurity profile 1 in FIG. 1 is 2 × 10 ¹⁸ cm
^-3 . The horizontal axis is the counter impurity concentration,
The vertical axis represents Vth and the change amount of Vth due to a change in the shape of profile 2 in FIG. The + mark represents Vth.
□ indicates that the profile 2 existing up to a depth of 10 nm is 0.
Vt when it becomes shallow by 5 nm and the depth reaches 9.5 nm
h represents the amount of change. The mark Δ indicates the amount of change in Vth when the density of profile 2 is reduced by 2%. The reason why the width of the change is set in this manner is that manufacturing variations due to semiconductor manufacturing equipment and the like are assumed. From this, low V
It can be seen that the counter impurity concentration needs to be as high as 5.3 × 10 ¹⁸ cm ⁻³ in order to achieve the threshold value th of, for example, 0.4 V. At this concentration, the variation in Vth due to the variation in the depth of the mark is 5
Reaches 0 mV. It was found that the variation of Vth due to the variation of the density of the mark reached 10 mV.

The reason for the large variation from the simulation is considered as follows. Here, nMI
The case of the SFET will be described as an example.

The Vth of a MISFET is determined by a net impurity profile irrespective of the respective profiles of channel impurities and counter impurities. Here, the “net impurity profile” is a profile of the net impurity concentration, and the “net impurity concentration” is the absolute value of the difference between the p-type and n-type impurity concentrations at the same position. Here, the impurity concentration means the concentration of electrically active impurities, that is, the active concentration, but does not mean the chemical impurity atomic concentration. In general, impurities introduced into a semiconductor and acting as p-type and n-type impurities have different rates of electrical activation (activation rates) depending on the substance type, concentration, and the like. In the description range of the present application, the concentration does not mean the chemical impurity concentration, but both the “concentration” and the “active concentration” mean the “concentration of the electrically activated impurity”. Therefore, for example, the “absolute value of the difference between the impurity concentrations” indicates the p-type impurity concentration when the p-type impurity concentration is greater than the n-type impurity concentration, and conversely, the n-type impurity concentration is greater than the p-type impurity concentration. Time indicates an n-type impurity concentration. This is because charges of the same concentration of bipolar impurities near the same position cancel each other out and do not contribute to the net charge. During the operation of the transistor, the end of the depletion layer extends toward the back of the substrate as the gate bias is applied,
The space charge due to the net impurity in the silicon region shallower than the end of the depletion layer forms an electric field and determines the operation of the transistor. That is, as the end of the depletion layer is extended, carriers (in this case, holes) are removed to the back of the substrate and the depletion layer is expanded, and the charge of carriers (electrons or holes) in the space charge corresponding to the net impurity concentration in this region. As a result, the portion that is not erased contributes to the formation of the electric field of the channel. Here, the depletion layer is defined as a region where the carrier concentration is lower than the impurity concentration by 10% or more.

In order to suppress the short channel effect, the depletion layer needs to stop near the substrate surface, and therefore, a high concentration of channel impurities is required. In order to eliminate the high-concentration channel impurity region on the substrate surface, it is necessary to introduce a high-concentration counter impurity. Since the concentration of the profile 2 of the counter impurity is high, it is considered that the variation in the depth and the variation in the concentration give variation to the position of the pn junction and the net profile of the p-type region near the junction. Further, since the concentration of the channel impurity profile 1 is also high, it is considered that variation in the concentration also causes variation in the net profile of the pn junction position and the n-type region. As a result, if the absolute value of the concentration variation of the channel impurity and the counter impurity is large, the net concentration variation near the pn junction position is large. Vth depends on the net density profile. If at least one of the p-type impurity and the n-type impurity has a non-uniform profile, it is considered that the net profile varies and Vth tends to fluctuate. The buried channel has a V
The reason for the large variation in th is that V
It can be explained that the channel structure determined by the two profiles is more likely to fluctuate and the net profile is more likely to fluctuate than the surface-type transistor whose th is determined.

[0013] The above problem is caused by introducing the n-type impurity at a very shallow or low concentration, by controlling the work function of the gate electrode material, or by applying a substrate bias to make the channel buried. However, even in the case of the surface type or the boundary between the surface type and the buried type, there is a problem similarly included in a transistor having a pn junction in a channel.

In general, when a metal or a metal compound is used for the gate electrode, the work function thereof is located in the middle of the band gap of silicon, so that the Vth of the MISFET becomes high. In order to lower this Vth in accordance with the demand for miniaturization, the buried channel is used as described above. However, the buried channel generally has a large variation in Vth, and therefore, in an integrated circuit which has been miniaturized, there is not enough buried channel. The yield could not be predicted. On the other hand, if a metal having a work function close to the end of the silicon band gap is developed and used to avoid using a buried channel, the metal used for a CMOS circuit is different for an nMISFET and a pMISFET. Since a metal material is used (dual gate), not only the assumed manufacturing process becomes complicated, but also a great development cost is required. Thus, the metal gate MIS
In developing FETs for use in CMOS integrated circuits, it has not been possible to find an appropriate solution for a combination of a work function value and a channel profile that meets the demand for miniaturization.

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a semiconductor device that suppresses a variation in Vth due to a short channel effect and manufacturing variations.

It is another object of the present invention to provide a method of manufacturing a semiconductor device which suppresses a variation in Vth due to a short channel effect and manufacturing variations.

[0017]

Means for Solving the Problems Next, the present inventors have proposed that Vt
Based on the cause of the variation in h, an impurity profile with a small variation in Vth was considered.

First, attention was paid to the fact that when two profiles of p-type and n-type impurities were overlapped, the variation of Vth was likely to increase, and an attempt was made to reduce the variation of Vth by optimizing one profile, that is, the channel impurity profile.

FIG. 3 shows an nMOS forming a surface channel.
FIG. 4 is a schematic diagram of a channel impurity profile of a semiconductor immediately below a gate oxide film of an FET. The horizontal axis represents the distance from the interface between the gate oxide film and the semiconductor, and the vertical axis represents the concentration of the channel impurity. First, the case where the concentration is high and constant in the p + region throughout the depth direction of the substrate will be considered. The channel impurity profile is represented by line segment 4 and dotted line 3. As the miniaturization advances, the variation in Vth increases due to the short channel effect. The short channel effect is achieved by reducing the thickness of the gate insulating film,
It can be suppressed by increasing the substrate concentration. The short channel effect can also be effectively suppressed by reducing the depth of the diffusion layer of both the source and the drain, or particularly the drain. However, here, the effect of channel impurities on the short channel effect is particularly considered, and the source / drain structure is fixed. The source / drain diffusion layer junction depth used in the simulation is 35 nm. Next, as miniaturization progresses, a low power supply voltage is required based on a demand for low power consumption, and a low Vth is required accordingly.
In order to realize a low Vth, the concentration on the surface of the substrate may be reduced. That is, in order to satisfy the two requirements, the dotted line 3 of the channel impurity profile 1 is
It is thought that it is sufficient to change to step 6 and to make a step-like profile. Note that the channel impurity profile 1 may have a shape like a dotted line 7. This is because the desired effect of reducing the short channel effect can be obtained when the line segment 4 has a length equal to or more than a certain value.

Here, Vt of step-like profile 1
In order to evaluate the easiness of variation of h, an attempt was made to quantitatively evaluate the degree of the short channel effect that directly affects the variation of Vth. FIG. 4 is a diagram conceptually showing a variation in Vth with respect to a variation in gate length (L). The horizontal axis is the gate length and the vertical axis is Vth. Solid line 8 represents Vth with respect to the gate length. As the gate length decreases, Vth tends to decrease, and this tendency is the short channel effect. Also, the slope of the solid line 8 tends to increase as the gate length becomes shorter, and it is considered that the magnitude of this slope indicates the degree of the short channel effect. Therefore, the short channel effect (Sh
ort Channel Effect: SCE) A new evaluation value is considered. The SCE range is represented by equation (1).

(SCE range: L) = Vth (L _{+ 8%} ) − Vth (L− _8% ) (1) where L is an arbitrary gate length, and L _{+ 8%} is a gate length. This is a gate length obtained by increasing L by + 8%, and Vth (L
_{+ 8%} ) is Vth at L _{+ 8%} . L- _{8 %} is a gate length obtained by reducing the gate length L by -8%, and Vth
(L- _8% ) is Vth at L _{- 8%} . In addition,
In the equation (1), 8% is set, but it is not limited to this and can be set. If it is set within the range of the variation of the gate length L generated in the manufacturing process of the MOSFET, the variation of Vth caused by the manufacturing process can be evaluated. is there.

FIG. 4 verifies that the degree of the short channel effect can be effectively evaluated in the SCE range. The SCE range for the gate length L1 is represented by the range R1 on the Vth axis, and the SCE range for the gate length L2 is represented by the range R2. The range R2 is larger than the range R1, and it is considered that the SCE range can certainly quantify the short channel effect. If the solid line 8 can be changed to the dotted line 9 or the dotted line 10 by changing the impurity profile, for example, the impurity profile that minimizes the SCE range while keeping the gate length L2 the same is the profile that the inventors need. Can be determined. The magnitude of the Vth variation caused by the variation in the channel impurity profile differs depending on the structure, and even in the case of a transistor having a pn junction in a channel, it varies depending on the gate material and the setting of Vth determined according to the channel impurity profile.

FIG. 5 shows the relationship between Vth and SCE range with respect to the distance from the semiconductor surface to the step (depth indicated by the solid line 5 in FIG. 3) when the step profile shown in FIG. 3 is used for a metal gate. It is a graph which shows a relationship.
This relationship was determined by simulation. Here, FIG.
The concentration indicated by the solid line 4 in the channel impurity profile of FIG.
× 10 ¹⁸ cm ⁻³ , and the concentration indicated by the solid line 6 is 1 × 1
0 ¹⁷ cm ⁻³ . The gate length is 95 nm. The horizontal axis is the depth of the low concentration layer on the surface, that is, the distance from the semiconductor surface to the step (solid line 5), and the vertical axis is V
th and the SCE range. □ represents Vth. A mark represents the SCE range. Thus, as the depth of the low concentration layer on the surface increases, Vth decreases and S
It can be seen that the CE range increases. In addition, low Vth
In order to achieve, for example, 0.4 V, the depth of the low concentration layer on the surface only needs to be 50 nm, and it has been found that the SCE range reaches 70 mV at this depth. Further, from the slope of Vth when the depth of the low-concentration layer on the surface is 50 nm, the amount of change in Vth when the depth of the low-concentration layer on the surface decreases from 50 nm to 2.5 nm and becomes 47.5 nm is: It turns out that it is 14 mV. Since the amount of change in Vth with respect to the change in depth at Vth of 0.4 V in FIG. 2 was 50 mV, it can be seen that the amount of change in Vth was reduced to one third or less. When the concentration of the low-concentration layer on the surface indicated by the solid line 6 in FIG. 3 is set to less than 1 × 10 ¹⁷ cm ⁻³ , the Vth slightly decreases, but the simulation result in FIG. 5 hardly changes. Accordingly, it is considered that the variation in Vth is smaller in the step-like profile in FIG. 3 than in the profile in FIG. As described above, in the step-like profile of FIG. 3, Vth is less likely to vary with respect to the variation of the profile shape than the profile of FIG.
It was thought that the SCE range needed to be further reduced.

The inventors have conducted intensive studies and invented a new semiconductor device.

That is, a first feature of the present invention for solving the above problems is that a first semiconductor region of a first conductivity type provided inside a semiconductor, and the first semiconductor region and the surface of the semiconductor. A second conductivity type second semiconductor region, provided between the first semiconductor region and the first conductivity type impurity concentration, wherein the second conductivity type impurity concentration is less than ４ of the first conductivity type impurity concentration of the first semiconductor region; An insulating film provided above the second semiconductor region on the semiconductor surface, a conductor provided on the insulating film, and a second conductive type second conductive type including the semiconductor surface and in contact with the side surface of the second semiconductor region. 3 is a semiconductor device having a semiconductor region and a fourth semiconductor region of the second conductivity type including a semiconductor surface and in contact with a side surface of the second semiconductor region.

As a result, the impurity concentration at the bonding position or near the substrate surface can be reduced, and the net impurity concentration and p
Alternatively, the difference from the n-type impurity concentration can be reduced. Then, the influence of the variation in the p or n-type impurity concentration on the net impurity concentration is reduced, and the Vth variation is suppressed. In particular, in a metal gate transistor in which it is necessary to provide a pn junction in a channel because of a high work function value, it is possible to suppress variation in Vth. Furthermore, by using the damascene gate process,
The above impurity profile can be manufactured. P and nMIS with metal gate according to the invention
A high-performance semiconductor integrated circuit chip can be manufactured with a high yield by mounting an FET.

A first feature of the present invention is that the profile of the impurity concentration distribution of the first conductivity type forming the first semiconductor region toward the semiconductor surface is sharply reduced in concentration, and the concentration ratio per 3 nm is reduced. It is effective to have a portion smaller than 0.9. As a result, a region having a high p-type impurity concentration is secured to suppress the short channel effect, and
The difference between the net profile of the n-type region and the n-type impurity profile of this region can be reduced, and Vth variation can be suppressed.

A first feature of the present invention is that the impurity concentration of the second conductivity type at the end of the second semiconductor region on the semiconductor inside side is:
This is more effective when the maximum concentration of the impurity of the first conductivity type in the depletion layer during operation of the semiconductor device is smaller than half the maximum concentration. Thus, for example, a region having a high p-type impurity concentration is ensured, the short channel effect is suppressed, the n-type impurity concentration is reduced at the same time, and at the same time, the location dependence of the n-type impurity distribution is reduced to reduce the n-type impurity concentration. Variations in the distribution can be suppressed, whereby variations between the net n-type region distribution and the net p-type region distribution can be suppressed, and Vth variations can be suppressed.

A first feature of the present invention is that the concentration gradient of the impurity of the second conductivity type is smaller than the concentration gradient of the impurity of the first conductivity type at the end inside the semiconductor in the second semiconductor region. Is more effective. This provides the same advantages as described above.

A first feature of the present invention is that the concentration of the second conductivity type impurity at the end of the depletion layer during the operation of the semiconductor device is the maximum value of the concentration of the first conductivity type impurity in the depletion layer. It is more effective if it is smaller than a quarter. As a result, the n-type impurity concentration in the first semiconductor region, for example, the region of the p-type impurity region that affects the characteristics of the MISFET is reduced, and the net p-type and p-type impurity profiles in this region are reduced. And Vth variation can be suppressed.

A first feature of the present invention is that the peak position of the impurity profile of the second conductivity type forming the second semiconductor region is located closer to the semiconductor surface than the end of the second semiconductor region on the semiconductor inner side. Positioning is more effective. Thereby, the main distribution of the second conductivity type, for example, the n-type impurity is separated from the p-type impurity distribution, and at the same time, the difference between the profile of the net n-type region and the n-type impurity profile of this region is reduced. However, Vth variation can be suppressed.

A first feature of the present invention is that, at the peak position of the impurity profile of the second conductivity type forming the second semiconductor region, the impurity concentration of the first conductivity type is 2% of the impurity concentration of the second conductivity type. It is more effective if it is smaller than one part. Thus, the difference between the net n-type region profile and the n-type impurity profile of this region is reduced by lowering the p-type impurity concentration at the peak position of the second conductivity type, for example, the n-type impurity distribution. Then V
th variation can be suppressed.

A first feature of the present invention is more effective when the impurity concentration of the first conductivity type is smaller than one fourth of the impurity concentration of the second conductivity type on the semiconductor surface. As a result, the first conductivity type, for example, the p-type impurity concentration on the substrate surface which strongly affects Vth is reduced.
By making the concentration lower than the n-type impurity concentration, the difference between the net n-type region profile and the n-type impurity profile here can be reduced, and Vth variation can be suppressed.

A first feature of the present invention is that the concentration of the impurity of the second conductivity type at the semiconductor surface is the concentration of the impurity of the second conductivity type at the end of the second semiconductor region on the semiconductor inside side, or The ratio of the concentration of the impurity of the second conductivity type in the second semiconductor region to the maximum value is smaller than 2 and the ratio of the concentration of the impurity of the second conductivity type at this end is smaller than 1/2. Greater is more effective. This makes it possible to reduce the location dependence of the impurity distribution of the second conductivity type, for example, n-type, so as to obtain a gentle distribution, thereby suppressing the variation in the n-type impurity distribution, thereby reducing the net n-type region. Variation between the distribution and the net p-type region distribution can be suppressed, Vth variation can be suppressed, and Vth control can be facilitated.

A first feature of the present invention is that the profile of the impurity concentration distribution of the first conductivity type forming the first semiconductor region toward the semiconductor surface is steeply reduced in concentration, and the concentration ratio per 1 nm is reduced. It is more effective to have a portion smaller than 0.9. Thereby, the first conductivity type,
For example, it is possible to secure a region having a high p-type impurity concentration, suppress the short channel effect, and at the same time enhance the effect of reducing the n-type impurity concentration, and at the same time, enhance the effect of suppressing Vth variation.

The first feature of the present invention is more effective when the impurity of the first conductivity type is indium.
Thus, in the case of an nMISFET, a p-type impurity distribution can be formed by utilizing the characteristics of indium having a small diffusion coefficient.

The first feature of the present invention is more effective when the impurity of the second conductivity type is phosphorus. This makes it possible to manufacture an nMISFET having a gentle n-type impurity distribution by utilizing the feature of phosphorus having a large diffusion coefficient.

The first feature of the present invention is even more effective when the impurity of the second conductivity type is antimony or arsenic. This makes it possible to realize an nMISFET having an n-type impurity distribution having a narrow distribution width by utilizing the characteristics of antimony having a small diffusion coefficient.
Vt with a small Vth variation after realizing an n-type impurity distribution with a small overlap with the n-type impurity distribution and securing a sufficient net p-type impurity concentration to suppress the short channel effect
h can be manufactured.

The first feature of the present invention is more effective when the impurity of the first conductivity type is antimony or arsenic. Thus, in the case of a pMISFET, an n-type impurity distribution can be formed by utilizing the characteristics of antimony or arsenic having a small diffusion coefficient.

The first feature of the present invention is more effective when the impurity of the second conductivity type is boron. As a result, a pMISFET having a gentle p-type impurity distribution is utilized by utilizing the feature of boron having a large diffusion coefficient.
Can be manufactured.

The first feature of the present invention is more effective when the second conductivity type impurity is indium.
This makes it possible to take advantage of the characteristics of indium having a small diffusion coefficient to make pM having a p-type impurity distribution having a narrow distribution width.
An ISFET can be manufactured.

The first feature of the present invention is more effective when the conductor is a metal or a metal compound. Thus, the resistance of the gate electrode can be reduced, and the increase in the effective gate insulating film thickness due to the depletion of the interface, unlike a polygate, can be prevented. In addition, a MISFET having a low Vth that is resistant to the short channel effect can be realized with a small Vth variation.

A first feature of the present invention is that a semiconductor device according to the first feature of the present invention in which the first conductivity type is p-type and a semiconductor device in which the first conductivity type is n-type are provided. It is more effective to mount the semiconductor device which is one of the features. As a result, one or both of a metal gate nMISFET and a pMISFET that have a low gate resistance and do not cause an increase in the effective thickness of the gate insulating film like a polygate can be manufactured so that the variation in Vth is reduced. A semiconductor integrated circuit chip with low power consumption and high performance can be realized.

A first feature of the present invention is the first feature of the present invention in which the first conductivity type is p-type and the conductor of the semiconductor device is the first feature of the present invention, and the first conductivity type is n-type in the present invention. It is more effective that the conductor of the semiconductor device, which is the first feature, is made of the same metal or metal compound. As a result, pMISF can be formed by one kind of gate electrode material.
By manufacturing both the ET and the nMISFET with a metal gate, the manufacturing process can be simplified and a semiconductor integrated circuit chip can be realized at low cost.

A second feature of the present invention is that a concentration profile in which the concentration of the second region deeper than the concentration of the first region including the semiconductor surface is at least four times higher than that of the first region is formed by impurities of the first conductivity type. A first step of distributing impurities of the second conductivity type in the first region beyond the concentration of the first region; a third step of forming an insulating film on the semiconductor surface; A method of manufacturing a semiconductor device, comprising: a fourth step of forming a conductor on an insulating film; and a fifth step of forming a second conductivity type semiconductor region including a semiconductor surface on both sides of the second region. It is. Thus, a semiconductor device having a steep or narrow width impurity profile can be realized.

A second feature of the present invention is that a fifth step is first performed, then an opening for embedding a conductor is formed, and then the first step is performed through the opening to the first step. This is performed by introducing impurities of the conductivity type into the semiconductor.
It is more effective to carry out the step and the fourth step. This makes it possible not only to form a conductor serving as a gate electrode by the damascene method, but also to reduce the number of heat steps applied to the channel impurity profile formed in the first step, thereby realizing an impurity profile with a sharp concentration change. .

The second feature of the present invention is more effective by performing the second step after forming the opening. Thus, the number of heat steps applied to the counter impurity profile formed in the second step can be reduced, and an impurity profile with a narrow distribution width can be realized.

The second feature of the present invention is effective when the second step is performed before the fifth step. Thus, for example, in the case of an nMISFET, (p
When a MISFET is manufactured by the "damascene gate method", counter doping is first performed among the channel impurities to smoothly distribute the n-type impurity region on the surface by a thermal process. In addition, the ion implantation of the channel is performed after the thermal process for activating the source / drain, thereby reducing the thermal process added to the p-type impurity and maintaining a steep p-type impurity distribution. can do.

The second feature of the present invention is more effective when the insulating film is formed by using a chemical vapor deposition method. As a result, the gate insulating film after the channel impurity is implanted can be formed at a low temperature without using thermal oxidation, and an impurity profile having a steep or narrow width of the channel can be realized.

The second feature of the present invention is effective when the duration of 850 degrees or more in the steps after the fourth step is 60 seconds or less. This can reduce the number of high-temperature heating steps, maintain an impurity profile having a steep or narrow channel width, and facilitate control of impurity concentration and impurity distribution profile.

As described above, according to the present invention, the process is not affected by the variation in the impurity profile due to the process variation.
A semiconductor device capable of miniaturizing a high-performance transistor and a method for manufacturing the same can be realized. Further, in the case of the medal gate, the present invention uses an impurity profile having a pn junction in the channel to make the M which is strong against the short channel effect.
After realizing ISFET and realizing low Vth,
A method of manufacturing an integrated circuit that suppresses Vth variation caused by variation in impurity distribution by the characteristics of the impurity distribution, realizes a transistor having performance superior to that of a polysilicon gate, and promotes miniaturization with high yield. provide.

[0052]

Referring to the drawings, a semiconductor device capable of reducing Vth variation and a method of manufacturing the same will be described as an embodiment of the present invention. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. In addition, it should be noted that the drawings are schematic, and the relationship between the thickness and the planar dimension, the ratio of the thickness of each layer, and the like are different from actual ones.

FIG. 6 is a sectional view of a MOSFET which is a semiconductor device. MOSFET: substrate 11, source region 1
2, a drain region 13, a gate insulating film 14, and a gate electrode 15. The coordinate axis 17 is set for the later description. The coordinate axis 17 has a zero point at the interface between the substrate 11 and the insulating film 14 and a positive value directly below. That is, this shaft 17
Represents the depth in the substrate 11. It should be noted that the zero point is not limited to the position in the figure, and if it is the above interface, the source region
2 may be anywhere as long as it does not overlap with the drain region 13.
The intersection of the axis 17 and the plane 16 extending to include the bottom surfaces of the source region 12 and the drain region 13 is referred to as depth A. Usually, the depth A is a depth of about 35 nm.

FIG. 7 shows a basic impurity profile of the semiconductor device according to the embodiment of the present invention. The horizontal axis is Fig. 6
Are coordinate axes 17. The vertical axis in FIG. 7A is a net impurity profile, and FIG. 7B is a channel impurity profile and a counter impurity profile. The relationship between (a) and (b) in FIG. 7 is that the absolute value of the difference between the channel impurity profile and the counter impurity profile at each depth in (b) is the net impurity profile in (a). .

In FIG. 7A, the net impurity profile 18 of the first conductivity type is located in a region deeper than the depth B. The density of the profile 18 may be a constant value, or there may be a small density area as indicated by a dotted line 21. A net impurity profile 19 of the second conductivity type is located in a region between the depth zero and the depth B. It is desirable that the density of the profile 19 be smaller than the highest density in the profile 18. It is desirable that the depth B is shallower than the depth A in FIG. Here, the “first conductivity type” and the “second conductivity type” are the opposite conductivity types. That is, the first
If the conductivity type is n-type, the second conductivity type is p-type and the first conductivity type is p-type.
If the conductivity type is p-type, the second conductivity type is n-type.

In FIG. 7B, the channel impurity profile 1 has a low concentration in a region shallower than the depth B and a high concentration in a deeper region. The low concentration may be zero. The counter impurity profile 2 is located in a region between zero depth and depth B. The density of profile 2 is greater than the density of the region of profile 1 between zero depth and depth B. That is, a high-concentration impurity region is provided near the junction depth of the source and drain electrodes, the impurity region is sharply reduced in concentration toward the surface, and an impurity region having an opposite polarity is provided in the low-concentration portion.

According to the study of the present inventors, in the case of the MOSFET channel profile in which the counter impurity is introduced, even if the impurity profile gives the same net impurity concentration, the high-concentration impurities of the opposite polarities cancel each other. In the case where there is no cancellation or the difference between the respective impurity concentrations and the net impurity concentration is smaller than in the case where Vth variation occurs due to the process variation, the Vth variation caused by the impurity variation is smaller. This is because a net profile generated by a plurality of profiles canceling each other is affected by both variations in the respective impurity distributions. Furthermore, by not using the cancellation, the concentration itself of the surface counter impurity can be reduced, and this fact can further suppress the Vth variation. This is because the absolute value of the density variation due to the process variation at a low density is generally smaller than that at a high density.

Further, with miniaturization, the number of impurity atoms contained in the channel depletion layer region decreases, and the statistical variation in the number or arrangement thereof causes variation in Vth. The effect of this statistical variation when a counter impurity layer is provided has not been reported and reported by academic societies and the like. According to the considerations of the present inventors, when comparing impurity distributions giving the same Vth, the higher the concentration of the counter impurity near the substrate surface, the greater the influence of variations in the number and arrangement on the Vth. Therefore, the surface portion of the high-concentration channel impurity region necessary for suppressing the short channel effect by the impurity profile of the present invention is made steeply low in concentration, and the counter impurity concentration near the substrate surface is lowered to realize the same Vth. By reducing the number of impurities, the variation in Vth caused by the statistical variation can be reduced.

Here, the impurity concentration or the number of the impurity atoms is the active impurity concentration or the number of the active impurity atoms as described above, and the electrically active portion of the silicon in the chemical concentration of the impurity contained in the silicon. Concentration, or number of atoms. Generally, the active impurity concentration is lower than the chemical concentration of the impurity, and the ratio is called an activation rate. Impurities introduced into silicon by ion implantation or the like are generally only partially active, and the remaining portions are activated by a thermal process. Generally, the higher the concentration, the lower the activation rate. In addition, the activation rate may be small especially near the substrate surface or at the interface between the substrate surface and the gate insulating film. If the concentration region is generally used for the channel profile, that is, about 5 × 10 ¹⁸ cm ⁻³ or less, the activation rate can be considered to be almost 100% for most of the impurity species through a normal activation annealing step. However, this activation rate may not be able to be secured near the substrate surface. The impurity profile of the conventional buried channel shown in FIG.
There is a possibility that the semiconductor device has a high-concentration impurity region near the substrate surface and the activation rate is reduced. In the case of the active impurity concentration distribution shown in FIG. 7B, the activation rate is generally sufficiently high in the high-concentration channel impurity region on the back side of the substrate, and the activation rate is not high on the substrate surface side. Is generally sufficiently high, so that the impurity distribution can be formed substantially the same as in FIG. 7B. The chemical impurity atom distribution of the impurity can be confirmed by using an impurity analysis technique such as SIMS analysis, and the profile of FIG. 7B takes into account the reduction in the activation rate near the substrate surface in the design stage. Channel profile design and process design such as ion implantation energy and dose can be performed without the need. Ensuring a sufficiently high concentration in the high concentration portion of the channel impurity profile 1 in FIG. 7B is important for suppressing the short channel effect. Therefore, 5
Using a high concentration of about × 10 ¹⁸ cm ⁻³ or more, it may be necessary to ensure a high active impurity concentration by introducing a high concentration until the activation rate of this portion decreases depending on the impurity species. In this case, the steepness of the chemical impurity distribution obtained by SIMS analysis and the like in the low concentration region toward the substrate surface and the steepness of the active impurity distribution are strictly different, and in a portion where the activation rate is reduced, The steepness of the active impurity distribution becomes gentler than that of the chemical impurity distribution. For this reason, in designing, it is necessary to take care that the active impurity distribution is formed sufficiently steeply in terms of the activation rate.
However, even in this case, the steepness is generally affected by the activation rate near the high concentration peak. On the other hand, in designing the profile, the low concentration portion of the channel impurity profile 1 on the substrate surface is sufficiently low. It is effective to maintain the concentration and to make the active impurity distribution of the channel impurity profile 1 at the portion toward the surface sufficiently low and steep enough. Usually, the activation rate of the channel impurity profile 1 at the concentration near this surface is effective. Is sufficiently large, and the steepness of the active impurity distribution can be confirmed by confirming the chemical impurity distribution by SIMS analysis or the like.

The details of the distribution of the counter impurity may be some cases depending on the situation. As an example, an nMOSFET in the case of using a metal (mid-gap gate electrode) whose Fermi level matches the energy level at the center of the silicon band gap for the gate electrode is mainly considered. In the case of this gate material, the band diagram of the gate electrode and the substrate becomes the same for the pMOSFET if the polarity is reversed. Therefore, the pMOSFET can be applied by using a profile in which the polarity of the impurity is reversed.

In the case of the metal gate nMOSFET, the work function difference between the substrate and the gate electrode is smaller than that in the case of the n + polysilicon gate, so that Vth is higher than that of the nMOSFET using the n + polysilicon gate. Low Vth
It is possible to obtain a low Vth by using a conventional buried channel by using a counter impurity in order to meet the demand of the semiconductor device. However, as a result of a study conducted by the present inventors using simulations, it was found that when a conventional buried channel structure was used, the variation in Vth caused by the profile variation became extremely large. .

The structures used by the present inventors are classified into two cases according to the Vth of the metal gate nMOSFET. When there is no counter impurity on the surface side of the channel p-type impurity, Vth is high, the channel is a surface channel, and as the counter impurity is added, Vth gradually decreases and the channel gradually becomes a buried channel.
In a range between the surface channel and the buried channel, in which the channel is formed on the substrate surface instead of the back side of the substrate at Vth, the effective increase of the gate insulating film thickness which has conventionally been a problem with the buried channel does not matter. . Therefore, according to the considerations of the present inventors, in this range, the introduction of the counter impurity shallowly as in the conventional buried channel pMOSFET does not improve the electrical characteristics, and it is necessary to introduce the counter impurity shallowly. Absent.

The channel structure just before the buried channel is provided is about 0.4 V in the case of a mid-gap metal gate. Vth is 0.4V
When the thickness is set to be less than about, the channel is formed deeper than the substrate surface, and the thickness of the gate insulating film is effectively increased.

First, when a mid-gap metal gate is used, Vth is 0.4 V or less.
Vth whose absolute value is smaller than 0.4 V), and when the channel is a buried channel, or when the n + polysilicon gate is used, the buried channel pMO
In the case of an SFET, a counter impurity profile 2 as shown in FIG. 8B can be used. In FIG. 8B, as in the case of the profile 1 in FIG. 7B, the channel impurity concentration near the surface is sharply lowered to obtain a desired Vth with a low-concentration counter impurity. It is formed shallow on the substrate surface to suppress an increase in the effective gate insulating film thickness. When the Fermi level of the gate electrode of the metal gate deviates from the mid gap, the value of Vth also deviates accordingly. That is, when the Fermi level of the gate electrode is shifted by xV to the conduction band side from the midgap, the Vth of the boundary between the surface channel and the buried channel with respect to the nMOSFET is about (0.4-x) V, and the pMOSFET Is about-(0.4 + x) V. FIG. 8A shows a net impurity concentration obtained from the absolute value of the difference between the channel impurity concentration and the counter impurity concentration at each depth in FIG.

Next, Vth (pMOSFE) above the boundary between the surface channel of the metal gate and the buried channel.
In the case of T), Vt whose absolute value is larger than the value at this boundary
In the case of h), if necessary, FIG.
The counter impurity profile 2 shown in FIG. As described above, in this case, it is not necessary to form the counter profile shallow. FIG. 9 (b) or FIG.
In the profile (b), the impurity concentration at the pn junction between the channel p-type impurity and the counter n-type impurity is low,
There is no cancellation of the concentration at the n-junction. In the case where a sufficient impurity concentration for suppressing the short channel effect cannot be obtained, for example, when the activation concentration of the channel p-type impurity is not sufficiently increased, the counter n-type impurity concentration does not cancel the channel p-type impurity concentration. (B) or FIG.
It is necessary to use the counter impurity profile of (b). In FIG. 10B, the counter impurity concentration on the surface of the substrate is reduced, so that a decrease in mobility due to scattering of channel carriers (electrons or holes) with the impurity can be prevented, and the current value can be increased. However, it is difficult to form the counter impurity profile 2 having a narrow distribution within the width of the shallow surface low concentration layer without variation.
It is good to use when precise process control is possible.

As shown in the simulations of the present inventors, the larger the width of the distribution of the counter layer in FIG. 9B or FIG. 10B, the smaller the effect of the process variation on the Vth variation. Therefore, the counter n having a width large enough not to cancel the active concentration of the p-type impurity
It is preferable to use a type impurity concentration. The channel impurity profile 1 shown in FIGS. 9B and 10B corresponds to FIG.
This is the same as channel impurity profile 1 in (b).
FIG. 9A shows a net impurity concentration obtained from the absolute value of the difference between the channel impurity concentration and the counter impurity concentration at each depth in FIG. FIG. 10A shows the net impurity concentration obtained from the absolute value of the difference between the channel impurity concentration and the counter impurity concentration at each depth in FIG.

If the activation concentration of the channel p-type impurity can be made high enough to suppress the short channel effect, the profiles shown in FIGS. 11 and 12 can be used.

In FIG. 11A, the channel p on the substrate surface is
The counter impurity concentration is reduced by sharply lowering the impurity concentration at the surface of the channel, and this counter n-type impurity profile 2
And overlap. By using the channel p-type impurity profile 1 having a steeply low concentration, a desired low Vth can be realized by a low-concentration counter n-type impurity. By using a low-concentration counter n-type impurity, cancellation of the channel p-type impurity concentration by the n-type impurity can be reduced, and a net p-type impurity concentration required for suppressing the short channel effect can be secured. When a sufficient active p-type impurity concentration can be ensured, FIG.
The n-type impurity may have a distribution extending to the back of the substrate as shown in FIG.

FIG. 12A shows that the counter n-type impurity profile 2 has a low concentration portion on the substrate surface. According to the considerations of the present inventors, the variation in Vth caused by the statistical variation in the number and arrangement of impurity atoms, which becomes important in a very fine MOSFET, is reduced by removing atoms on the substrate surface. The Vth variation includes a portion caused by the variation of the first conductivity type impurity and a portion caused by the variation of the second conductivity type impurity. As the concentration of the second conductivity type impurity is increased, the first conductivity type is increased. The variation caused by the impurity of the type is canceled out, and the variation of the entire Vth is reduced, has a minimum value near the boundary between the surface channel and the buried channel, and further increases as the impurity concentration of the second conductivity type is increased. growing. According to the impurity profile of FIG. 12A, the p-type impurity concentration near the substrate surface is sharply reduced to reduce the statistical variation except for the p-type impurity atom concentration near the substrate surface. By lowering the counter n-type impurity concentration in the region and further lowering the outermost surface of the n-type impurity profile 2, Vth variations due to statistical variations in atom arrangement and number of atoms are further reduced. The effect of reducing the variation in Vth due to the variation in the number of impurity atoms and the arrangement of the atoms due to the impurity distribution in FIG. 12A is particularly effective when the channel is sufficiently buried at Vth. In a structure in which the surface of the counter n-type impurity has a low concentration, the low-concentration counter n-type impurity may be distributed deep into the substrate as shown in FIG.

The variation in Vth due to the statistical variation in the number of atoms and the arrangement thereof caused by the decrease in the number of impurity atoms in the channel region of a very fine transistor has been discussed for the surface channel. In the case of a surface channel, channel impurities at the position of the substrate surface where a channel carrier distribution occurs most strongly contribute to the Vth variation, and impurities on the substrate surface side in the channel depletion layer more strongly contribute to the Vth variation. It has been made clear by the inventors.

On the other hand, in the case of a buried channel, Vth variation caused by process variations such as when a shallow counter impurity distribution is formed is large, and the above-mentioned statistical variation is not discussed, and measures are not sufficient.

For example, by increasing the concentration of the counter impurity on the substrate surface and sharply lowering the impurity concentration at the position where the channel carrier is generated deeper than the substrate surface, the number of impurity atoms in the channel carrier and the statistical information on the arrangement thereof are obtained. Even if an effort is made to suppress the variation in the characteristics, the improvement in the characteristics due to the suppression of the effective increase in the thickness of the gate insulating film at this time can be expected, but the suppression of the variation in the Vth caused by the statistical variation of the impurity atoms is considered. Does not give good results.

In the case of the buried channel, it is necessary to analyze in detail the influence of the statistical variation in the number of atoms and the arrangement on Vth in comparison with the case of the surface channel.

As shown in FIG. 13, the gate bias (V
_G ) is lower than the electric potential value (Φs) on the substrate surface by an amount determined by the electric field (Eox) on the silicon substrate surface by the thickness (tox) of the gate insulating film. Value.

As shown in FIG. 14, in the case of the surface channel, the channel carrier position is on the substrate surface, and the electric potential (Φch) at the channel carrier position matches Φs. Note that the carrier distribution in the surface channel has a spread of the electron wave function. qΦch should be the potential at the position of the center of gravity of this spread, and is shifted by several nm from the outermost surface of the substrate. The statistical variation of the impurity atoms in the depletion layer causes variation in Φch, variation in the slope Eox, and variation in Vth. Eox is an electric field reaching the gate electrode. The influence of the variation on Φs is greater on the side closer to the gate electrode, that is, on the impurity atoms closer to the substrate surface.

In the case of the surface channel, the position of the substrate surface that has the largest influence on Φs is the position where the channel is generated, and the influence of the impurity atom variation on the electric potential at the channel position is smaller on the substrate surface side. The greater the variation of the impurities, the greater the two.

However, in the case of a buried channel as shown in FIG. 15, variation in Φs causes variation in the potential corresponding to Vth. Φs is greatly affected by the variation of the impurity profile on the substrate surface side. For example, the counter impurity concentration at the position where the channel carrier occurs on the back side of the substrate is lowered, the profile of the counter impurity concentration on the substrate surface is sharply increased, and the influence of the dispersion of the impurity atoms on the electric potential at the channel position is reduced. However, since the counter impurity concentration on the substrate surface is high, the impurity charge on the substrate surface near the gate electrode varies, so that the variation of Φs is rather large. Therefore, the variation in the buried channel Vth in this case is rather large. From this,
In order to suppress the Vth variation due to the statistical variation of the impurity atoms, it is necessary to suppress the variation of the net impurity profiles 18 and 19 on the substrate surface and the variation of Φs and Eox as shown in FIG. 16 instead of the channel position. is there. In particular, as shown in FIGS. 12A and 12B, it is effective to reduce the counter impurity concentration on the substrate surface, preferably to make the concentration zero, in order to suppress the variation in Vth. Similarly, lowering the surface concentration of the channel impurity on the substrate surface within a range that does not deteriorate the short channel effect, and ideally setting the concentration to zero can also be achieved by reducing the Vth due to the statistical variation in the distribution of impurity atoms. This is effective in reducing variations. FIG. 16 is a graph showing a net impurity concentration obtained from the absolute value of the difference between the channel impurity concentration and the counter impurity concentration for each depth in FIGS. 12 (a) and 12 (b). Even when the counter impurity profile has a shape with a high surface concentration, the surface of the channel impurity having the opposite polarity is low, so that the concentration of the counter impurity is reduced and a desired Vth is obtained.
Can be obtained, and Vth variation due to statistical variation can be suppressed.

In the buried channel, forming a distribution in which the concentration of the counter impurity is low on the surface side and high on the back side of the buried channel effectively increases the thickness of the gate insulating film, deteriorating the S factor and reducing the short channel. The effect is increased.
In order to avoid these, the necessity of forming a shallow counter layer cannot be satisfied.

When a counter impurity is introduced into a low concentration or a narrow range to form a channel on the substrate surface at Vth, that is, when a transistor having a counter impurity profile is operated in the range of the surface channel, the surface concentration of the channel impurity is reduced. Suddenly has a low concentration,
An impurity profile in which the surface concentration of the counter impurity is low is effective. Since the channel is formed on the substrate surface, there is no effective increase in the thickness of the gate insulating film, and thus the necessity of forming a shallow counter impurity layer is small.
If the gate bias is lower than Vth, the carriers gradually become deeper in the substrate according to the distribution of the counter impurity layer. Therefore, if the counter layer is shallow enough to keep the current value sufficiently small when the gate bias is zero, Good. In particular, in the case of a metal gate, Vth of about 0.4 V can be realized in the range of the surface channel by using a channel impurity distribution having a counter impurity layer.

FIG. 17 shows the result of simulating the Vth and the SCE range with respect to the concentration of the counter impurity when the stepped profile shown in FIG. 7 is used in the case of the metal gate. Here, the upper concentration of the step of the p-type impurity concentration profile in FIG. 7 is 5 × 10 ¹⁸ cm.
⁻³ , and the density near the surface at the lower stage of the step is zero. The distance from the semiconductor surface to the step was 25 nm. The gate length is 95 nm. The horizontal axis represents the concentration of the counter impurity, and the vertical axis represents Vth and the SCE range. □ represents Vth. A mark represents the SCE range. From this, it can be seen that Vth decreases and the SCE range increases as the concentration of the counter impurity increases. In addition, a low Vth of, for example, 0.4 V
In order to achieve the above, the concentration of the counter impurity is 9
× 10 ¹⁷ cm ⁻³ , and at this concentration,
The SCE range was found to be about 50 mV. The concentration of the counter impurity Vth is in 0.4V in FIG. 2 is 5.3 × ¹⁰ 18 cm ^- since it is ^3, in order to obtain the Vth of the same size it can be seen that achieved in less than one concentration of 5 minutes. SC at Vth of 0.4 V in FIG.
Since the E range was 70 mV, Vth of the same size
It can be seen that the SCE range was able to be reduced by 20 mV. As described above, the step-like profile in FIG. 7 can reduce the concentration of the counter impurity more than the profile in FIG. 1, and the SC-profile from the step-like profile in FIG.
It has been found that the E range can be reduced and Vth does not easily fluctuate.

FIG. 18 also shows a simulation result of Vth variation due to the variation of Vth with respect to the counter dopant concentration and the variation of the profile of the impurity layer of the opposite conductivity type when the stepped profile shown in FIG. 7 is used in the case of the metal gate. is there. Here, the shape of the p-type impurity concentration profile 1 in FIG. 7 is the same as that in FIG. The horizontal axis represents the n-type impurity concentration of the counter-doped n + impurity layer, and the vertical axis represents Vth and the profile 2 in FIG.
Is the variation of Vth due to the change of the shape. X mark is Vt
h. The □ marks indicate the variation in Vth when the pn junction existing at the position of 25 nm depth becomes 1 nm shallower and the depth becomes 24 nm. △ mark is profile 2
Represents the variation of Vth when the concentration of the Vth decreases by 2%. Therefore, Vth indicated by the crosses in FIG. 18 and Vth indicated by the squares in FIG.
th indicates the same relationship. The reason why the width of the change is set in this manner is that manufacturing variations due to semiconductor manufacturing equipment and the like are assumed. This indicates that the n-type impurity concentration needs to be as high as 9.3 × 10 ¹⁷ cm ⁻³ in order to achieve a low Vth, for example, 0.4 V. At this concentration, the variation of Vth due to the variation of the depth of the mark was about 20 mV.
The amount of change in Vth due to the change in the density of the mark was 5 mV. The change amount of Vth with respect to the change of the depth in FIG.
V, it can be seen that it was reduced to 40%. In addition, since the amount of change in Vth with respect to the change in density in FIG. 2 was 10 mV, it can be seen that it was reduced to half. As described above, the step-like profile of FIG.
From the profile, it was found that the concentration of the counter impurity in which Vth hardly fluctuated with the change in the profile shape.

Example 1 FIG. 19 shows a model obtained by obtaining a profile that can be realized by ion implantation, thermal diffusion, or the like based on the profile of the step-like deformation shown in FIG. 9, and furthermore, the gate voltage is the threshold voltage Vth. 4 is an impurity concentration profile in the depth direction of the MIS transistor according to the first embodiment of the present invention obtained by using a device simulation to determine a hole concentration distribution at the time. The horizontal axis represents the depth from the interface 23 between the gate insulating film and the semiconductor substrate to the inside of the semiconductor.
The vertical axis is the impurity concentration. The solid line is the net impurity concentration profile, and the solid line with a black square is the counter (n
Type) impurity concentration profile, and a solid line with a white square is a channel (p-type) impurity concentration profile,
The dotted line shows the carrier (hole) concentration distribution when the gate voltage is Vth when 1 V is applied to the drain electrode. Here, the impurity concentration profile is the distribution in the substrate depth direction of the average of the impurity concentration at a specific distance from the gate end in the channel region of a transistor created to perform the same operation in the integrated circuit chip. And In the following embodiments, an n-channel MIS transistor will be described unless otherwise specified. In the case of a p-channel MIS transistor, the conductivity types may be reversed.

In the first embodiment, the channel (p-type) impurity concentration at a depth deeper than around 35 nm is set to 5 × 10 ¹⁸ cm ^−3.
And higher. Then, the concentration is sharply reduced at a depth of about 30 nm, and the concentration toward the substrate surface 23 is reduced.
The channel impurity profile is required to have a high concentration in order to suppress the short channel effect, while it is desirable that the channel impurity profile has a low concentration near the substrate surface 23 in order to obtain a low Vth. From these facts, the channel impurity profile was approximated by a Fermi distribution function.

In the first embodiment, the channel impurity concentration is reduced by at most 20% per 1 nm, and the channel impurity concentration near the substrate surface 1 is suppressed to 1 × 10 ¹⁷ cm ⁻³ . Therefore, a low Vth could be obtained even if the concentration of the counter impurity (n-type impurity) was kept low.

That is, the counter impurity concentration is about 1.
It is 4 × 10 ¹⁸ cm ⁻³ , the net n-type impurity concentration is about 1.3 × 10 ¹⁸ cm ⁻³ , and the contribution of the channel impurity profile to the net n-type impurity concentration is small. For this reason, the influence of the channel impurity distribution on the net n-type impurity concentration variation is small, and only the counter impurity concentration variation determines the net n-type impurity concentration variation. As a result, the variation in p-type impurity concentration given to Vth can be reduced. In addition, since the counter impurity concentration for obtaining the same Vth can be kept low, the absolute value of the net n-type impurity concentration variation can be reduced, and the variation given by the counter impurity concentration variation to Vth can be reduced. .

FIG. 20 shows three types of channel impurity profiles examined to show the effectiveness of the first embodiment.
Generally, in a transistor having a pn junction in a channel, high-energy ion implantation and a heat process are used.
The channel (p-type) impurity profile has a gentle gradient. These channel impurity profiles were generated by changing the shape factor t of the Fermi distribution function to 2, 4, and 6. The profile whose shape factor t is 2 is the same as the channel impurity profile shown in FIG. 19 of the first embodiment, and the peak concentration of the counter impurity is adjusted so that Vth becomes 0.4 V in each p-type impurity profile. did. However, the peak position of the counter doping was at a depth of 15 nm from the semiconductor interface. On the other hand, t is 6
Profile 1 × 10 ¹⁷ cm similarly to the profile t is 2 in the semiconductor surface ^- but with ³ degree of surface impurity concentration, a decrease in the concentration of towards the surface is smooth. The profile with t = 4 is located between the profiles with t = 2 and t = 6. When the profile of t is 6, the peak concentration of the counter impurity required to obtain the same Vth: 0.4 V as the profile of t is 2 is 2 × 1.
0 ¹⁸ cm ⁻³ . When t is 4, 1.
It was 7 × 10 ¹⁸ cm ⁻³ . When t is smaller than this, the required counter impurity concentration is lower, and thus the absolute value of the net n-type impurity concentration variation is smaller. Further, since the channel impurity concentration is low in the entire channel impurity profile and the net n-type impurity concentration is determined by the counter impurity concentration, the Vth variation is small.

FIG. 21 is a graph showing Vt with respect to profile variation when the corresponding counter impurity profile is added to each of the three types of profiles shown in FIG.
6 is a graph showing h variation. Numerical values were obtained using device simulation. The axis labeled nsc-5% is the Vth when the counter impurity concentration varies by 5%.
Represents the value of variation. The axis labeled nwell-5% represents the value of the variation of Vth when the channel impurity concentration varies by 5%. The axis marked rgwx-1 nm is
This represents the value of the variation in Vth when the position where the channel impurity concentration rapidly decreases (depth indicated by the line segment 25 in FIG. 20: 30 nm) varies by 1 nm. The axis of Scp-1 nm represents the value of variation of Vth when the peak position of the counter impurity concentration (depth indicated by the line segment 26 in FIG. 20: 15 nm) varies by 1 nm. The axis of scj-1 nm represents the value of the variation of Vth when the distance (set at 20 nm) from the peak position of the counter impurity concentration to the position at which the concentration at the peak position becomes 1/10 of the concentration is 1 nm. Represents The mark Δ indicates a case where t is 6, the mark □ indicates a case where t is 4, and the mark ○ indicates a case where t is 2. From this, t
The smaller the value, the smaller the Vth variation in the channel impurity concentration variation, the counter impurity concentration variation, and the variation in the depth of the step-shaped step in the channel impurity profile. Further, it was found that a smaller t gives a smaller Vth variation not only in the variation in the concentration but also in the variation in the peak position of the counter impurity concentration and the variation in the shape of the counter impurity profile. These things, Vt
In order to reduce the variation in h, it is considered that the slope of the step portion of the channel impurity profile should be as steep as possible.

Further, a comparison will be made with FIG. First, as for the impurity concentration, in FIG.
Although the voltage fluctuated, in FIG. 21, it fluctuated only by about 10 mV despite the fluctuation of 5%. The variation in the depth direction of the profile is also 0.5 nm in FIG.
Although Vth fluctuated by 50 mV when it varied, in FIG. 21, even if the position of the step of the channel impurity of the profile with the t of 6 being the most fluctuating varied by 1 nm, it fluctuated only by 24 mV. As described above, when t is 6 or less, variation in Vth can be significantly reduced as compared with FIG. Note that t
The maximum concentration gradient of the profile of 6 is that the ratio of concentration per 1 nm is about 0.9, and if it is smaller than 0.9,
This corresponds to the case where t is smaller than 6.

In the first embodiment, the counter impurity profile is formed so as to be included in the surface low concentration region of the channel impurity profile. That is, the concentration of the counter impurity profile at the end of the depletion layer is formed to be smaller than 1/4 of the maximum value of the concentration of the channel impurity profile in the depletion layer. Is achieved by a low counter impurity concentration in the p-type impurity profile of FIG. In order to suppress the short channel effect, a high concentration p-type impurity distribution is used on the back side of the channel impurity profile. The depletion layer extends to the high concentration region of the channel impurity profile, and the transistor characteristics are such that the high concentration channel (p
(Type) It depends strongly on the high concentration of charges in the impurity region. Since the counter impurity profile is not included in the high concentration region of the channel impurity profile, the net channel (p-type) impurity profile in the depletion layer is determined only by the channel impurity profile. Even if the counter impurity profile varies, the V of the net p-type impurity profile
The important part that determines th is not affected, and Vth variation is reduced. In order to reduce the width of the counter impurity profile, a low-concentration pn junction may be formed on the substrate surface side of the counter impurity profile as shown in FIG.

In the first embodiment, these modulations affect the transistor operation by making the p-type and n-type impurity concentrations at the position of the pn junction at least one digit lower than the maximum channel impurity concentration in the depletion layer. The effect is reduced.
Here, the depletion layer is defined as a region where the carrier concentration is lower than the impurity concentration by 10% or more. In Example 1 in FIG. 19, the end of the depletion layer is around 38 nm in depth, and the channel impurity in the depletion layer is The maximum value of the concentration is located near the end of the depletion layer, and the concentration is 5 × 10 ¹⁸ cm ⁻³ . Note that the maximum value of the channel impurity concentration may exist at a position shallower than the end of the depletion layer.

Further, in the first embodiment, at the semiconductor interface, the channel impurity concentration is smaller than ４ of the counter impurity concentration. Regarding the influence on the electric characteristics per unit charge in the depletion layer, the influence of the charge distribution on the semiconductor interface side on the electric characteristics per unit charge is larger than that by the charge distribution on the back side of the semiconductor. By reducing the influence of the channel impurity profile on the net n-type impurity concentration at the semiconductor interface, it is possible to reduce the variation of the channel impurity concentration on the electrical characteristics. On the other hand, in the net n-type impurity concentration profile in the depletion layer, the influence of the maximum concentration on the electrical characteristics is generally large. In the first embodiment, the channel impurity concentration at the position where the maximum net n-type impurity concentration is provided is smaller than １ ／ of the counter impurity concentration, and the influence of the variation in the channel impurity concentration on the electrical characteristics is reduced. be able to.

In the first embodiment, the peak position of the counter impurity profile is located shallower than the position of the pn junction. Thus, the main profile of the counter impurity is located away from the channel impurity profile, the net n-type impurity profile is determined exclusively by the counter impurity profile, and the net p-type impurity profile is determined exclusively by the channel impurity profile. The variation in the net p-type and n-type impurity profiles due to the variation in the counter impurity profile and the channel impurity profile is reduced, and Vt
The variation of h is reduced.

In the first embodiment, by increasing the counter impurity concentration, the MISFE having a lower Vth
At T, Vth variation can be kept small. At this time, it is desirable to suppress the counter impurity profile to the depth of the surface low-concentration portion of the channel impurity profile. Even in the case of overlapping, the Vth variation can be reduced by using the channel impurity profile in which the concentration becomes sharply low toward the surface described in the first embodiment.

In the first embodiment, as shown in FIG. 19, the place where the channel impurity profile sharply decreases toward the surface is set to around 30 nm. However, by using a profile in which this place is further moved to the surface side, The short channel effect can be further suppressed. In this case, to obtain the same Vth as in the case of FIG. 19, a counter impurity profile having a higher concentration or a wider distribution than that shown in FIG. 19 may be used. Conversely, if the location where the temperature suddenly lowers is moved to the back side and an n-type impurity profile having a lower concentration or a narrower distribution than that in FIG. 19 is used to obtain the same Vth, it is shorter than in FIG. The channel effect increases. However, generally, the more the location where the temperature suddenly lowers is moved toward the surface side, the greater the variation in the impurity variation given to Vth. Thus, there is a so-called trade-off relationship between the suppression of the short channel effect and the suppression of Vth variation due to the impurity distribution variation. In consideration of the accuracy of gate processing such as lithography and etching used in the manufacture of transistors and the accuracy of channel impurity profile control such as ion implantation and thermal processes, an optimum channel impurity distribution in the above trade-off is used to obtain a desired Vth. Just fine. By using the channel impurity distribution of the present invention,
Vth variation caused by short channel effect and impurity profile variation can be suppressed. Then, a transistor with low Vth can be realized, and an integrated circuit with high speed and low power consumption can be realized with high yield.

Embodiment 2 FIG. 22 shows a model obtained by modeling a profile that can be realized by ion implantation, thermal diffusion or the like in the same manner as in FIG. 19, based on the step-like profile of FIG. 9 is a channel profile in the depth direction of the MIS transistor according to the second embodiment of the present invention obtained by determining a carrier (hole) concentration distribution at a certain time using device simulation. The meanings of the horizontal axis, the vertical axis, the solid line, the solid line with a black square, the solid line with a white square, and the dotted line are the same as those in FIG. As in the first embodiment, the short channel effect is suppressed by using a channel impurity profile whose concentration rapidly decreases toward the substrate surface 23 and a low impurity counter impurity profile at the pn junction position. In the second embodiment, unlike the first embodiment, at the position where the counter impurity profile intersects the channel impurity profile, the concentration gradient of the counter impurity is gentler than that of the channel impurity. Then, the counter impurity profile extends to the high concentration portion of the channel impurity profile.

In the second embodiment, the channel impurity profile and the counter impurity profile have the same concentration at a depth of 26 nm from the semiconductor interface (position of the line segment 24 in FIG. 22), and a pn junction is formed. A step-like channel impurity profile in which the concentration is rapidly reduced toward the interface 23 is used, whereby the concentration of the channel impurity and the counter impurity at the pn junction is reduced to 12 which is the maximum channel impurity concentration in the depletion layer. %. p
The concentration of the channel impurity and the counter impurity at the n-junction is about 6 × 10 ¹⁷ cm ⁻³ , and by reducing the channel impurity concentration at the pn-junction, the variation in the channel impurity concentration near the junction is a net n-type impurity. The variation in the concentration is reduced, and the influence of the variation on the transistor operation is reduced.

The channel impurity profile is gently distributed with a peak near a depth of 15 nm. pn
The concentration gradient of the counter impurity at the junction is smaller than the concentration gradient of the channel impurity. For this reason, the depth position dependence of the channel impurity profile is small, and even if the depth and the width of the distribution vary, the net n-type impurity profile does not vary and does not affect the electrical characteristics.

FIG. 23 is a graph showing Vth variation with respect to profile variation in each case where the shape of the counter impurity profile in FIG. 22 is changed in three ways. Numerical values were obtained using device simulation. At this time, t of the channel impurity profile was kept constant at 2, and the depth at which the channel impurity concentration rapidly decreased was also kept constant at 30 nm. Further, the peak position of the counter impurity concentration was made constant at a position at a depth of 15 nm. Then, the distance (scj) from the peak position of the counter impurity concentration to a position at which the concentration was 1/10 of the concentration at the peak position was changed to change the concentration gradient of the profile. Axis marked nsc-5%, nwell-
Axis marked 5%, axis marked rgwx-1 nm, scp
The meaning of the axis of -1 nm and the axis of scj-1 nm are the same as in FIG. The squares indicate the case where scj is 40 nm, which corresponds to the counter impurity profile in FIG. ○ indicates a case where scj is 20 nm, and △ indicates a case where scj is 10 nm.
nm. From this, nsc-5%, nwel
It has been found that 1-5% and rgwx-1 nm take constant values even when scj is changed. In addition, it was found that scp-1 nm and scj-1 nm decreased as scj increased. In order to reduce the variation in Vth, it is only necessary to increase scj. In other words, it is considered that the gentler the gradient of the concentration of the counter impurity, the better.

Further, a comparison will be made with FIG. First, impurities
As for the concentration, in FIG.
V fluctuated, but in Fig. 23
Nevertheless, it fluctuates only by about 10 mV. Profile
In FIG. 2, the variation in the depth direction of the
Vth fluctuated by 50 mV when it varied, but in FIG.
The scj which is easy to vary is s with a profile of 10 nm.
Even if cj is reduced to 9 nm, it changes only by 17 mV. This
If scj is 10 nm or more, as shown in FIG.
Thus, variation in Vth can be significantly reduced. And Vt
To set h to 0.4 V, scj is 40 nm
7.5 × the peak concentration of the counter impurity profile
10¹⁷cm^-3And scj is 20 nm
Is 9.4 × 10¹⁷cm^-3And scj is 10n
1.6 × 10 for m¹⁸cm ^-3Should be set to
I understand. This means that Vth in FIG.
Set the counter impurity profile to
Peak concentration of 5 × 10 ¹⁸cm^-3High concentration
Lower than one-third compared to what must be specified
is made of.

The concentration gradient of the channel impurity at the pn junction position is larger than that of the counter impurity, and the channel impurity profile rapidly increases toward the back of the substrate. As a result, the counter impurity profile overlapping with the net p-type impurity profile is eliminated, and a net p-type impurity profile with a high concentration can be formed. If the counter impurity profile is flat, the concentration does not depend on the position, so even if the counter impurity profile overlapping the net p-type impurity profile near the pn junction varies, the net p-type impurity profile does not vary, and the electrical characteristics Does not affect

Further, although the net p-type impurity profile near the pn junction is mainly determined by the channel impurity profile, it is subtracted from the counter impurity profile. Since the concentration gradient of the counter impurity is smaller than that of the channel impurity and the dependence of the channel impurity concentration on the position is small,
Even if the channel impurity concentration varies, the variation in the subtraction of the counter impurity concentration is small, the variation in the net p-type impurity concentration is suppressed, and the influence on the electrical characteristics is suppressed.

At the location where the maximum value of the counter impurity concentration is given, the channel impurity concentration is as small as 1/4 or less of the counter impurity concentration. Net n in the depletion layer
The influence of the maximum value of the type impurity concentration on the electrical characteristics is generally large. The influence of the variation in the channel impurity concentration on the electrical characteristics can be reduced.

On the surface of the substrate, the channel impurity concentration is smaller than the counter impurity concentration by 1/4 or less. The effect on the electrical characteristics per unit charge in the depletion layer is as follows:
The influence of the charge distribution on the substrate surface side per unit charge on the electrical characteristics is greater than that of the charge distribution on the substrate back side. The effect of the channel impurity profile on the net n-type impurity concentration is reduced by reducing the channel impurity concentration to 1/4 or less of the counter impurity concentration on the substrate surface, and the variation of the channel impurity concentration on the electrical characteristics is reduced. Can be smaller.

Further, from FIG. 20, the end of the depletion layer has a depth of 38 nm.
The maximum value of the channel impurity concentration in the vicinity and in the depletion layer is 5 × 10 ¹⁸ cm ⁻³ near the end of the depletion layer. The maximum value of the channel impurity concentration may be located shallower than the end of the depletion layer.

The counter impurity concentration on the substrate surface is は of the maximum value of the counter impurity concentration.
Greater than 、 and less than twice the concentration at the pn junction. Due to this feature, the location dependency of the counter impurity concentration is small, and the net n-type and p-type impurity concentration profiles are hardly influenced by the variation of the counter impurity profile.

Although the peak of the counter impurity profile is located near the center of the low-concentration region of the surface of the channel impurity profile, the peak may be located further on the front side or the back side. It may be located in the profile or further inside. FIG.
It may be a uniform distribution having no peak like the profile 2 of 1 (a) and (b).

By increasing the counter impurity concentration, a lower Vth can be obtained. At the same Vth, the counter impurity concentration is desirably low. When a desired low Vth is obtained by using a low-concentration n-type impurity layer, it is effective to flatten the counter impurity profile. Even when the counter impurity concentration increases as much as the channel impurity concentration and the counter impurity concentration greatly contributes to the net p-type impurity concentration, the concentration gradient of the channel impurity that decreases toward the substrate surface is smaller than that of the counter impurity. Due to the large feature, Vth variation generally smaller than that of the conventional example can be obtained. This is because, when the counter impurity concentration is increased, the net p-type impurity profile affected by the counter impurity distribution is far from the substrate surface, and the influence of the variation on Vth is generally smaller than when the counter impurity is closer to the substrate surface. Not only that, the counter impurity distribution has a gentle shape, so that the variation is small.

The advantage of the second embodiment over the first embodiment is that the formation and control of this profile are easier because the counter impurity profile is gentle and has little dependence on position or shape. In the first embodiment, since the width of the counter impurity profile needs to be suppressed to about the width of the surface low-concentration layer of the channel impurity profile, it is necessary to limit the heating process, and control the counter impurity concentration, peak position, distribution shape, and the like. There is a need to. In the second embodiment, it is not necessary to limit the heating process for forming the counter impurity profile because of the gentle distribution, and only the concentration needs to be controlled basically. However, the higher the concentration, the lower the Vth becomes, and it is necessary to precisely control the concentration in accordance with the channel impurity profile in the depletion layer and the desired Vth value. In the second embodiment, in order to obtain a desired Vth, a channel impurity profile counter impurity is formed to have a steep low concentration on the surface, and then only the counter impurity concentration is used as a parameter.

(Embodiment 3) FIG. 24 shows, based on the profile of the step-like deformation shown in FIG. 9, a model that can be realized by ion implantation or thermal diffusion as in FIG. 10 is a channel profile in the depth direction of the MIS transistor of Example 3 of the present invention obtained by using a device simulation to determine a carrier (hole) concentration distribution when 1 V is applied and the gate voltage is Vth. The meanings of the horizontal axis, the vertical axis, the solid line, the solid line with a black square, the solid line with a white square, and the dotted line are the same as those in FIG. A channel impurity profile whose concentration rapidly decreases toward the substrate surface as in the first embodiment,
The short channel effect is suppressed by using a low-concentration counter impurity profile at the n-junction position. In the third embodiment, unlike the first and second embodiments, the peak position of the counter impurity profile is on the substrate surface 23.
The concentration of the channel impurity profile overlapping the pn junction and the net n-type impurity profile is reduced, and the counter impurity concentration is increased. This results in a low V
th can be obtained. Further, the counter impurity concentration for obtaining a high net n-type impurity concentration can be suppressed low, and the absolute value of the variation in the counter impurity profile can be reduced. Thus, the variation in the channel or counter impurity concentration is n
The influence on the variation in the type or p-type impurity concentration can be reduced, and the variation in the electrical characteristics can be reduced.

The point that the profile of the third embodiment is superior to the profile of the first embodiment is that the pnp
It is easy to introduce more counter impurities into the substrate while keeping the impurity concentration at the junction 2 low. As a result, the restriction on the heating step can be relaxed more than in the case of the first embodiment. In the case where a shallow counter impurity profile is formed by minimizing the thermal process, a place where the channel impurity profile sharply decreases may be moved to the surface side while keeping the impurity concentration at the pn junction 2 low. It is possible to further suppress the short channel effect.

The first to third embodiments can be applied to a case where the gate electrode is a poly gate and a case where the gate electrode is a metal gate. As the metal gate electrode, a portion in contact with the gate insulating film is formed of at least one of a nitride, a carbon nitride, and a silicon nitride of at least one transition metal element belonging to Group IV, V, or VI. Is used. Specifically, the portion in contact with the gate insulating film is tungsten (W) nitride, molybdenum (Mo) nitride, tantalum (Ta) nitride, titanium (Ti) nitride, W silicon nitride, Mo silicon nitride. , Ta silicon nitride, Ti silicon nitride, Ti carbon nitride, W carbon nitride, Mo carbon nitride, and Ta carbon nitride. Alternatively, portions of the metal gate electrode that are in contact with the gate insulating film are formed of ruthenium (Ru) containing oxygen, Ru containing nitrogen, and Ru oxide containing Ru (RuO ₂ ).
.

Since the magnitude of the work function of the part of the gate electrode in contact with the gate insulating film changes the value of Vth, if the crystal grain size of this part is large, the work function differs depending on the plane orientation. Variations occur. For this reason, the crystal grain size of this portion is set to 10 nm or less, preferably 30 nm or less.

In the first to third embodiments, the MIS of the metal gate is used.
When applied to an FET, particularly, a metal material whose work function is located near the center of the band gap of silicon, for example,
When applied to a MISFET using titanium nitride (TiN), an important effect is exhibited. At this time, pMISFE
Vth in any case of T and nMISFET becomes large. In order to obtain a low Vth, by applying the first to third embodiments, the variation of Vth can be reduced by using the same metal or metal compound material having a work function near the center of the silicon band gap without using the dual gate. A suppressed high-performance MISFET for CMOS can be realized.

Fourth Embodiment A fourth embodiment relates to a MISFET having an impurity profile according to the second embodiment and a method of manufacturing the same. FIG. 25 is a cross-sectional view of a MISFET having an impurity profile according to the second embodiment. M
The ISFET includes a semiconductor substrate 31 of a first conductivity type and a substrate 31.
The gate insulating film 46 is in surface contact with the upper surface of the gate insulating film 46, and the gate electrode 47 is in surface contact with the upper surface of the insulating film 46. The substrate 31 includes a second conductivity type counter impurity region 44 located below the insulating film 46, a first conductivity type channel impurity region 45 located below the region 44, and a region 44 including the upper surface of the substrate 31. Source region 38 of second conductivity type in surface contact
And a drain region 39 of the second conductivity type including the upper surface of the substrate 31 and in surface contact with the region 44. Regions 44 and 4
The impurity profile of No. 5 is the impurity profile according to the second embodiment. Note that the sacrificial insulating film 33 is in contact with the upper surfaces of the source region 38 and the drain region 39.
Are arranged, and an interlayer insulating film 42 is arranged so as to be in surface contact with the upper surface of the insulating film 33.

Although the source region 38 and the drain region 39 do not extend below the gate electrode 47 in the drawing, the gate insulating film 46
It is preferable that the source region 38 and the drain region 39 are formed so as to extend therethrough. This makes it possible to reduce the gate source resistance and the gate drain resistance.

FIGS. 26 and 27 show the MIS having the channel impurity distribution of the second embodiment using the “damascene gate” process.
FIG. 4 is a process cross-sectional view illustrating a method for manufacturing the FET. By using a “damascene gate”, activation of source and drain impurities can be performed before forming the gate electrode without using polysilicon for the gate electrode 47. This not only allows a metal or metal compound to be used as the gate electrode 47, but also allows the gate electrode 47 to be used.
In the second embodiment, the high-temperature heat step or the heat step for activating the impurities in the source / drain regions 38 and 39, which is required when polysilicon is used, does not affect the channel impurity profile. It is possible to realize a channel impurity profile in which the concentration sharply decreases toward the surface, which is a characteristic. The manufacturing method will be described below.

(A) First, as shown in FIG.
100 nm thick on a silicon substrate 31 using a thermal oxidation method.
An m-th sacrificial insulating film 33 is formed. Next, an ion implantation method 49 is performed through the sacrificial insulating film 33 to introduce an n-type impurity. For example, phosphorus is introduced at a dose of 5 × 10 ¹³ cm ⁻² using an acceleration energy of 40 keV. This diffuses in a subsequent thermal process to form a counter impurity profile having a gentle concentration gradient near the substrate surface. Instead of using the ion implantation method, a silicon crystal layer containing an n-type impurity may be epitaxially grown to a thickness of 50 nm uniformly on the substrate surface.

(B) Next, as shown in FIG.
A dummy gate electrode pattern 35 having a thickness of about 50 to 200 nm is formed on the sacrificial insulating film 33 by using lithography and anisotropic etching. As the pattern 35, for example, a silicon oxide film containing hydrogen, a silicon oxide film formed by thermal oxidation, a silicon oxide film formed by thermal nitridation, an amorphous silicon film, or a polycrystalline silicon film is used. By using a silicon-based semiconductor film or an insulating film instead of a metal as the pattern 35 in this manner, the side surface roughness of the pattern 35 due to reactive ion etching (RIE) can be reduced, thereby reducing the variation in the gate length dimension. be able to.

Next, as shown in FIG. 26B, impurity ions are implanted using the pattern 35 as a mask, and then annealing is performed to form the source / drain impurity regions 38 and 3.
9 is formed.

The annealing for activating the source / drain regions 38 and 39 is performed before the formation of the channel impurity profile and the formation of the buried gate electrode 47 which are performed in a later step. Has no real effect.

(C) As shown in FIG. 26C, a silicon oxide film to be an interlayer insulating film 42 is formed on the entire surface by using the CVD method so as to cover the pattern 35. Next, the pattern 35
Until the silicon is exposed by chemical mechanical polishing (C
Polishing is performed by an MP) method or a mechanical polishing (MP) method.
As a result, the silicon oxide film is planarized, and the interlayer insulating film 42 can be formed. Note that the interlayer insulating film 42 may be a stacked film in which a silicon oxide film and a silicon oxide film containing phosphorus are stacked thereon.

(D) As shown in FIG. 27A, the pattern 35 and the sacrificial insulating film 33 are removed by a wet etching method to form an opening 41. A sacrificial oxide film 33 having a thickness of 5 nm is deposited inside the opening 41. Opening 41
, Ion implantation 50 of the channel impurity is selectively performed in the substrate 31 through the substrate. In the case of an nMISFET, indium (In) is injected at a dose of 5 × 10 ¹³ cm ^{−2 and} a dose of 20 × 10 ¹³ cm ^−2.
The injection is performed at an acceleration energy of 0 keV. 9 implanted ions
Activation is performed by using a rapid thermal annealing (RTA) method at 00 ° C. for 30 seconds. In the case of a pMISFET, for example, boron (B) is used as a counter impurity, and antimony (Sb) is used as a channel impurity. The ion implantation may be performed with the same dose and acceleration energy as in the case of the nMISFET.

(E) The sacrificial oxide film 33 is removed, and the gate insulating film 46 is formed by the CVD method. Next, FIG.
As shown in (b), a metal film 4 serving as a metal gate electrode
7. For example, TiN is formed on the entire surface of the substrate using the CVD method to fill the opening 41.

(F) Finally, the excess metal film 47 outside the opening 41 is removed by using the CMP method or the MP method.
ISFET is completed.

Fifth Embodiment A fifth embodiment relates to a MISFET having an impurity profile according to the first embodiment and a method of manufacturing the same. FIG. 28 is a cross-sectional view of a MISFET having an impurity profile according to the first embodiment.
The MISFET comprises a semiconductor substrate 31 of the first conductivity type and a substrate 3
A gate insulating film in surface contact with the upper surface of the first insulating film;
A first gate electrode 47 in surface contact with the upper surface of the first gate electrode, and a second gate electrode 48 in surface contact with the upper surface of the first gate electrode 47
It consists of. The substrate 31 includes a second conductivity type counter impurity region 44 located below the insulating film 46, a first conductivity type channel impurity region 45 located below the region 44,
A second conductivity type source region 36 including the upper surface of the substrate 31 and in surface contact with the region 44; a second conductivity type drain region 37 including the upper surface of the substrate 31 and in surface contact with the region 44;
And a second conductive type deep drain region 39 including the upper surface of the second conductive type and in surface contact with the region 36, and a second conductive type deep drain region 39 including the upper surface of the substrate 31 and in surface contact with the region 37. The impurity profiles of the regions 44 and 45 are as described in the first embodiment.
Is related to the impurity profile. The sacrificial insulating film 33 is arranged so as to be in surface contact with the upper surfaces of the source region 38 and the drain region 39 and in surface contact with the side surface of the insulating film 46. Sidewall 40 is arranged so as to make surface contact, and interlayer insulating film 42 is arranged so as to make surface contact with the upper surfaces of source region 38 and drain region 39 and make surface contact with insulating film 33 and the side surface of sidewall 40. I have. The insulating film 42 comes into surface contact with the side surfaces of the source region 38 and the drain region 39.
The element isolation region 32 is arranged so as to be in surface contact with the bottom surface of the device.

Although the source region 36 (source extension region) and the drain region 37 (drain extension region) do not reach below the gate electrode 47 in the drawing, the gate insulating film 46 is formed below the end of the gate electrode 47. Through the source region 36 and the drain region 37
It is desirable that the extension be formed. This makes it possible to reduce the gate source resistance and the gate drain resistance.

FIGS. 29 to 31 show a “damascene gate”.
MI having the impurity profile of Example 1 using the process
It is a process sectional view showing a method of manufacturing an SFET. The manufacturing method will be described below.

(A) First, the silicon substrate 31 is dry-etched to form trenches for element isolation. Next, an insulating film made of an insulating material such as a silicon oxide film is embedded in the groove by deposition or coating. The insulating film outside the isolation groove is C
By removing by MP method or MP method, FIG.
As shown in FIG. 9A, an element isolation region 32 is formed in a silicon substrate 31. Next, a sacrificial oxide film 33 having a thickness of about 3 nm is formed on the substrate 31 by a thermal oxidation method. A film 34 serving as a dummy gate pattern 35 is formed on the sacrificial oxide film 33 and the element isolation region 32. As the film 34, for example, a silicon oxide film containing hydrogen or a two-layer laminated film is used. In the case of a laminated film, a film having an etching rate higher than that of the sacrificial oxide film 33, for example, an amorphous silicon film is used as a lower layer, and an upper layer is formed as compared with the interlayer insulating film 42 in a polishing process of the interlayer insulating film 42 in a later step. A film having a low polishing rate, for example, a silicon nitride film is used.

(B) Next, as shown in FIG.
The film 34 is subjected to RI so that it has the same pattern as the gate electrode.
The dummy gate pattern 35 is formed by processing using anisotropic etching such as the E method. Subsequently, impurities are introduced into the substrate surface by ion implantation or the like using the pattern 35 as a mask. By heat-treating and electrically activating these impurities, source / drain regions 36 and 37 are formed. The introduction of the impurities may be performed by plasma doping, gas phase diffusion, or solid phase diffusion. The activation of the impurities is performed at a temperature rising rate of 100 ° C./sec or more and a temperature of 80 ° C./sec.
By performing the RTA at about 0 to 900 ° C. for 30 seconds or less, the depth of the source / drain regions 36 and 37 can be kept small.

(C) As shown in FIG.
A sidewall 40 made of a silicon nitride film or a silicon oxynitride film having a thickness of about 30 nm is formed. In order to form the sidewall, an insulating film is formed on the entire surface of the substrate including the pattern 35 by a chemical vapor deposition (CVD) method.
The insulating film is partially etched using the RIE method,
It is formed by leaving the insulating film only on the side wall of the pattern 35. Here, the insulating film is made of RI rather than pattern 35.
A material that reduces the etching rate by the E method is used. For example, when a silicon oxide film is used as the pattern 35, a silicon nitride film or a silicon oxynitride film (SiO 2
xNy) or the like. In the case of a polycrystalline silicon film, a silicon oxide film is used.

The thickness of 10 n is provided between the side wall 40 and the pattern 35 so that the side wall 40 does not recede in the lateral direction during the subsequent step of removing the pattern 35.
It is desirable to form an oxide film of m or less on the surface of the pattern 35 in advance.

Next, the side wall 40 and the pattern 3
5 as a mask by ion implantation on the substrate surface
Introduce impurities. This impurity can be activated electrically.
To form deep source / drain regions 38 and 39
Form. To increase the concentration of the activating impurities,
Beam, laser with ultraviolet wavelength, mercury laser
Using a lamp or xenon lamp
Heat treatment for one second or less may be performed. In addition, source dress
The activation of the in-regions 36 and 37 is performed by a deep source drain.
At the same time as activating the impurities in
You may go to. Deep source / drain regions 38 and 3
9 on top of cobalt silicide (CoSi ₂) Layer of gold
A metal silicide layer can also be formed.

As described above, in the "damascene gate transistor" process, unlike the case of the normal planar transistor process, the source and drain regions 36 and 37 and the deep source and drain regions are formed before the channel impurity profile is formed. 38 and 39 can be formed. As a result, the thermal step for activation does not receive channel impurities. Deep source / drain region 3
The thermal process for silicidizing the surfaces of the layers 8 and 39 does not receive channel impurities. Thus, a lightly doped drain (LDD) structure can be formed.

(D) Next, an interlayer insulating film 42 is formed on the entire surface of the substrate by the CVD method. As shown in FIG. 30A, the interlayer insulating film 42 is polished by the CMP method until the surface of the pattern 35 appears. By this polishing, the surface of the interlayer insulating film 42 is flattened.

(E) As shown in FIG. 30B, the pattern 35 and the sacrificial oxide film 33 are removed by using selective etching, and an opening 41 is formed. Next, as shown in FIG. 31A, impurity ions are implanted into the substrate surface through the opening 41. First, indium with a dose of 5 × 10 ¹³ cm ⁻² is implanted at an acceleration energy of 190 keV, and subsequently, antimony with a dose of 5 × 10 ¹¹ cm ⁻² is injected with 5 k.
The injection is performed at an acceleration energy of eV. 8
Activated by RTA at 50 ° C. for 30 seconds.

(F) As shown in FIG. 31B, as the gate insulating film 46, a SiOxNy film having a thickness of 2 to 3 nm,
Alternatively, a nitride film is formed at a temperature of 500 ° C. or lower by nitridation using a nitride radical or the like as a nitride species. As shown in the figure, the gate insulating film 46 is formed not only on the bottom surface of the opening 41 but also on the side wall using CVD, and also, the silicon substrate 31 with the bottom surface of the opening 41 exposed.
The gate insulating film 46 may be formed only on the bottom surface of the opening 41 by oxidizing the surface.

Next, TiN for determining the work function of the gate
A conductive film 47 serving as a first gate electrode having a thickness of 10 nm or less is formed using a material having metal conductivity such as a metal. T
When iN is used, the film forming conditions such as the composition of TiN, the film forming temperature, and the pressure are set so that the particle size of TiN becomes 30 nm or less.

Next, a conductive film 48 to be a second gate electrode
Is formed on the entire surface. Specifically, after an Al film is entirely formed by a sputtering method, the Al film is reflowed to form an opening 4.
1 is filled. Alternatively, a low-resistance metal film such as a W film is deposited as the conductive film 48 on the entire surface by the CVD method so as to fill the inside of the opening 41.

(G) Finally, as shown in FIG. 28, surplus gate insulating film 46,
8 is removed by the CMP method or the MP method. This flattens the polished surface. As described above, the gate insulating film 46 buried in the opening 41, the first gate electrode 47,
By forming the second gate electrode 48, the MIS
The transistor is completed. Thereafter, a contact to the source / drain diffusion layer is formed through the interlayer insulating film 42 for wiring, but the parasitic capacitance between the gate electrode and the contact or the wiring increases with miniaturization, and the speed and the like are increased. Degrades the circuit characteristics. In order to reduce this parasitic capacitance, the upper surface of the sidewall nitride film is exposed when the surface is planarized by the above-mentioned (g) CMP or MP method, and then the nitride film is introduced into the trench after the removal. It is also effective to bury an insulating film having a smaller dielectric constant than the above and to replace the side wall 40 with a low dielectric constant film. Examples of the film that replaces the side wall 40 include a silicon oxide film formed by low-pressure CVD, a fluorine-added silicon oxide film formed by plasma CVD, a low dielectric constant organic film or an organic-inorganic mixed film or an inorganic film formed by spin coating. Used.

Embodiment 6 Embodiment 6 relates to a MISFET having an impurity profile according to Embodiment 3 and a method of manufacturing the same. Example 6 is a method for manufacturing the transistor of the present invention without using the “damascene gate process”. The channel profile of the third embodiment does not use the “damascene gate process” as in the fourth or fifth embodiment, but also uses a heavy metal having a small diffusion coefficient as an impurity for forming a channel impurity profile according to a conventional planar transistor manufacturing method. In addition, it can be manufactured by minimizing a thermal process such as formation of a gate insulating film and activation of source and drain impurities or activation annealing when a gate electrode is formed of polysilicon. Although the concentration gradient that rapidly decreases in the channel surface of the channel impurity profile to the substrate surface becomes gentle, the variation in Vth can be reduced.

FIG. 32 is a sectional view of a MISFET having a channel profile according to the third embodiment. MISF
The ET includes a semiconductor substrate 31 of the first conductivity type, a gate insulating film 46 in surface contact with the upper surface of the substrate 31, and a gate electrode 47 in surface contact with the upper surface of the insulating film 46. The substrate 31
A second conductivity type counter impurity region 44 located below the insulating film 46, a second conductivity type source region 38 including the upper surface of the substrate 31 and in surface contact with the region 44, and a region 44 including the upper surface of the substrate 31; Surface-contact second conductivity type drain region 3
9 and a first conductivity type channel impurity region 45 located below the regions 44, 38 and 39. The impurity profiles of the regions 44 and 45 are the same as those of the third embodiment. The element isolation region 32 is arranged so as to be in surface contact with the side surfaces of the source region 38, the drain region 39, and the channel impurity region 45. Insulating film 3
An interlayer insulating film 42 is arranged so as to make surface contact with the upper surface of the gate electrode 47 and surface contact with the upper surface and the side surface of the gate electrode 47. An extraction electrode 56 is arranged so as to be in contact therewith.

FIG. 31 shows a MIS having a channel impurity distribution of Example 3 using a planar transistor manufacturing method.
FIG. 4 is a process cross-sectional view illustrating a method for manufacturing the FET. The manufacturing method will be described below.

(A) First, as shown in FIG.
An element isolation region 32 is formed on a substrate 31. Next, a sacrificial oxide film 33 having a thickness of 20 nm is formed. Indium having a dose of 1.2 × 10 ¹⁴ cm ⁻² is ion-implanted through the sacrificial oxide film 33 at an acceleration energy of 60 keV.
Thus, a channel impurity region 45 is formed.
Next, arsenic was implanted at an acceleration energy of 5 keV and a dose of 1 × 10
Ion implantation is performed at ¹² cm ⁻² . Thus, a counter impurity region 44 is formed.

(B) The sacrificial oxide film 33 is peeled off, and a gate oxide film 46 having a thickness of 5 nm is formed by a steam oxidation (hydrogen thermal oxidation) process at 850 ° C. for 10 minutes. Polysilicon is deposited by a CVD method. Through a photolithography process and a dry etching process by the RIE method, a gate electrode 47 is formed as shown in FIG.

(C) As shown in FIG. 33C, ion implantation is performed using the gate electrode 47 as a mask. Thus, not only can the source and drain impurity regions 38 and 39 be formed, but also impurities can be introduced into the polysilicon gate electrode 47. Next, the source / drain region 3
In order to activate the impurities in the gate electrodes 8 and 39 and the gate electrode 47, activation annealing is performed at a substrate temperature of 900 ° C. for 1 minute.

(D) Finally, an interlayer insulating film 42 is deposited.
A contact hole is formed using a lithography process using a mask. Then, as shown in FIG. 32, an aluminum film is formed by embedding it in the contact hole by a sputtering method.
The wiring 56 drawn out through a dry etching process by the IE method is formed. At this time, the peak position of the indium profile is 30 nm from the silicon surface.
In the vicinity, the peak concentration becomes about 3 × 10 ¹⁸ cm ⁻³ ,
The surface concentration is about 5 × 10 ¹⁷ cm ⁻³ . A conventional MISF having a pn junction in the channel region although indium diffuses due to a thermal process after ion implantation and has a high surface concentration
The channel impurity concentration in the net n-type impurity region is lower than that of ET, and a small Vth variation can be obtained.

(Embodiment 7) In Embodiment 7, a channel impurity profile of the present invention and a C
The present invention relates to a MOS transistor and a method for manufacturing the same. In an integrated circuit having CMOS transistors, both an nMOSFET and a pMOSFET are densely formed on the same substrate. Therefore, when a metal gate is used, nM
Simplification of the manufacturing process of the gate electrode used for the OSFET and the pMOSFET, and the nMOSFET and the pMOSF
It is necessary that each channel profile realizing a desired Vth with ET can be manufactured so that the variation of Vth is reduced. By using the low-concentration counter impurity profile of the present invention and the channel impurity profile having a steeply low concentration on the surface, pMO
Even if the SFET and the nMOSFET have a simple gate electrode using the same metal gate electrode material, a low Vt
h, and a CMOS integrated circuit with small Vth variation can be realized. Note that pMOSFET and nM
The channel profile or the like of the present invention can be used for only one of the OSFETs and the other channel can be used for the conventional channel profile. In this embodiment, a case where the OSFET is used for both the pMOSFET and the nMOSFET will be described.

FIG. 34 is a sectional view of a CMOS transistor having a channel impurity profile of the present invention and a metal gate electrode. CMOS transistors are nMISFETs and pMOSFETs arranged on a semiconductor substrate 31.
It is composed of

The nMOSFET includes a p-type semiconductor substrate 31,
A gate insulating film 46 in surface contact with the upper surface of the substrate 31, a first gate electrode 47 in surface contact with the upper surface of the insulating film 46, and a second gate electrode 48 in surface contact with the upper surface of the first gate electrode 47; Be composed. The substrate 31 includes a counter n-type impurity region 44 located below the insulating film 46, a channel p-type impurity region 45 located below the region 44, and an n-type source in contact with the region 44 including the upper surface of the substrate 31. Region 38
And an n-type drain region 39 including the upper surface of the substrate 31 and in surface contact with the region 44. The impurity profiles of the regions 44 and 45 are the impurity profiles according to the second embodiment. The interlayer insulating film 42 is arranged so as to make surface contact with the upper surfaces of the source region 38 and the drain region 39 and make surface contact with the side surface of the insulating film 46. The element isolation region 32 is arranged so as to make surface contact with the side surfaces of the source region 38 and the drain region 39 and make surface contact with the bottom surface of the insulating film 42. A contact (not shown) is formed between the source electrode and the drain electrode through the interlayer insulating film, and is connected to the wiring of the integrated circuit.

The pMOSFET includes a p-type semiconductor substrate 31 and
A gate insulating film 46 in surface contact with the upper surface of the substrate 31, a first gate electrode 47 in surface contact with the upper surface of the insulating film 46, and a second gate electrode 48 in surface contact with the upper surface of the first gate electrode 47; Be composed. The substrate 31 includes a counter p-type impurity region 44p located below the insulating film 46 and a region 44p.
, A p-type source region 38p including the upper surface of the substrate 31 and in surface contact with the region 44p, a p-type drain region 39p including the upper surface of the substrate 31 and in surface contact with the region 44p. , Regions 45p, 38p, and 39p. The impurity profiles of the regions 44p and 45p are the impurity profiles according to the second embodiment. The interlayer insulating film 42 is arranged so as to make surface contact with the upper surfaces of the source region 38p and the drain region 39p and make surface contact with the side surface of the insulating film 46. The element isolation region 32 is arranged so as to make surface contact with the side surfaces of the source region 38p and the drain region 39p and make surface contact with the bottom surface of the insulating film 42.

FIG. 35 is a process sectional view showing a method of manufacturing a CMOS transistor having a channel impurity profile and a metal gate electrode of the present invention by using a “damascene gate” process. As a manufacturing method, any of the methods described in the first to sixth embodiments can be used. Here, as an example, a CMOS structure is manufactured by using the manufacturing method of the channel profile of the fourth embodiment. Hereinafter, this manufacturing method will be described.

(A) First, nMOSFET and pMOSF
In order to electrically separate ET, a p-type silicon substrate 31 is used.
As shown in FIG. 35A, for example, in the same manner as described with reference to FIG. 29A of the fifth embodiment, the oxide film is flattened by a step of embedding an oxide film in a groove and a CMP method. The element isolation region 32 is formed.

Next, an n-well region 52 is formed in the substrate where the pMOSFET is to be formed. First of all,
For example, a 4 nm sacrificial oxide film is formed on the surface of the element region by thermal oxidation. Next, n
A region where a MOSFET is to be formed is covered with a resist 51. Using this resist as a mask, for example, phosphorus ions are implanted at an acceleration energy of 500 keV and a dose of 2 × 10 ¹³ cm ⁻² . Finally, thermal annealing is performed to diffuse the impurity in the n-well region 52 to a desired depth and activate the impurity at the same time. Instead of this annealing, activation may be performed by a heat process such as gate oxidation later.

Next, the method for manufacturing a counter impurity profile according to the fourth embodiment of the present invention is used for a pMOSFET.
First, ion implantation 53 is performed using the same resist as that used when the n-well region 52 is formed as a mask, and the pMOSFET
Is implanted to form a counter p-type impurity region 44p. The counter impurity of the pMOSFET is, for example, boron, and a dose of 1 × 10 ¹³ cm at an acceleration energy of 10 keV and an implantation angle of 0 °.
^-2 ions are implanted.

Next, the resist 51 on the substrate is peeled off, and the method for manufacturing a counter profile according to the fourth embodiment of the present invention is performed. First, a region for forming a pMOSFET is covered with a resist by using a photolithography technique, and ions are implanted using the resist as a mask to form a counter impurity region 44 of an nMOSFET. nMOSFET
As a counter impurity of arsenic, for example, arsenic is used, and arsenic is accelerated to 2 × 10 ¹² cm at an acceleration energy of 5 keV.
^The implantation is performed at a dose of ^-2 at 0 degree.

(B) Next, the resist was peeled off.
As described above, the film 34 serving as the dummy gate pattern in FIG. 29B is formed. Next, as described in FIG. 29B, a dummy gate pattern 35 is formed by lithography and anisotropic etching.

Next, as described with reference to FIG. 27B, using the pattern 35 as a mask, source and drain regions adjacent to both sides of the pattern 35 are formed. nM
A region where an OSFET or a pMOSFET is to be formed is sequentially covered with a resist using a photolithography method and one of the regions is masked. A p-type impurity is added to the source and drain regions 38p and 39p of the pMOSFET, and an nMOSF
N-type impurities are selectively ion-implanted into the source and drain regions 38 and 39 of the ET, respectively. Next, as described with reference to FIG. 29C, it is preferable to form a source / drain structure having an LDD structure in which a deep diffusion layer recessed from the channel region is added using the sidewall 40. At this time, as described above, a mask is sequentially formed using a resist or the like, and a p-type deep impurity layer is selectively introduced into the pMOSFET and an n-type deep impurity layer is selectively introduced into the nMOSFET.

Thereafter, the resist on the substrate is removed to activate the impurities. Also, as described in the fifth embodiment, the source / drain regions 38, 39, 38p, 39p
It is desirable to reduce the contact resistance to the source / drain by depositing a metal such as titanium or cobalt thereon and forming a silicide. In this embodiment, p
After the respective counter impurities of the MOSFET and the nMOSFET are introduced into the substrate, a heat step for forming and activating the source / drain impurity regions and silicidation is performed. As described in the fourth embodiment, the counter impurity has a gentle distribution due to these heat processes, and as described in the second embodiment, the variation in the profile is Vt due to the gentle counter impurity distribution.
The variation given to h can be reduced.

Next, as described with reference to FIG. 30A, the interlayer insulating film 42 is deposited, flattened by the CMP method, the pattern 35 is removed by etching, and the opening is formed as shown in FIG. 41 is formed.

(C) Next, channel impurities are implanted and n
Channel impurity region of MOSFET and pMOSFET
45 and 45p are formed. First, the silicon inside the opening 41
After removing the oxide film on the substrate surface, the exposed silicon substrate
On the surface of the plate, for example, a sacrifice oxide film of 2 nm is formed at about 750 degrees.
Formed by moderate steam oxidation. Heat as sacrificial oxide film
Use chemical oxide film by COM processing etc. to reduce the process
May be. Next, as shown in FIG.
NMOSFET and pMOSF using the method of
One of the ETs is covered with a resist and masked, and pMOSFE
The surface is steep in the channel region of T through the opening 41.
N-type impurity ion implantation 55 having a low concentration
In addition, the concentration must be high enough to suppress short channel effects.
U. As an n-type impurity whose surface becomes steeply low concentration,
If antimony is present, the acceleration energy of 130 keV
At an injection angle of 0 °, 4 × 10¹³cm^-2Dose
Inject. Similarly, the channel region of the nMOSFET
In addition, the p-type impurity ion implantation is selectively and sufficiently high.
Perform the concentration. As a p-type impurity, for example, indium is used.
And an injection angle of 0 degree with an acceleration energy of 130 keV
And 2 × 10¹³cm ^-2Is implanted.

(D) Finally, the resist on the substrate is removed,
A gate insulating film and a gate electrode are formed as described with reference to FIG.
Complete OSFET and nMOSFET.

Since the desired Vth can be realized without variation using the channel profile of the present invention in accordance with the work function of the gate electrode, pMOSFET and nMOSF
Both gate electrodes of ET can be formed at the same time, that is, a single gate structure can be used, greatly simplifying the process and eliminating costs compared to the case of dual gate,
Further, the yield can be increased.

In order to use a single gate structure, the channel profile of the present invention is changed to pMOSFET and nM
The use of both with the OSFET increases the difficulty of the channel profile forming process. Desired Vth
It is also effective to set the work function value of the single gate to a value deviated from the mid gap so that the profile formation of the nMOSFET or the pMOSFET becomes easier according to the above. Also, pMOSFET and nMOS are formed as a single gate using the same metal or metal compound material.
The first gate electrode 47 and the second gate electrode 48 of both FETs are formed, and at this time, an additional step is added to only one of them, and only one of the first gate electrodes 47 is modified or its composition is changed. To change its work function,
A desired Vth may be realized for both the SFET and the nMOSFET.

As an additional step to be added to one side,
After the gate electrode 47 is formed using CVD or PVD, the work function of the metal or metal compound can be changed by changing the crystal orientation of the metal or metal compound. Alternatively, an additional impurity such as nitrogen can be implanted into one of the gate electrodes 47 to change its work function.

The channel profile of the present invention is pMOS
After using both or one of FET and nMOSFET,
By adjusting the work function value of the single gate and, if necessary, making additional adjustments to pMOSFETs and / or nMOSFETs, V
and a high-performance metal gate CMOS integrated circuit having a threshold value th.

(Eighth Embodiment) FIG. 36 is a diagram showing a channel impurity profile and a counter impurity profile of a pMOSFET having a metal gate according to an eighth embodiment of the present invention. The horizontal axis is the depth from the silicon interface, and the vertical axis is the impurity concentration obtained by using a process simulation. The dots in the figure indicate the profile immediately after ion implantation, and the solid line indicates the final profile after the thermal process. The channel impurity is antimony (Sb), and the counter impurity is boron (B). Note that phosphorus is n
This is an impurity that has been deeply ion-implanted in advance to form a well. As a result, the concentration of antimony as a channel impurity at a concentration of about 40 nm from the silicon surface is 5 × 10 ¹⁸ c.
The density is as high as m ⁻³ or more, and the concentration is sharply lowered toward the substrate surface. Further, the low concentration region is doped with boron as a counter impurity, and the concentration decreases toward the substrate surface, and the boron concentration decreases at the substrate surface. These are shown in FIGS. 12A and 12B.
, A channel impurity profile and a counter impurity profile are formed.

Next, the p-type semiconductor device according to the eighth embodiment having the metal gate
A method for manufacturing a MOSFET will be described. First, the steps up to the step illustrated in FIG. 30B are performed as in the fifth embodiment. Next, after removing the dummy gate, antimony is accelerated at an energy of 130 keV and a dose of 4 × 1 through a sacrificial oxide film having a thickness of 3 nm.
Ion implantation is performed at 0 ¹³ cm ⁻² , and then boron is implanted at an acceleration energy of 5 keV and a dose of 8 × 10 ¹² cm ⁻² . Next, the sacrificial oxide film is peeled off, and a 3 nm-thick gate insulating film is formed by steam oxidation at 750 degrees.
Subsequent steps are the same as those of the fifth embodiment, and start with the step described with reference to FIG.

As described above, immediately after antimony ion implantation, boron is superimposed and deeply introduced so as to overlap with the substrate surface side of the antimony profile where the surface sharply becomes low in concentration. The boron concentration in the substrate is kept high even after the final step such as the gate oxidation step. on the other hand,
Boron, which is ion-implanted shallowly into the substrate surface, diffuses from the silicon surface into the oxide film by the subsequent heat treatment, and further diffuses out of the substrate, reducing the boron concentration. Further, in the eighth embodiment, by distributing boron having a negative charge on antimony having an opposite positive charge, boron is attracted to antimony by an electric field effect. As a result, a counter impurity distribution having a low concentration from the pn junction toward the silicon substrate surface can be obtained.

(Embodiment 9) FIG. 37 shows the result of a computer experiment on the variation of Vth caused by the statistical variation in the number or arrangement of the atoms of channel impurities and counter impurities using device simulation. This computer experiment method is basically the same as the method used by the present inventors in the case of a surface channel device (Kazumi Nishinoha
ra et al. “Effects of Microscopic Fluctuztions in Dopa
nt Distributions on MOSFET Threshold Voltage, ”IE
EE Transactions onElectron Devices, Vo1,39, pp634-63
9,1992). Hereinafter, this method will be described.

First, in the device simulation, when the device structure is discretized in a lattice shape to calculate the device characteristics, for each discretized unit region, the device concentration is obtained from the set impurity concentration and the volume of this unit region. The number of impurities to be obtained is calculated. Next, the number of impurities is set as an average value of the number of impurities in the unit region, and a random number is separately generated on a computer to vary the number of impurities around the average value. The set impurity concentration is replaced with the impurity concentration corresponding to the changed number of impurities. In this way, an impurity concentration profile having variation is obtained,
The device simulation is performed using this. The random number distribution used is a Poisson distribution.

One device structure sample corresponding to the random number sequence is obtained by one random number sequence generation. Ten samples were generated for each impurity profile, and each Vth was determined. Three types of impurity profiles used in the experiment will be described. These relate to the case of a metal gate nMOSFET and will be described in detail below.

(1) The impurity profile of FIG. The channel impurity concentration was 2 × 10 ¹⁸ cm ⁻³ , the counter impurity concentration was 5.3 × 10 ¹⁸ cm ⁻³ , and the counter impurity region 2 reached a depth of 10 nm from the semiconductor surface.

(2) The impurity profile of FIG.
The concentration in the high concentration region of the channel impurity profile is 5 × 1
0 ¹⁸ cm ⁻³ , counter impurity concentration 1.6 × 10
¹⁸ cm ⁻³ , the depth at point B was 25 nm, and the counter impurity region 2 reached a depth of 10 nm from the semiconductor surface.

(3) The impurity profile of FIG. 7 (b).
The concentration in the high concentration region of the channel impurity profile is 5 × 1
0 ¹⁸ cm ⁻³ , counter impurity concentration is 8.3 × 10
¹⁷ cm ⁻³ and the depth of point B were 25 nm.

The gate length L = 95 nm and the channel width W0 = 95 nm.

In general, the statistical variation of the impurity distribution is averaged by increasing the width W with respect to W0, and Vth
The variation is reduced to about (W0 / W) ^1/2 . Each counter impurity concentration was adjusted so that Vth = 0.4 V in an impurity distribution that did not cause variation. As shown in FIG. 37, when the high n-type impurity concentration and the high p-type impurity concentration cancel each other out on the substrate surface having the profile of FIG. 1, the statistical variation in the atomic distribution gives the largest Vth variation. In the case of the impurity profile of the present invention, in which the high concentration portion of the counter impurity is provided on the substrate surface of FIG. 8, the Vth variation was about 1/3 or less as compared with the profile of FIG. Further, the Vth variation is smaller in the case of the profile of FIG. 7 in which the counter impurity is distributed to the depth of the substrate and the substrate surface concentration is lower than in the case of the profile in FIG.

The statistical variation of the atomic distribution is caused by ion implantation,
If a device is manufactured using a manufacturing process having statistical properties such as thermal diffusion, it cannot be excluded in principle. It is thought that as the gate length becomes shorter with miniaturization, the area of the channel region becomes smaller, the number of impurity atoms contained in the channel depletion layer becomes smaller, and the variation in the number and arrangement of the device characteristics increases the device characteristics. Can be The channel profile of the present invention is:
MI due to channel impurity distribution with counter impurity
This is effective for improving the yield when manufacturing SFETs for very miniaturized integrated circuits.

As described above, the present invention has been described with nine embodiments, but it should not be understood that the description and drawings forming part of this disclosure limit the present invention.
From this disclosure, various alternative embodiments, examples, and operation techniques will be apparent to those skilled in the art. Therefore, the technical scope of the present invention is defined only by the matters specifying the invention according to the claims that are appropriate from the above description.

[0179]

As described above, according to the present invention,
A semiconductor device capable of suppressing variation in Vth due to a short channel effect and manufacturing variation can be provided.

Further, according to the present invention, it is possible to provide a method of manufacturing a semiconductor device which suppresses variations in Vth due to short channel effects and manufacturing variations.

[Brief description of the drawings]

FIG. 1 is a schematic diagram of a typical impurity profile in a semiconductor immediately below a gate oxide film of an nMOSFET forming a buried channel.

FIG. 2 is a graph showing Vth with respect to a counter impurity concentration and Vth variation due to variation in a counter impurity profile when a typical buried channel structure is used for a metal gate.

FIG. 3 is a schematic diagram of a channel impurity profile of a semiconductor immediately below a gate oxide film of an nMOSFET forming a surface channel.

FIG. 4 is a diagram conceptually showing a variation in Vth with respect to a variation in gate length (L).

5 is a graph showing the relationship between Vth and the SCE range with respect to the distance from the semiconductor surface to the step when the step-like profile shown in FIG. 3 is used for a metal gate.

FIG. 6 is a sectional view of a MOSFET.

FIG. 7 is a basic impurity profile immediately below a gate insulating film of a semiconductor device according to an embodiment of the present invention. FIG.
(A) relates to net impurities and (b) relates to channel impurities and counter impurities.

FIG. 8 is a modification (part 1) of the basic impurity profile of FIG. 7 immediately below the gate insulating film of the semiconductor device according to the embodiment of the present invention;

FIG. 9 is a modification (part 2) of the basic impurity profile of FIG. 7 immediately below the gate insulating film of the semiconductor device according to the embodiment of the present invention;

FIG. 10 is a modification (part 3) of the basic impurity profile of FIG. 7 immediately below the gate insulating film of the semiconductor device according to the embodiment of the present invention;

FIG. 11 is a modification (part 4) of the basic impurity profile of FIG. 7 immediately below the gate insulating film of the semiconductor device according to the embodiment of the present invention;

FIG. 12 is a modification (part 5) of the basic impurity profile of FIG. 7 immediately below the gate insulating film of the semiconductor device according to the embodiment of the present invention;

FIG. 13 is a graph showing an energy band diagram of an nMOSFET and a potential in a depth direction.

FIG. 14 is an energy band diagram of an nMOSFET for generating a surface channel.

FIG. 15 shows an nMOSFET for generating a buried channel.
FIG. 4 is an energy band diagram of FIG.

FIG. 16 is a modification (part 6) of the basic impurity profile of FIG. 7 immediately below the gate insulating film of the semiconductor device according to the embodiment of the present invention;

FIG. 17 is a graph showing the relationship between the Vth and the SCE range with respect to the concentration of counter impurities when the stepped profile shown in FIG. 7 is used for the metal gate.

FIG. 18 is a graph showing the relationship between Vth and Vth variation with respect to the concentration of counter impurities when the stepped profile shown in FIG. 7 is used for a metal gate.

19 is an impurity profile (part 1) that can be realized by ion implantation, thermal diffusion, or the like based on the profile of the step-like deformation in FIG. 9, and the gate voltage is equal to the threshold voltage Vt.
h represents the hole concentration distribution.

FIG. 20 is a table 3 showing the effectiveness of the first embodiment.
4 is a diagram showing a kind of channel impurity profile.

21 is a graph showing Vth variation with respect to profile variation of channel impurities and counter impurities in the three types of profiles of FIG. 20.

FIG. 22 shows an impurity profile that can be realized by ion implantation, thermal diffusion, or the like based on the step-like profile of FIG. 7, and a hole concentration distribution when the gate voltage is a threshold voltage Vth.

23 is a graph showing Vth variation with respect to profile variation of channel impurity and counter impurity in each case where the shape of the counter impurity profile of FIG. 22 is changed in three ways.

FIG. 24 shows an impurity profile (part 2) that can be realized by ion implantation, thermal diffusion, or the like based on the profile of the step-like deformation in FIG. 9, and a hole concentration distribution when the gate voltage is Vth.

FIG. 25 is a cross-sectional view of a MISFET having an impurity profile according to the second embodiment.

FIG. 26 is a process cross-sectional view (part 1) illustrating a method for manufacturing a MISFET having an impurity profile of Example 2 using the “damascene gate” process.

FIG. 27 is a process cross-sectional view (part 2) illustrating the method for manufacturing the MISFET having the impurity profile of the second embodiment by using the “damascene gate” process.

FIG. 28 is a cross-sectional view of a MISFET having an impurity profile according to the first embodiment.

FIG. 29 is a process cross-sectional view (part 1) illustrating the method of manufacturing the MISFET having the impurity profile of the first embodiment using the “damascene gate” process.

FIG. 30 is a process cross-sectional view (part 2) illustrating the method of manufacturing the MISFET having the impurity profile of the first embodiment using the “damascene gate” process.

FIG. 31 is a process cross-sectional view (part 3) illustrating the method of manufacturing the MISFET having the impurity profile of the first embodiment using the “damascene gate” process.

FIG. 32 is a cross-sectional view of a MISFET having a channel profile according to the third embodiment.

FIG. 33 is a process sectional view illustrating the method of manufacturing the MISFET having the channel impurity distribution of the third embodiment using the method of manufacturing the planar transistor.

FIG. 34 is a cross-sectional view of a CMOS transistor provided with a channel impurity profile and a metal gate electrode according to the present invention.

FIG. 35 is a process sectional view showing a method of manufacturing a CMOS transistor having a channel impurity profile and a metal gate electrode of the present invention by using a “damascene gate” process.

FIG. 36 is a diagram illustrating a channel impurity profile and a counter impurity profile of a pMOSFET having a metal gate according to an eighth embodiment of the present invention.

FIG. 37 is a graph showing variations in the number or arrangement of atoms of channel impurities and counter impurities given to Vth.

[Explanation of symbols]

Reference Signs List 1 channel impurity profile 2 counter impurity profile 3, 7, 9, 10, 21 dotted line 4, 5, 6 line segment 8 solid line 11 semiconductor substrate 12, 36 source region 13, 37 drain region 14, 46 gate insulating film 15, 47 gate Electrode 16 Plane extending to include bottom surfaces of source region and drain region 17 Coordinate axis 18 Net impurity profile of first conductivity type 19 Net impurity profile of second conductivity type 23 Interface between gate insulating film and semiconductor substrate (substrate) Front surface) 24 pn junction surface 25 Position where channel impurity concentration sharply decreases 26 Peak position of counter impurity concentration 31 Semiconductor substrate 32 Element isolation region 33 Sacrificial insulating film 34 Film 35 Dummy gate electrode pattern 38, 38p Deep source region 39, 39p Deep drain region 40 side wall Lumpur 41 opening 42 interlayer insulating film 43,49,50,53,55 ion implantation 44,44p counter impurity regions 45,45p channel impurity region 48 a second gate electrode 51, 54 resist 52 n-well region 56 extraction electrode

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/8238 H01L 29/78 301L 27/092 21/336 (72) Inventor Kyoichi Suguro Isogo, Yokohama-shi, Kanagawa 8F, Shinsugita-cho, Tokushima F-term in Toshiba Yokohama Office (Reference)

Claims (25)

[Claims] A first conductive type first semiconductor region provided inside a semiconductor; and a first conductive type impurity provided and contained between the first semiconductor region and a surface of the semiconductor. A second semiconductor region of a second conductivity type having an active concentration of less than one-fourth of an active concentration of the impurity of the first conductivity type of the first semiconductor region; and An insulating film provided above the region; a conductor provided on the insulating film; a third semiconductor region of the second conductivity type including the surface and in contact with a side surface of the second semiconductor region; And a fourth semiconductor region of a second conductivity type in contact with a side surface of the second semiconductor region. 2. The method according to claim 1, wherein an active concentration of impurities of a first conductivity type forming the first semiconductor region becomes lower toward the surface, and a ratio of a concentration per 3 nm is smaller than 0.9. The semiconductor device according to claim 1, wherein: 3. An impurity active concentration of a second conductivity type at an end of the second semiconductor region on the semiconductor inner side is equal to a maximum of an impurity of a first conductivity type in a depletion layer during operation of the semiconductor device. 2. The method according to claim 1, wherein the density is less than one half.
Alternatively, the semiconductor device according to claim 2. 4. The semiconductor device according to claim 1, wherein an active concentration gradient of the second conductivity type impurity is smaller than an active concentration gradient of the first conductivity type impurity at an end of the second semiconductor region on the semiconductor inner side. The semiconductor device according to claim 1 or 2, wherein 5. An active concentration of said second conductivity type impurity at an end of a depletion layer during operation of said semiconductor device is 4 times a maximum of an active concentration of said first conductivity type impurity in said depletion layer. The semiconductor device according to claim 1, wherein the semiconductor device is smaller than one-half. 6. A semiconductor device according to claim 1, wherein a peak position of an impurity profile of a second conductivity type forming the second semiconductor region is located closer to the surface than an end of the second semiconductor region on the semiconductor inner side. The semiconductor device according to claim 1, wherein: 7. The method according to claim 7, wherein a peak position of the impurity profile of the second conductivity type forming the second semiconductor region is
7. The semiconductor device according to claim 1, wherein the first conductive type impurity active concentration is lower than half of the second conductive type impurity active concentration. 8. 8. An impurity active concentration of the first conductivity type on the surface is 4% of an impurity active concentration of the second conductivity type.
The semiconductor device according to claim 1, wherein the semiconductor device is smaller than one-half. 9. The active concentration of the impurity of the second conductivity type at the surface of the second semiconductor region at an end of the second semiconductor region on the semiconductor inner side, or
The ratio of the active concentration of the impurity of the second conductivity type to the maximum value of the impurity of the second conductivity type in the second semiconductor region is smaller than 10, and the ratio of the active concentration of the impurity of the second conductivity type at the end portion is 10 minutes. The semiconductor device according to claim 1, wherein the semiconductor device is larger than one. 10. The method according to claim 1, further comprising: forming a first semiconductor region.
10. The method according to claim 1, wherein the profile of the conductivity type active impurity concentration distribution toward the surface has a steep low concentration, and has a portion having a concentration ratio per nm of less than 0.9. 2. The semiconductor device according to item 1. 11. The semiconductor device according to claim 1, wherein the first conductivity type impurity is indium.
3. The semiconductor device according to claim 1. 12. The semiconductor device according to claim 1, wherein the impurity of the second conductivity type is phosphorus. 13. The semiconductor device according to claim 1, wherein the second conductivity type impurity is antimony or arsenic. 14. The semiconductor device according to claim 1, wherein said first conductivity type impurity is antimony or arsenic. 15. The semiconductor device according to claim 1, wherein the impurity of the second conductivity type is boron. 16. The semiconductor device according to claim 1, wherein said impurity of the second conductivity type is indium.
5. The semiconductor device according to any one of 4. 17. The semiconductor device according to claim 1, wherein the conductor is a metal or a metal compound. 18. The semiconductor device according to claim 1, wherein the semiconductor device includes the semiconductor device having the first conductivity type of p-type and the semiconductor device having the first conductivity type of n-type.
18. The semiconductor device according to any one of claims 17 to 17. 19. The conductor of the semiconductor device, wherein the first conductivity type is p-type, and the conductor of the semiconductor device, wherein the first conductivity type is n-type, are the same metal or metal compound. The semiconductor device according to claim 18, wherein: 20. An active concentration profile in which an active concentration of a second region deeper than that of a first region including a semiconductor surface is four times or more higher than an active concentration of a first region including a semiconductor surface. A first step, a second step of distributing a second conductivity type impurity in the first region beyond an active concentration of the first region, and a third step of forming an insulating film on the semiconductor surface A fourth step of forming a conductor on the insulating film; and a fifth step of forming a second conductivity type semiconductor region including a semiconductor surface on both sides of the second region. Semiconductor device manufacturing method. 21. First, the fifth step is performed. Next, an opening for embedding the conductor is formed. Next, the first step is performed through the first conductive layer through the opening. 21. The method of manufacturing a semiconductor device according to claim 20, wherein the method is performed by introducing a type impurity into the semiconductor, and finally, the third step and the fourth step are performed. 22. The method according to claim 21, wherein the second step is performed after forming the opening. 23. The method according to claim 21, wherein the second step is performed before the fifth step. 24. The method according to claim 20, wherein the insulating film is formed by using a chemical vapor deposition method. 25. In a step after the fourth step, 85
25. The method of manufacturing a semiconductor device according to claim 20, wherein a duration of 0 degree or more is 60 seconds or less.