JP2003298047A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To form a semiconductor element (a MIS field-effect transistor or a bipolar transistor) of an SOI structure (including an SON structure) on a semiconductor substrate, using an easy technique. <P>SOLUTION: A pair of vertical epitaxial silicon layers 5 are provided between a nitride film 2 and an oxide film 4 selectively provided on a p-type silicon substrate 1. Between the vertical epitaxial silicon layers 5, a transverse epitaxial silicon layer 7 (SON substrate) is provided with a void (space) directly above the nitride film 2 between while both ends are in contact with the vertical epitaxial silicon layer 5. On a part of the transverse epitaxial silicon layer 7, a gate electrode 15 having a barrier metal 14 is provided via a gate oxide film 13 in between. The transverse epitaxial silicon layer 7 is provided with n<SP>+</SP>type and n type source/drain regions (9, 8), while being self-aligned with the gate electrode 15. A conductive film 12, comprising a barrier metal 11 that is insulated/separated at the gate oxide film 13, is provided on both ends of the gate electrode 15, while being in contact with the n<SP>+</SP>source/drain region 8, and an N-channel MIS field-effect transistor is formed. <P>COPYRIGHT: (C)2004,JPO

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION This invention is SOI (S ilicon
O n I nsulator) structure or SON (S
relates to a semiconductor integrated circuit ilicon O n N othing) structure, particularly in the semiconductor substrate (bulk wafer),
A low-cost SOI substrate or SON substrate is formed by an easy manufacturing process, and this SOI substrate or SO
The present invention relates to forming a high-speed, low-power, high-reliability, high-performance semiconductor device including a short-channel MIS field-effect transistor or a bipolar transistor on an N-substrate. 2. Description of the Related Art Conventionally, as for a semiconductor device having an SOI structure, a semiconductor integrated circuit using a so-called bonded SOI wafer, in which a semiconductor substrate having a uniform single crystal is bonded to another semiconductor substrate via an oxide film, is beginning to be put into practical use. However, since the use of two semiconductor substrates and the necessity of forming an extremely thin SOI substrate for complete depletion, the yield is low, and commercially available bonded SOI wafers are extremely expensive. There are drawbacks. A so-called SIMOX method of forming an oxide film inside the bulk wafer by high-temperature heat treatment by implanting oxygen ions into a normal semiconductor substrate (bulk wafer),
The formation of the I-substrate has disadvantages such as the purchase of an expensive high-dose ion implantation machine, high cost due to a long manufacturing process, and instability of characteristics when using a large-diameter wafer. At the research stage, by forming a trench in the silicon substrate and adding H ₂ annealing,
As for the SON structure in which silicon is melted to form a hollow structure inside the silicon substrate, the channel region is flattened,
There is a problem that it is difficult to obtain an extremely thin SON substrate that can be formed into a fully depleted type. At present, ignoring the problem of high cost, it has been practically used only for portable devices that require extremely high speed and low power consumption, and for system LSIs with mixed analog / digital. LDD using a side wall (L ightly
D oped D rain) around the MIS field effect transistor of short channel structure obtained by forming the SOI substrate which are separated by an insulating layer, the junction capacitance, the depletion layer capacitance, high speed and low by reducing the threshold voltage and the like Although power is measured, on the other hand, miniaturization is attempted due to the fact that the contact resistance of the source / drain region is increased due to the formation on a thin-film SOI substrate and the resistance of each element is not reduced. Has the drawback that high speed has not been achieved. Further, when a voltage different from the voltage applied to the gate electrode is applied to a conductor (semiconductor substrate or lower layer wiring) under the SOI substrate, a small back channel leak generated at the bottom of the SOI substrate cannot be prevented. There was also the disadvantage that reliability was not achieved. Therefore, a fully depleted SOI structure (including a SON structure) can be formed by a low-cost and easy process, further miniaturization is possible, the resistance of each element including a contact resistance can be reduced, and a higher speed can be achieved. SOI structure (SOI structure
Means capable of forming a semiconductor device (including an N structure) are demanded.

[0002]

2. Description of the Related Art FIG. 33 is a schematic side sectional view of a conventional semiconductor device, and shows a semiconductor device formed using a bonded SOI wafer.
It shows a part of a semiconductor integrated circuit including an N-channel MIS field-effect transistor having an OI structure, 61 is a first p-type silicon substrate, 62 is an oxide film for bonding, and 63 is a second p-type silicon film. A silicon substrate (SOI substrate), 64 is a trench for forming an element isolation region and a buried oxide film, 65 is an n-type source / drain region, 66 is an n ⁺ -type source / drain region, 67 is a gate oxide film (SiO ₂ ), and 68 is a gate. Electrodes, 69 is a base oxide film, 70 is a sidewall (SiO ₂ ), 71 is an oxide film for impurity blocks, 72 is a PSG film, and 73 is a barrier metal (Ti / TiN).
), 74 is a conductive plug (W), 75 is a barrier metal (Ti / T)
iN), 76 denotes an Al wiring, and 77 denotes a barrier metal (Ti / TiN). In the figure, a p-type thin film is bonded on a first p-type silicon substrate 61 via an oxide film 62 and is insulated and isolated in an island shape by a trench for forming an element isolation region and a buried oxide film 64. Second silicon substrate (SOI
A p-type second silicon substrate (SOI substrate) 63 is provided with an MIS having an N-channel LDD structure.
A field effect transistor is formed. Therefore,
A reduction in junction capacitance by forming a source / drain region surrounded by an insulating film, a reduction in depletion layer capacitance by being able to completely deplete the SOI substrate, and a reduction in threshold voltage by being able to improve sub-threshold characteristics;
By removing the contact region from the I-substrate or the like, higher speed, lower power, and higher integration can be achieved as compared with a semiconductor integrated circuit including MIS field-effect transistors formed on a normal bulk wafer. However, a fully-depleted thin film SOI
Since it is formed on a substrate, the contact resistance of the source / drain region increases, and the resistance of each element is not reduced. Was. When a voltage different from the voltage applied to the gate electrode is applied to a conductor (semiconductor substrate or lower wiring) under the SOI substrate, the SO
There is also a drawback that high reliability has not been achieved due to failure to prevent minute back channel leak at the bottom of the I-substrate. Furthermore, in order to make such an SOI structure, a commercially available bonded SOI wafer must be purchased, and even if the cost reduction technology of a wafer maker is relied on, it is three times as large as a bulk wafer in a mass production stage. There is a disadvantage that the cost is extremely high, about five times.

[0003]

The problem to be solved by the present invention is that, as shown in the prior art, in order to obtain a semiconductor device with improved high-speed performance, a fully depleted thin film S is required.
An OI substrate is required. In order to form a source / drain region on the thinned SOI substrate, the SOI substrate forming the source / drain region is over-etched when etching the interlayer insulating film for forming a conductive plug. Inevitably, the contact with the conductive plug can be obtained, but the contact resistance of the source / drain region increases, and the capacitance can be reduced, but the resistance of the thin source / drain region and the resistance of the gate electrode are reduced. Higher speed could not be achieved despite miniaturization due to inability, etc., when forming C-MOS or SOI
When there is a lower wiring to which a voltage different from the voltage applied to the gate electrode is applied below the substrate, high reliability cannot be obtained due to inability to prevent back channel leakage, and in order to form an SOI structure, Laminated SOI
Using a wafer or SIMOX method
Even if an OI substrate is formed, the current technology is considerably expensive, so that it can be used only for special-purpose products with high added value, and there is little technology applicable to inexpensive general-purpose products.

[0004]

The object of the present invention is to provide a semiconductor substrate and a vertically (vertically) selectively provided on the semiconductor substrate.
A direction epitaxial semiconductor layer, an insulating film selectively provided on the semiconductor substrate, and a part of a side surface of the longitudinal (vertical) direction epitaxial semiconductor layer via a hole (space) on the insulating film. The problem is solved by the semiconductor device of the present invention comprising the lateral (horizontal) epitaxial semiconductor layer provided and a semiconductor element provided at least in the lateral (horizontal) epitaxial semiconductor layer.

[0005]

[Operation] That is, the main points constituting the semiconductor device of the present invention are (1) a semiconductor substrate (2) an insulating film (Si ₃ N ₄ ) formed on the semiconductor substrate, and (3) a part of the insulating film is opened. The semiconductor substrate exposed by the hole (4) The vertical (vertical) epitaxial semiconductor layer (5) formed on the exposed semiconductor substrate (5) The exposed portion (6) formed on a part of the side surface of the vertical epitaxial semiconductor layer (7) Spaces formed at the exposed side and lower portions of the vertical epitaxial semiconductor layer (7) Lateral (horizontal) epitaxial semiconductor layers formed from the exposed side surfaces of the vertical epitaxial semiconductor layer (8) Lateral epitaxial semiconductor Voids formed immediately below the layer (pores in which the space is closed) (9) Consisting of more than semiconductor elements formed in the lateral epitaxial semiconductor layer (SON substrate). Further, a further point is that a lateral epitaxial semiconductor layer is converted into an SON substrate by burying an insulating film in the closed hole, or a gate electrode is buried in the closed hole through a gate insulating film via a gate insulating film. An MIS field-effect transistor having an encircling gate electrode structure, or a polycrystalline silicon layer doped with impurities is buried in these closed holes to form a buried low-resistance layer required for a bipolar transistor. Things. Therefore, the vertical epitaxial semiconductor layer is provided on the selectively exposed semiconductor substrate, a part of the side surface of the vertical epitaxial semiconductor layer is exposed on the space, and the lateral epitaxial semiconductor layer unaffected by the base is bridged. With the provision, a semiconductor layer over a hole having extremely few crystal defects can be formed. That is, without using an expensive bonded SOI wafer, an inexpensive wafer is used, a relatively easy technique is used, and a highly-depleted SOI structure with extremely high reliability and easy film thickness control ( (Including SON structure)
Can be formed. The inventor of the present application space bridged epitaxy the art (S pa
tial B ridge E pitaxy) a name not a only, referred to hereinafter as SBE.

[0006]

BRIEF DESCRIPTION OF THE DRAWINGS FIG.
I will tell. FIG. 1 shows a first embodiment of the semiconductor device of the present invention.
FIG. 2 is a schematic side sectional view of the example in the channel length direction, and FIG.
Schematic in the channel width direction of the first embodiment in the conductor device
FIG. 3 is a side sectional view, and FIG. 3 shows a second embodiment of the semiconductor device of the present invention.
FIG. 4 is a schematic side sectional view of an embodiment, and FIG.
FIG. 5 is a schematic side sectional view of a third embodiment according to the present invention, and FIG.
FIG. 6 is a schematic sectional side view of a fourth embodiment of the apparatus,
5 is a schematic side sectional view of a fifth embodiment of the semiconductor device according to the present invention;
FIG. 7 is a schematic view of a sixth embodiment of the semiconductor device of the present invention.
FIG. 8 is a side sectional view, and FIG. 8 shows a seventh embodiment of the semiconductor device of the present invention.
FIG. 9 is a schematic side sectional view of an embodiment, and FIG.
FIG. 10 is a schematic side sectional view of an eighth embodiment according to the present invention, and FIG.
FIG. 11 is a schematic side sectional view of a ninth embodiment of the body device,
10th Embodiment Channel in Semiconductor Device of Present Invention
FIG. 12 is a schematic side sectional view of the semiconductor device of the present invention.
Side sectional view of the tenth embodiment in the channel width direction
FIG. 13 and FIG. 13 show an eleventh embodiment of the semiconductor device of the present invention.
Schematic cross-sectional view of example (with lateral epitaxial silicon layer
FIG. 14 shows a first example of the semiconductor device of the present invention.
1 is a schematic cross-sectional side view (lateral epitaxial
FIG. 15 shows a semiconductor device of the present invention.
16 to 23 are schematic side sectional views of a twelfth embodiment.
Step cross section of first manufacturing method in semiconductor device of present invention
FIGS. 24 to 32 show a second example of the semiconductor device of the present invention.
FIG. 7 is a cross-sectional view illustrating a step in the method for manufacturing Same object throughout all figures
Are indicated by the same reference numerals. However, the oblique lines in the side sectional view are mainly
To describe only the essential insulating film and to show the main part of the invention,
Horizontal and vertical sizes are not necessarily exact dimensions
Is not shown. 1 and 2 show a semiconductor device according to the present invention.
FIG. 1 is a schematic side sectional view of the first embodiment (FIG.
In the long direction (Fig. 2 is the channel width direction), ordinary p-type silicon
Bridge-type epitaxial growth method (SB
E) Short channel formed on SON substrate grown
Includes N-channel MIS field-effect transistor
Shows a part of a semiconductor integrated circuit, where 1 is 10^Fifteencm^-3degree
P-type silicon substrate, 2 is a nitride film with a thickness of about 200 nm
(Si_ThreeN_Four 3) vacancies (spaces) with a depth of about 200 nm,
4 is an oxide film (SiO 2) having a thickness of about 500 nm._Two, Vertical (vertical) direction
5) vertical (vertical) direction
Oriented epitaxial silicon layer, 6 is an acid with a thickness of about 10 nm
Oxide film (SiO_TwoHoles and horizontal (horizontal) epitaxial
7 for horizontal (horizontal) with a thickness of about 100 nm
Epitaxial silicon layer (SON substrate), 8 is 10¹⁷
cm^-3About n-type source / drain regions, 9 is 10²⁰cm^-3degree
N⁺ Type source / drain region, 10 has a thickness of about 200 nm
Oxide film (SiO_Two), 11 is a barrier metal (TiN) of about 20 nm
 ), 12 is a conductive film (W, metal source) about 200 nm thick
13) a gate oxide film with a thickness of about 12 nm
(SiO_Two/ Ta_TwoO_Five ), 14 is about 10 nm barrier metal (TiN
 ), 15 are gate electrodes (Al) with a gate length of about 100 nm, 16
Is a phosphor silicate glass (PSG) film of about 800 nm, and 17 is about 20 nm
Barrier metal (TiN), 18 is a conductive plug (W), 19 is
Barium metal (TiN) of about 50nm, 20 is about 500nm of Al
Wiring, 21 indicates about 50 nm barrier metal (TiN)
You. In FIG. 1, a p-type silicon substrate 1 is selectively
Nitride film (Si_ThreeN _Four 2) and oxide film (SiO_Two) 4
A pair of vertical (vertical) epitaxial silicon layers 5 between
And a pair of vertical (vertical) direction epitaxial
Between the silicon layers 5, a nitride film (Si_ThreeN_Four ) 2 hole just above
Pace) 3, a pair of vertical (vertical) direction epi at both ends
In contact with the axial silicon layer 5,
The axial silicon layer 7 (SON substrate) is provided.
(Horizontal) epitaxial silicon layer 7 (SON)
A gate oxide film (SiO_Two/ Ta_TwoO_Five ) 13
Via a gate electrode with barrier metal (TiN) 14
(Al) 15 is provided, and the gate electrode (Al) 15 is self-aligned.
In combination, the lateral (horizontal) direction epitaxial silicon layer 7
(SON substrate)⁺ And n-type source / drain regions
(9, 8) are provided and n⁺ Type source / drain region 9
In contact with both sides of the gate electrode (Al) 15, the gate oxide film
(SiO_Two/ Ta_TwoO_Five ) 13 barrier metal (Ti
N) 11 conductive film (W, metal source drain region)
Region) 12 and an N-channel MI having a structure in which
An S field effect transistor is formed. (The present invention
Metal source / drain region is a silicon semiconductor
Compound between the impurity region formed on the substrate and the metal film [Sali
Side) and a conventional metal source / drain region
Is different from that of the metal film or alloy film only
Area. ) Therefore, use a normal semiconductor substrate
Vertical epitaxial silicon layer selectively formed
Lateral silicon over vacancies supported by
MIS field-effect transistor
Extremely low cost SON type because it can be formed
A semiconductor integrated circuit can be formed. Also, film thickness control
Easy to form fully depleted SON substrate, heat dissipation
Good, self-heated_I Phenomenon (traffic caused by temperature rise)
(Deterioration of transistor characteristics).
You. Most of the source / drain regions are formed on the SON substrate.
Therefore, the junction capacitance can be reduced. Also impure
The source / drain region with a conductive film provided on the object region
To reduce the resistance of the source / drain
It is also possible to reduce the load resistance. Ta with high dielectric constant
_TwoO_Five Can be used as a gate oxide film.
The thickness of the gate electrode and the SON substrate can be very small.
It is also possible to improve current leakage and reduce gate capacitance.
Sources requiring high-temperature heat treatment to activate impurity regions
Drain region is self-aligned before gate electrode formation
A gate made of a low-resistance low-melting-point metal
Since electrodes can be formed, the resistance of the gate electrode wiring can be reduced.
Noh. Also, the oxide film of the element isolation region, the source / drain
Continuous without step on top surface of conductive film and gate electrode on region
It can be formed on a flat surface
In addition, a thin interlayer insulating film and a wiring body can be formed. this
As a result, using a semiconductor substrate, extremely low cost, easy
High speed, low power, high reliability and high performance depending on the manufacturing process
Having a MIS field-effect transistor combined with
A semiconductor device having a structure can be obtained.

FIG. 3 is a schematic side sectional view of a semiconductor device according to a second embodiment of the present invention. The semiconductor device is formed on a SON substrate grown by a spatial bridge epitaxial growth method (SBE) using a normal p-type silicon substrate. 1 shows a part of a semiconductor integrated circuit including a short-channel N-channel MIS field-effect transistor. Reference numerals 1 to 21 denote the same components as those in FIG. In this figure, instead of providing a pair of vertical epitaxial silicon layers, a vertical epitaxial silicon layer 5 is provided only on one side, and one end of the vertical epitaxial silicon layer 5 An N-channel MIS field-effect transistor having the same structure as that of FIG. 1 except that an (SON substrate) is provided is formed. In this embodiment, the same effects as in the first embodiment can be obtained.

FIG. 4 is a schematic side sectional view of a semiconductor device according to a third embodiment of the present invention, which is formed on a SON substrate grown by a spatial bridge epitaxial growth method (SBE) using a normal p-type silicon substrate. 1 shows a part of a semiconductor integrated circuit including an N-channel MIS field-effect transistor of a short channel, 1 to 9, 16 to 21 are the same as those in FIG. 1, 22 is a gate oxide film (SiO ₂ ), and 23 is Gate electrode (po
lySi / WSi), 24 denotes a sidewall (SiO ₂ ), and 25 denotes an impurity blocking oxide film (SiO ₂ ). In the figure, a pair of vertical epitaxial silicon layers 5 and horizontal epitaxial silicon layers 7 (S
ON substrate), and an LDD using a normal sidewall 24 is provided on the lateral epitaxial silicon layer 7.
N-channel MIS field-effect transistor is formed. In this embodiment, although the resistance of the gate electrode and the source / drain region cannot be reduced and the contact resistance of the conductive plug to the source / drain region slightly increases, the same effect as in the first embodiment can be obtained. N-channel MIS field-effect transistor can be formed.

FIG. 5 is a schematic side sectional view of a semiconductor device according to a fourth embodiment of the present invention. The semiconductor device is formed on a SON substrate grown by a spatial bridge epitaxial growth method (SBE) using a normal p-type silicon substrate. 1 shows a part of a semiconductor integrated circuit including a short-channel N-channel MIS field-effect transistor, wherein 1 to 6, 8, 9, 16 to 25 are the same as those in FIGS. A lateral epitaxial silicon layer (SON substrate), 27 is a second lateral epitaxial silicon layer (SON substrate), and 28 is an oxide film (Si substrate).
O ₂ ) and 29 indicate oxide films (SiO ₂ , etching stopper films). In the figure, a pair of vertical epitaxial silicon layers 5 is provided, and a thick first horizontal epitaxial silicon layer (SON substrate for forming source / drain regions) is provided between the pair of vertical epitaxial silicon layers 5. ) 26 are provided halfway from both sides, and a thin second lateral epitaxial silicon layer (which is a SON substrate for forming a channel region, is formed between the first lateral epitaxial silicon layers 26). Since a gate electrode cannot be formed by self-alignment with the substrate, a part of the source / drain region is diffused).
An LD using a normal sidewall 24 is applied to the first and second lateral epitaxial silicon layers (26, 27) formed by the stepwise spatial bridge epitaxial growth method (SBE).
A D-type N-channel MIS field-effect transistor is formed. In the present embodiment, the contact resistance of the conductive plug to the source / drain region is improved by the thick SON substrate, the resistance of the gate electrode and the source / drain region cannot be reduced, and the junction capacitance slightly increases. A conventional N-channel MIS field-effect transistor capable of obtaining substantially the same effect as described above can be formed.

FIG. 6 is a schematic side sectional view of a fifth embodiment of the semiconductor device according to the present invention. The semiconductor device is formed on a SON substrate grown by a spatial bridge epitaxial growth method (SBE) using a normal p-type silicon substrate. 1 shows a part of a semiconductor integrated circuit including a short-channel N-channel MIS field-effect transistor, wherein 1 to 6, 8, 9, 16 to 27 are the same as those in FIGS. 1, 4 and 5, and 30 is Buried nitride film (Si
₃ N ₄ ). In FIG.
A nitride film (Si ₃ N ₄ ) 30 is buried under the lateral epitaxial silicon layer (SOI substrate for forming the source / drain region) 26 of FIG. Although a SON substrate is used, a part of the source / drain region is diffused because a gate electrode cannot be formed in a self-aligned manner with the SON substrate. On the first and second lateral epitaxial silicon layers (26, 27), an LDD type N-channel MIS field effect transistor utilizing a normal sidewall 24 is formed. Also in the present embodiment, the contact resistance of the conductive plug to the source / drain region is improved by the thick SOI substrate, the resistance of the gate electrode and the source / drain region cannot be reduced, and the junction capacitance slightly increases. A conventional N-channel MIS field-effect transistor capable of obtaining substantially the same effect as described above can be formed.

FIG. 7 is a schematic side sectional view of a sixth embodiment of the semiconductor device according to the present invention, which is an empty space under a SON substrate grown by a spatial bridge epitaxial growth method (SBE) using a normal p-type silicon substrate. An oxide film is buried in the hole, SO
1 shows a part of a semiconductor integrated circuit including a short-channel N-channel MIS field-effect transistor formed on an I-structured SOI substrate, wherein 1, 2 and 4 to 21 are the same as those in FIG. An oxide film (SiO ₂ ) is shown.
In the figure, the holes 3 are filled with a buried oxide film (SiO ₂ ) 31, and a gate electrode (A) having a barrier metal (TiN) 14 is interposed via a gate oxide film (SiO ₂ / Ta ₂ O ₅ ) 13.
l) A lateral epitaxial silicon layer (SOI substrate) 7 is provided only directly below the area where 15 is provided, and a channel region and fine n
⁺ Type and n type source / drain regions (9, 8) are provided, and a conductive film (W, metal source / drain region) 12 having a barrier metal (TiN) 11 is provided in contact with the n ⁺ type source / drain region 9. An N-channel MIS field-effect transistor having substantially the same structure as that of FIG. 1 is formed. In this embodiment, almost the same effect as that of the first embodiment can be obtained, and most of the source / drain regions can be formed of a thick low-resistance conductive film. An N-channel MIS field-effect transistor having an SOI structure can be formed without using an expensive bonded SOI wafer.

FIG. 8 is a schematic side sectional view of a semiconductor device according to a seventh embodiment of the present invention. The semiconductor device according to the seventh embodiment uses a normal p-type silicon substrate and is grown under a SON substrate grown by a spatial bridge epitaxial growth method (SBE). An oxide film is buried in the hole, SO
1 shows a part of a semiconductor integrated circuit including a short-channel N-channel MIS field-effect transistor formed on an I-structured SOI substrate, and includes 1, 2, 4 to 9, and 16 to 2
Reference numerals 5 and 31 denote the same components as those in FIGS. 1, 4 and 7. 4, an SOI N-channel MIS field-effect transistor having the same structure as that of FIG. 4 is formed except that the holes 3 are filled with a buried oxide film (SiO ₂ ) 31. In this embodiment, substantially the same effects as in the third embodiment can be obtained.

FIG. 9 is a schematic side sectional view of an eighth embodiment of the semiconductor device according to the present invention. The semiconductor device according to the eighth embodiment uses an ordinary p-type silicon substrate and is grown under a SON substrate grown by a spatial bridge epitaxial growth method (SBE). An oxide film is buried in the hole, SO
A part of a semiconductor integrated circuit including a short-channel N-channel MIS field-effect transistor formed on an I-structured SOI substrate is shown. Reference numerals 1, 2, 4 to 21 are the same as those in FIG. ^{A +} type impurity region, 33 indicates a lower gate oxide film (SiO ₂ ), and 34 indicates a lower gate electrode (W).
In the figure, p ^{+ is} partially formed on the nitride film (Si ₃ N ₄ ) 2.
A lower gate electrode (W) 34 connected to the vertical epitaxial silicon layer 5 in which the type impurity region is formed, to which the same voltage as that of the source region is applied, and a lower gate oxide film (SiO ₂ ) N-channel MIS having almost the same structure as that of FIG.
A field effect transistor is formed. In the present embodiment, it is possible to completely suppress back channel leak, in addition to obtaining substantially the same effect as the sixth embodiment. In this embodiment, the same voltage as that of the source region is applied to the lower gate electrode, but the lower gate electrode may be modified so as to be connected to the upper gate electrode.

FIG. 10 shows a ninth semiconductor device according to the present invention.
In the schematic side cross-sectional view of the embodiment, an ordinary p-type silicon substrate is used, and an oxide film is buried in holes under the SON substrate grown by the space-bridge epitaxial growth method (SBE).
1 shows a part of a semiconductor integrated circuit including a short-channel N-channel MIS field-effect transistor formed on an SOI substrate having an OI structure, and includes 1, 2, 4, 6 to 21,
31 is the same as in FIGS. 1 and 7, and 35 is a buried oxide film (Si
O ₂ ). 7, the vertical epitaxial silicon layer 5 is removed, an oxide film 35 is buried in place, and the metal source / drain region is substantially the same as that of FIG. A channel MIS field effect transistor is formed.
In this embodiment, substantially the same effect as in the sixth embodiment can be obtained, and the junction capacitance of the source / drain region can be further reduced (substantially zero).

FIGS. 11 and 12 are schematic side sectional views of a semiconductor device according to a tenth embodiment of the present invention (FIG. 11 shows a channel length direction, and FIG. 12 shows a channel width direction), using a normal p-type silicon substrate. Then, a gate electrode having a barrier metal is buried through a gate oxide film in a hole under the SON substrate grown by the spatial bridge epitaxial growth method (SBE) to form an N-channel of a short channel formed on a deformed SOI substrate having an SOI structure. 1 shows a part of a semiconductor integrated circuit including a MIS field-effect transistor of FIG.
4 to 9, 11 to 14, 16 to 21, and 29 are the same as those in FIGS. 1 and 5, 36 is a gate electrode surrounding the channel region (W), 37 is a buried nitride film (Si ₃ N ₄ ), and 52 is An oxide film (SiO ₂ ) is shown. In the figure, most of the vertical epitaxial silicon layer 5 is removed, and instead, a nitride film (Si ₃ N ₄ ) 37 is formed.
And a metal source / drain region (W) 12 having a barrier metal 11 and a channel region and a fine n are formed in the lateral epitaxial silicon layer (deformed SOI substrate) 7.
⁺ -Type and n-type source / drain regions (9, 8) are provided, and a gate electrode 36 having a barrier metal 14 is provided so as to surround a lateral epitaxial silicon layer (modified SOI substrate) 7 via a gate oxide film 13. An N-channel MIS field-effect transistor having the above structure is formed. In this embodiment, all the channels (front channel, back channel, and side channel) can be obtained except that substantially the same effect as in the first embodiment can be obtained.
Can be controlled, and higher speed and higher performance can be achieved.

FIGS. 13 and 14 are schematic side sectional views of an eleventh embodiment of the semiconductor device of the present invention (FIG. 13 is a direction along the lateral epitaxial silicon layer, and FIG. 14 is a direction perpendicular to the lateral epitaxial silicon layer). Then, using an ordinary p-type silicon substrate, buried poly-silicon doped with n ⁺ -type impurities into vacancies under the SON substrate grown by spatial bridge epitaxial growth (SBE) to form an SOI substrate having an SOI structure. 1 shows a part of a semiconductor integrated circuit including a formed bipolar transistor, and includes 1, 2, 4,.
16 to 21 are the same as those in FIG. 1, and 38 is a buried low resistance layer (n ⁺
39 is an n ⁺ -type collector region, 40 is an n ⁻ -type collector region, 41 is a p-type base region, 42 is a p ⁺ -type base contact region, 43 is an n ⁺ -type emitter region, 44 indicates a side wall insulating film (SiO ₂ ), and 45 indicates a collector contact region (W). In the figure, the vertical epitaxial silicon layer 5 is removed, a nitride film (Si ₃ N ₄ ) 37 is buried in place, and the lateral epitaxial silicon layer 7 which is insulated and isolated in an island shape by an insulating film is n ⁺ type. Collector region (region formed by diffusing impurities from poly-Si doped with n ⁺ -type impurities embedded in holes) 39, n ⁻ -type collector region 40, p-type base region 41, p ⁺ -type base contact A region 42 and an n ⁺ -type emitter region 43 are respectively formed, and polySi 38 doped with an n ⁺ -type impurity to be a low-resistance layer is buried in a hole formed immediately below the lateral epitaxial silicon layer 7. In the buried low resistance layer 38, a bipolar transistor having an SOI structure connected to the collector contact region (W) 45 is formed. In this embodiment, the base width and the collector width can be reduced by removing the step of raising the impurity region, which is difficult to control, when forming the epitaxial silicon layer after the conventional formation of the buried low-resistance layer by the impurity. Since the transistor can be formed with good control, a high-performance and high-speed bipolar transistor having an SOI structure can be formed.

FIG. 15 shows a first example of the semiconductor device of the present invention.
2 is a schematic cross-sectional side view of the second embodiment, using a normal p-type silicon substrate, and utilizing a vertical silicon substrate column formed by forming a trench in the p-type silicon substrate, using a spatial bridge-like epitaxial growth method. S grown by (SBE)
N channel M of short channel formed on ON substrate
1 shows a part of a semiconductor integrated circuit including an IS field-effect transistor, and 1 to 4 and 6 to 21 show the same thing as FIG. In the same drawing, a vertical silicon substrate column provided by forming a trench in a p-type silicon substrate without using a vertical epitaxial silicon layer is used, and a part of the side surface of the silicon substrate column is used. An N-channel MIS field-effect transistor having the same structure as that of FIG. 1 except that the lateral epitaxial silicon layer formed in FIG. Also in the present embodiment, the same effects as in the first embodiment can be obtained.
Although not shown, the holes are filled with an insulating film.
It is also possible to transform into an OI structure.

In the above embodiment, an N-channel MIS field-effect transistor has been described. However, the present invention may be applied to a P-channel MIS field-effect transistor (however, it is not necessary to consider the hot carrier effect). Therefore, it is not necessary to provide a low-concentration source / drain region), the present invention can be applied to a C-MOS and a bi-C-MOS, and a semiconductor element other than a transistor can be formed. Although the vertical epitaxial semiconductor layer and the lateral epitaxial semiconductor layer are silicon layers, the present invention is not limited to the silicon layer. The invention holds. The metal source / drain region, gate electrode, barrier metal, conductive plug, gate insulating film, wiring, etc. are not limited to those in the above embodiment, and any material having similar characteristics may be used. Absent.

Next, an embodiment of a first manufacturing method in a semiconductor device according to the present invention will be described with reference to FIGS. 16 to 23 and FIG. 1, and an embodiment of a second manufacturing method will be described with reference to FIGS. This will be described with reference to FIG. However, here, only the manufacturing method relating to the formation of the semiconductor device of the present invention is described, and description of the manufacturing method relating to the formation of various elements (other transistors, resistors, capacitors, etc.) mounted on a general semiconductor integrated circuit is omitted. I do.

An embodiment of the first manufacturing method will be described. FIG. 16 A nitride film (Si ₃ N ₄ ) 2 of about 500 nm is grown on a p-type silicon substrate 1 by chemical vapor deposition. Next, the nitride film (Si ₃ N ₄ ) 2 is anisotropically dry-etched using a normal photolithography technique with a resist (not shown) as a mask layer. Next, the resist (not shown) is removed.
Next, an oxide film (Si
O ₂ ) grow 4; Then the nitride film (Si ₃ N ₄₎ 2 was laminated on the oxide film (SiO ₂₎ 4 chemical mechanical polishing (C hemica
l M echanicl referred to as P ol-ishing after CMP), and is flattened. Next, using a resist (not shown) and an oxide film (SiO ₂ ) 4 as a mask layer, the nitride film (Si ₃ N ₄ ) 2 is selectively anisotropically dry-etched using a normal photolithography technique. , An opening of the p-type silicon substrate 1 is formed. Next, the resist (not shown) is removed. Then exposed p
An epitaxial silicon layer 5 is formed on a silicon substrate 1 in a vertical direction. Next, the epitaxial silicon layer 5 protruding from the flat surface is subjected to chemical mechanical polishing (CM).
P) and flatten. Next, the nitride film (Si ₃ N ₄ ) 2 is anisotropically dry-etched by about 100 nm. (Since the etching thickness of the nitride film determines the thickness of the lateral (horizontal) epitaxial silicon layer, the thinner the etching thickness of the nitride film, the more accurate the lateral (horizontal) epitaxial silicon layer of the thin film becomes. Next, TiN 46 of about 10 nm is grown by sputtering. Next, the TiN 46 is anisotropically dry-etched to leave the TiN 46 only on the side walls of the vertical epitaxial silicon layer 5. Next, the remaining nitride film (Si ₃ N ₄ ) 2 is isotropically dry-etched about 200 nm,
A part of the side surface of the vertical epitaxial silicon layer 5 under the TiN 31 is exposed. Next, a thermal oxide film (Si) of about 10 nm is formed on the upper and side surfaces of the exposed vertical epitaxial silicon layer 5.
O ₂ ) grow. FIG. 19 Next, the TiN 46 remaining on the side wall is subjected to isotropic dry etching. Next, a lateral (horizontal) direction epitaxial silicon layer 7 is grown on the exposed side surface of the vertical epitaxial silicon layer 5 so as to bridge the space. In this way, an epitaxial silicon layer 7 (which becomes an SON substrate) having an extremely small number of crystal defects similar to a silicon wafer without being affected by the underlayer is formed on the holes (spaces) 3. Next, an oxide film (SiO ₂ ) of about 10 nm is grown for ion implantation. Next, boron for controlling the threshold voltage is ion-implanted into the SON substrate 7. Next, the oxide film for ion implantation is chemically mechanically polished (C
MP) and flatten. FIG. 20 Next, an oxide film (SiO ₂ ) of about 200 nm is formed by chemical vapor deposition.
Grow 10 Next, the oxide film (SiO ₂ ) 10 is anisotropically dry-etched using a resist (not shown) as a mask layer by using a usual photolithography technique to selectively expose the SON substrate 7. Next, the resist (not shown) is removed. Next, an oxide film (SiO
₂ ) Grow. Next, phosphorus is ion-implanted using the oxide film 10 as a mask layer. Next, N ₂ annealing at about 800 ° C. is performed to diffuse in the lateral direction, thereby forming an n-type source / drain region 8. Next, arsenic is ion-implanted. Then
By performing N ₂ annealing at about 800 ° C., an n ⁺ -type source / drain region 9 including a slight lateral diffusion is formed. (The lateral diffusion may be controlled by the difference between the diffusion coefficients of phosphorus and arsenic only by annealing at about 800 ° C. without performing annealing twice.) Then, an oxide film for ion implantation (SiO ₂ ) Is anisotropically dry-etched. FIG. 21 Then, about 20 nm of TiN 11 is grown by sputtering.
Next, a tungsten film (W) 12 is grown by chemical vapor deposition. Next, chemical mechanical polishing (CMP) is performed, and TiN 11 and a tungsten film (W) 12 are buried in the opening, and n ⁺
A metal source / drain region (W) 12 having a barrier metal (TiN) 11 is formed on the mold source / drain region 9. Next, using a normal photolithography technique, a metal source drain region (W) 12 having a resist (not shown) and a barrier metal (TiN) 11 is used as a mask layer.
Oxide film 10 is selectively anisotropically dry-etched to form an opening for forming a gate electrode. Next, the resist (not shown) is removed. Next, a gate oxide film 13 of about 12 nm
(SiO ₂ / Ta ₂ O ₅ ) is grown. Next, a barrier metal (TiN) 14 of about 10 nm and Al 15 serving as a gate electrode are grown by continuous sputtering. Next, chemical mechanical polishing (CMP)
To form a buried gate electrode structure comprising a gate oxide film 13 (SiO ₂ / Ta ₂ O ₅ ), a barrier metal (TiN) 14 and a gate electrode (Al) 15. In this case, unnecessary portions of Al15 and barrier metal (TiN) 1
4 and the gate oxide film (SiO ₂ / Ta ₂ O ₅ ) 13 are also removed. Next, a phosphor silicate glass (PSG) film 16 of about 800 nm is grown by chemical vapor deposition. Next, the PSG film 16 is anisotropically dry-etched using a resist (not shown) as a mask layer, and a contact hole is selectively formed using a normal photolithography technique. Next, the resist (not shown) is removed. Next, TiN 17 serving as a barrier metal is grown by sputtering. Next, a tungsten film (W) 18 is grown by chemical vapor deposition. Then, the conductive plug (W) 18 is formed by filling the contact hole by chemical mechanical polishing (CMP). Fig. 1 Next, a barrier metal of about 50 nm is formed by sputtering.
TiN 19, Al for wiring of about 500nm (including several percent Cu)
TiN 21 to be a barrier metal of about 20 and 50 nm is sequentially grown. Then, using normal photolithography technology,
Using a resist (not shown) as a mask layer, barrier metal (TiN) 21, Al (containing several% of Cu) 20 and barrier metal (TiN) 19 are successively anisotropically dry-etched to form an Al wiring 20.
To form Then remove the resist (not shown)
An N-channel MIS field-effect transistor using an epitaxial silicon layer having a space bridge structure as an SON substrate is completed.

An embodiment of the second manufacturing method will be described.
You. FIG. About 200 nm by chemical vapor deposition on p-type silicon substrate 1
Degree nitride film (Si_ThreeN_Four) Oxide film (SiO_Two) 29,
200nm nitride film (Si_ThreeN_Four) 47, 10nm oxide film (Si
O_Two) Nitride film (Si_ThreeN_Four) 49, 10nm acid
Oxide film (SiO_Two) 50-200nm nitride film (Si_ThreeN_Four) 51
grow up. Then use normal photolithography technology.
Using a resist (not shown) as a mask layer and a nitride film
(Si_ThreeN_Four) 51, oxide film (SiO_Two) 50, nitride film (Si_ThreeN_Four) 49, acid
Oxide film (SiO_Two) 48, nitride film (Si_ThreeN_Four) 47 is sequentially anisotropic dry
Etch. Next, the resist (not shown) is removed.
You. Next, an oxide film of about 600 nm is formed by chemical vapor deposition.
(SiO_Two) Grow 4. Next, nitride film (Si_ThreeN_Four) 51
Layered oxide film (SiO_Two4) Chemical mechanical polishing (CMP)
And flatten. FIG. Next, using normal photolithography technology,
The nitride film (Si) is used as a mask (not shown) as a mask layer._ThreeN_Four) Five
1. Oxide film (SiO_Two) 50, nitride film (Si_ThreeN_Four) 49, Oxide film (SiO
_Two) 48, nitride film (Si_ThreeN_Four) 47, Oxide film (SiO_Two29) Nitride film
(Si_ThreeN_Four2) is sequentially anisotropically dry-etched. Then
The resist (not shown) is removed. Then exposed p-type
Epitaxial on the silicon substrate 1
A silicon layer 5 is formed. Next, chemical mechanical polishing (CM
P) and flatten. FIG. Next, nitride film (Si_ThreeN_Four) Anisotropic dry etching of 51
You. Next, an oxide film (SiO_Two) 50 anisotropic dry etching
I do. Then thermally oxidized and exposed vertical epitaxial
An oxide film (SiO 2) of about 10 nm is formed on the silicon layer 5._TwoGrow 52)
You. FIG. Next, nitride film (Si_ThreeN_Four) Anisotropic dry etching of 49
You. Next, an oxide film (SiO_Two) 48 is anisotropic dry etching
I do. Next, about 10 nm of TiN 46 is grown by sputtering
I do. Next, anisotropic dry etching of TiN 46
TiN 46 remains only on the side wall of the epitaxial silicon layer 5
You. Next, a nitride film (Si_ThreeN_Four) 47 isotropic dry etchin
The vertical epitaxial silicon layer 5 under TiN 46
Exposing a part of the side. Next, an oxide film (SiO_Two) 29 isotropic
Dry etching. Then thermally oxidized and exposed vertical
Oxide film of about 10 nm on the direction epitaxial silicon layer 5
(SiO_Two6.) Grow 6. FIG. Next, isotropic dry etching of TiN 46 left on the side wall
I do. Then exposed vertical epitaxial silicon layer
5 on the side (horizontal) so as to bridge the space
The epitaxial silicon layer 7 is grown. So below
Unaffected by ground, crystal defects are as high as silicon wafers
Less epitaxial silicon layer 7
Are formed on the holes (spaces) 3. Then hot acid
Oxide film (SiO 2) of about 10 nm for ion implantation._Two , Illustrated
G) to grow. Then, boron for controlling the threshold voltage is replaced with SO.
Ions are implanted into the N substrate 7. FIG. Next, using normal photolithography technology,
(Not shown) and the epitaxial silicon layer 7
Oxide film (SiO_Two4) Anisotropic dry etching
(The nitride film 2 serves as an etching stopper film)
Openings for gate electrode formation selectively on both sides of SON substrate 7
Section is provided. (At this time, an oxide film for ion implantation (SiO_Two)
Pitching is removed. ) Then resist (not shown)
Remove. Next, a gate oxide film 13 (SiO_Two/ Ta
_TwoO_Five Grow). Next, a barrier metal (Ti
N) 14 and a tungsten film (W) 36 serving as a gate electrode
It grows by continuous sputtering. Then chemical mechanical polishing
(CMP) embedded in the opening for gate electrode formation
Only, the gate oxide film 13 (SiO_Two/ Ta_TwoO_Five ), Barrier metal
Epitaxy consisting of (TiN) 14 and gate electrode (W) 36
Char silicon layer 7 (silicon base serving as channel region)
The gate electrode structure of the surrounding type is formed. Unnecessary
Gate electrode (W) 36, barrier metal (TiN) 14,
Oxide film (SiO_Two/ Ta _TwoO_Five 13) and oxide film (SiO_Two6)
Removed. FIG. Next, the exposed epitaxial silicon layer 5 is anisotropically doped.
Light etching is performed to form an opening. (In that case, p-type
There is no problem even if the silicon substrate 1 is slightly etched.
No. Then, phosphorus is obliquely ion-implanted. Then about 800 ° C
Degree N_TwoSlightly diffused laterally by adding annealing
Then, an n-type source / drain region 8 is formed. Then arsenic
Is obliquely ion-implanted. Then N at about 800 ℃_TwoAnnealing
To add n with some lateral diffusion⁺ Type
The source drain region 9 is formed. (Do two annealings
Without annealing, only annealing at about 800 ° C.
The lateral diffusion may be controlled by the difference in diffusion coefficient.
No. ) Next, nitride film (Si_ThreeN_Four) 37
grow up. Next, the chemical mechanical polishing (CMP)
Nitride film (Si_ThreeN_Four) 37 is buried and flattened. Then buried
Embedded nitride film (Si_ThreeN_Four) 37 is about 400nm anisotropic dry
Etching is performed to form a new opening. FIG. Then, about 20 nm of TiN 11 is grown by sputtering.
Next, a tungsten film (W) 12 is formed by chemical vapor deposition.
grow up. Next, the chemical mechanical polishing (CMP)
Embedded with TiN 11 and tungsten film (W), and nitride film
(Si_ThreeN_Four) 37 on n⁺ Contacts the source / drain region 9
Metal source drain with barrier metal (TiN) 11
An area (W) 12 is formed. FIG. Next, by chemical vapor deposition, a phosphor silicate glass of about 800 nm
A (PSG) film 16 is grown. Next, normal photolithography
Using a fee technology, a resist (not shown) is used as a mask layer
Select the PSG film 16 by anisotropic dry etching
A contact hole is formed. Then resist (Figure
(Not shown). Next, the barrier
Grow TiN 17 which will become a barrel. Then by chemical vapor deposition
Then, a tungsten film (W) 18 is grown. Then chemical
Embedded in contact holes by mechanical polishing (CMP)
Then, a conductive plug (W) 18 is formed. FIG. Next, it becomes a barrier metal of about 50 nm by sputtering.
TiN 19, Al for wiring of about 500nm (including several percent Cu)
Growth of TiN 21 as barrier metal of about 20 and 50 nm sequentially
You. Then, using normal photolithography technology,
Barrier metal using resist (not shown) as a mask layer
(TiN) 21, Al (including several% of Cu) 20 and barrier metal
(TiN) 19 is successively anisotropically dry-etched to form Al wiring 20
To form Then remove the resist (not shown)
Epitaxial silicon layer formed in a spatial bridge-like structure
Gate electrode surrounding silicon substrate)
N-channel MIS field-effect transistor having structure
To complete.

[0022]

As described above, according to the present invention, an SOI substrate is formed by a special method which is technically difficult (SIMO).
X, an SOI substrate formed by bonding semiconductor substrates, and a recrystallized SOI substrate formed by laser irradiation) without using a vertical (vertical) epitaxial semiconductor layer selectively formed on a semiconductor substrate. A lateral epitaxial semiconductor layer having a very small number of crystal defects formed in a spatial bridge structure on a part of the side surface of the vertical epitaxial semiconductor layer is formed on a semiconductor substrate (SON substrate or S substrate).
OI substrate), and a semiconductor element (MIS)
Field effect transistors or bipolar transistors) are easily formed. Therefore, when the MIS field-effect transistor is formed, the resistance of the source / drain region is reduced by forming the metal source / drain region, the junction capacitance is reduced, the contact resistance is reduced, and the gate electrode wiring is formed by using a low-resistance metal gate electrode. Improvement of minute current leakage between gate electrode and SOI substrate (including SON substrate), reduction of gate capacitance, and easy control of film thickness by using low resistance, high dielectric constant Ta ₂ O ₅ gate oxide film It is possible to remove a depletion layer capacitance by using a depleted SOI substrate and to reduce a threshold voltage by improving a subthreshold characteristic. In addition, since gate electrodes can be formed above and below the SOI substrate (including the case where the gate electrode is formed so as to surround the SOI substrate), not only can back channel leakage (including side channel leakage) during off-time be completely prevented, but also In the ON state, as much drive current as possible can flow through not only the front channel but also the back channel (including the side channel). Also, when forming a bipolar transistor, it is not necessary to consider the rise of impurities in the buried low-resistance layer during epitaxial growth, so that vertical miniaturization and control are easy, and high speed and high performance can be achieved. Become. That is, a semiconductor device having an SOI structure (including a SON structure) that can form a high-speed, low-power, highly reliable, and high-performance semiconductor integrated circuit by using a semiconductor substrate, at an extremely low cost, and by an easy manufacturing process. Can be obtained.

[Brief description of the drawings]

FIG. 1 is a schematic side sectional view of a first embodiment of a semiconductor device of the present invention (in a channel length direction).

FIG. 2 is a schematic side sectional view of a first embodiment of the semiconductor device of the present invention (in a channel width direction).

FIG. 3 is a schematic side sectional view of a second embodiment of the semiconductor device of the present invention.

FIG. 4 is a schematic side sectional view of a third embodiment of the semiconductor device according to the present invention;

FIG. 5 is a schematic side sectional view of a fourth embodiment of the semiconductor device of the present invention.

FIG. 6 is a schematic side sectional view of a fifth embodiment of the semiconductor device of the present invention.

FIG. 7 is a schematic side sectional view of a sixth embodiment of the semiconductor device according to the present invention;

FIG. 8 is a schematic side sectional view of a semiconductor device according to a seventh embodiment of the present invention;

FIG. 9 is a schematic side sectional view of an eighth embodiment of the semiconductor device according to the present invention;

FIG. 10 is a schematic side sectional view of a ninth embodiment of the semiconductor device according to the present invention;

FIG. 11 is a schematic side sectional view of a tenth embodiment of the semiconductor device according to the present invention (in a channel length direction).

FIG. 12 is a schematic side sectional view of a tenth embodiment of the semiconductor device according to the present invention (in a channel width direction).

FIG. 13 is a schematic side sectional view of an eleventh embodiment of the semiconductor device according to the present invention (in a direction along a lateral epitaxial silicon layer).

FIG. 14 is a schematic side sectional view of an eleventh embodiment of the semiconductor device according to the present invention (in a direction perpendicular to the lateral epitaxial silicon layer).

FIG. 15 is a schematic side sectional view of a twelfth embodiment of the semiconductor device according to the present invention;

FIG. 16 is a process cross-sectional view of the first manufacturing method in the semiconductor device of the present invention.

FIG. 17 is a process cross-sectional view of the first manufacturing method in the semiconductor device of the present invention.

FIG. 18 is a process cross-sectional view of the first manufacturing method in the semiconductor device of the present invention.

FIG. 19 is a process cross-sectional view of the first manufacturing method in the semiconductor device of the present invention.

FIG. 20 is a process cross-sectional view of the first manufacturing method in the semiconductor device of the present invention.

FIG. 21 is a process cross-sectional view of the first manufacturing method in the semiconductor device of the present invention.

FIG. 22 is a process cross-sectional view of the first manufacturing method in the semiconductor device of the present invention.

FIG. 23 is a process cross-sectional view of the first manufacturing method in the semiconductor device of the present invention.

FIG. 24 is a process cross-sectional view of the second manufacturing method in the semiconductor device of the present invention.

FIG. 25 is a process cross-sectional view of the second manufacturing method in the semiconductor device of the present invention.

FIG. 26 is a process cross-sectional view of the second manufacturing method in the semiconductor device of the present invention.

FIG. 27 is a process cross-sectional view of the second manufacturing method in the semiconductor device of the present invention.

FIG. 28 is a process sectional view of the second manufacturing method in the semiconductor device of the present invention;

FIG. 29 is a process cross-sectional view of the second manufacturing method in the semiconductor device of the present invention.

FIG. 30 is a process cross-sectional view of the second manufacturing method in the semiconductor device of the present invention.

FIG. 31 is a process cross-sectional view of the second manufacturing method in the semiconductor device of the present invention.

FIG. 32 is a process sectional view of the second manufacturing method in the semiconductor device according to the present invention;

FIG. 33 is a schematic side sectional view of a conventional semiconductor device.

[Explanation of symbols]

Reference Signs List 1 p-type silicon (Si) substrate 2 nitride film (Si ₃ N ₄ ) 3 vacancy (space) 4 oxide film (SiO ₂ , for forming vertical epitaxial silicon layer) 5 vertical epitaxial silicon layer 6 oxide film (SiO _2. Voids and lateral epitaxial silicon layer formation 7. Lateral epitaxial silicon layer (SOI or SON substrate) 8 n-type source / drain region 9 n ⁺ type source / drain region 10 oxide film (SiO ₂ ) 11 barrier metal (TiN) ) 12 conductive (W, metal source drain regions) 13 a gate oxide film _{(SiO 2 / Ta 2 O 5} ) 14 a barrier metal (TiN) 15 gate electrode (Al) 16 phosphosilicate glass (PSG) film 17 a barrier metal (TiN ) 18 conductive plug (W) 19 a barrier metal (TiN) 20 Al wiring 21 a barrier metal (TiN) 22 gate oxide film (SiO ₂₎ 23 gate electrode (polySi / WSi) 24 side wall (SiO ₂₎ 25 impure Block oxide film (SiO ₂₎ 26 first lateral epitaxial silicon layer (SOI or SON substrate) 27 second transverse epitaxial silicon layer (SOI or SON substrate) 28 oxide film (SiO ₂₎ 29 oxide film (SiO ₂ ) 30 buried nitride film (Si ₃ N ₄ ) 31 buried oxide film (SiO ₂ ) 32 p ⁺ -type impurity region 33 lower gate oxide film (SiO ₂ ) 34 lower gate electrode (W) 35 buried oxide film (SiO ₂ ) 36 Channel region surrounding gate electrode (W) 37 Buried nitride film (Si ₃ N ₄ ) 38 Buried low resistance layer (n ⁺ type impurity doped
polySi) 39 n ⁺ type collector region 40 n ⁻ type collector region 41 p type base region 42 p ⁺ type base contact region 43 n ⁺ type emitter region 44 sidewall insulating film (SiO ₂ ) 45 collector contact region 46 antioxidant film (TiN) ) 47 nitride film (Si ₃ N ₄ ) 48 oxide film (SiO ₂ ) 49 nitride film (Si ₃ N ₄ ) 50 oxide film (SiO ₂ ) 51 nitride film (Si ₃ N ₄ ) 52 oxide film (SiO ₂ )

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (Reference) H01L 29/417 H01L 29/78 626C 29/732 29/72 P 29/786 F term (Reference) 4M104 AA01 AA09 BB01 BB02 BB18 BB30 CC01 CC05 DD02 DD04 DD08 DD19 DD37 DD43 DD66 DD71 DD75 DD91 EE03 EE09 EE12 EE16 FF02 FF04 FF13 FF14 FF22 GG06 GG08 GG09 HH15 HH16 5F003 AZ03 BA12 BA27 BB06 A08 EA06 DD08 A08 DD10 FF01 FF02 FF09 FF29 FF35 GG02 GG12 GG25 GG32 GG41 HJ01 HJ13 HK01 HK04 HK21 HK33 HK34 HK42 HL01 HL04 HL14 HL23 HL24 HL27 HM15 BC02 NN02 NN04 NN25 NN35 QQ13 AB01 BCBA A01BAB BD05 BD12 BE03 BE09 BE11 BF10 BF11 BF15 BF43 BF45 BF59 BF60 BG05 BG30 BG45 BH08 BH15 BH25 BH26 BH39 BH45 BJ10 BJ11 BJ17 BJ27 B K02 BK05 BK07 BK09 BK13 BK14 BK18 BK23 BK26 BK29 CA02 CA03 CB01 CB04 CB10 CC05 CE07 CE08 CF07

Claims (4)

[Claims] A semiconductor substrate, a vertical (vertical) epitaxial semiconductor layer selectively provided on the semiconductor substrate, and an insulating film selectively provided on the semiconductor substrate.
A lateral (horizontal) epitaxial semiconductor layer provided on a part of a side surface of the vertical (vertical) epitaxial semiconductor layer via a hole (space) on the insulating film; and at least the lateral (horizontal) epitaxial semiconductor And a semiconductor element provided in the layer. 2. The semiconductor device according to claim 1, wherein said holes are filled with a gate electrode via an insulating film or a gate insulating film. 3. The semiconductor device according to claim 1, wherein said vertical (vertical) direction epitaxial semiconductor layer comprises a part of said semiconductor substrate. 4. An insulating film formed on a semiconductor substrate is partially opened, and a vertical (vertical) direction epitaxial semiconductor layer is selectively formed on the semiconductor substrate. A part of a side surface of the epitaxial semiconductor layer is exposed, a lateral (horizontal) epitaxial semiconductor layer is formed on a space above the insulating film, and a semiconductor element is formed on the lateral (horizontal) epitaxial semiconductor layer. Manufacturing method of a semiconductor device.