JP2004319808A - Mis field effect transistor and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a vertical type MIS field effect transistor with a short channel. <P>SOLUTION: A trench element isolation region 2 is provided on a p-type silicon substrate 1, and a p-type channel stopper region 3 is provided on the bottom of the element isolation region 2. A column-structured p-type epitaxial semiconductor layer 4 is selectively provided on the silicon substrate 1. Drain regions 7, 6 are provided above the column structured semiconductor layer 4, and a source region 5 filling the bottom of the column-type structured semiconductor layer 4 is provided on the upper surface of the p-type silicon substrate 1. A gate electrode 12 having a barrier metal 11 is provided on the side surface of the semiconductor layer 4 through a gate oxide film 10, and a conductive film 9 is provided so as to be contacted with the upper part of drain regions 7 above the semiconductor layer 4. The vertical type MIS field effect transistor has a quasi SOI (silicon on insulator) structure provided with a channel enclose type low resistance metal gate electrode. AlCu wirings 17 having the upper and lower barrier metals in up-and-down are connected respectively to the MIS FET through a conductive plug 15 having the barrier metal 14. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
[Industrial applications]
The present invention relates to SOI ( S ilicon O n I The present invention relates to a semiconductor integrated circuit having an nsulator structure, in particular, a low-cost pseudo SOI substrate is formed on a semiconductor substrate (bulk wafer) by an easy manufacturing process, and the pseudo SOI substrate is provided with a high speed, low power, high performance, and high performance. The present invention relates to forming a semiconductor integrated circuit including a reliable and highly integrated short channel MIS field effect transistor.
Conventionally, as for a semiconductor integrated circuit having an SOI structure, a semiconductor integrated circuit using a so-called bonded SOI wafer, in which a semiconductor substrate having a uniform single crystal is bonded to another semiconductor substrate via an oxide film, is being put to practical use. However, the yield is low because two semiconductor substrates are used and an extremely thin SOI substrate must be formed to completely deplete the semiconductor substrate, and a commercially available bonded SOI wafer is extremely expensive. There are drawbacks.
In addition, a so-called SIMOX method (in which an oxide film is formed inside a bulk wafer by high-temperature heat treatment by implanting oxygen ions into a normal semiconductor substrate (bulk wafer) ( S -Eparation by IM planted OX ygen) has drawbacks such as the purchase of expensive high-dose ion implantation machines, high costs due to long manufacturing processes, and instability of characteristics when using large-diameter wafers.
At present, ignoring the problem of high cost, it is practically used only for portable devices requiring extremely high speed and low power consumption and for system LSIs mixed with analog / digital, and all of them are customary using SOI wafers. LDD using sidewall ( L rightly D oped D A short channel MIS field-effect transistor having a (rain) structure is formed on an SOI substrate whose periphery is separated by an insulating film. By reducing junction capacitance, depletion layer capacitance, threshold voltage, etc., high speed and low power consumption are achieved. On the other hand, it is high speed despite the miniaturization because the contact resistance of the source / drain region is increased because it is formed on a thin film SOI substrate and the resistance of each element is not reduced. There is a drawback that the conversion has not been achieved. In addition, when a voltage different from the voltage applied to the gate electrode is applied to a conductor (semiconductor substrate or lower wiring) under the SOI substrate, a small back channel leak generated at the bottom of the SOI substrate cannot be controlled. There was also a disadvantage that the property was not achieved. In addition, since the channel length that determines various characteristics of the MIS field-effect transistor depends on the control of the gate length by the photolithography technique, it is extremely difficult to control the manufacturing variation in a large-diameter wafer, and the characteristics of the MIS field-effect transistor may be reduced. The disadvantage that it is becoming difficult to control it to an allowable range has also become significant.
Therefore, an SOI structure can be formed by a low-cost and easy process that enables the manufacture of a semiconductor integrated circuit for high-speed large-capacity communication or a portable information terminal, and further high integration, high speed, low power, and high reliability. There is a need for a means that can form a short-channel MIS field-effect transistor that can achieve high performance.
[0002]
[Prior art]
FIG. 33 is a schematic side sectional view of a conventional semiconductor device. FIG. 33 shows a part of a semiconductor integrated circuit including an N-channel MIS field-effect transistor having an SOI structure formed using a bonded SOI wafer. Type silicon substrate, 52 is a bonding oxide film, 53 is a p-type SOI substrate, 54 is a trench and a buried oxide film for forming an isolation region, 55 is an n-type source / drain region, and 56 is n ⁺ Type source / drain region 57 is a gate oxide film (SiO 2 ₂ ), 58 is a gate electrode (WSi / PolySi), 59 is a base oxide film, 60 is a sidewall (SiO ₂ ), 61 are impurity blocking oxide films, 62 is a BPSG film, 63 is a barrier metal (Ti / TiN), 64 is a plug (W), 65 is a barrier metal (Ti / TiN), 66 is an AlCu wiring, and 67 is a barrier. Metal (Ti / TiN) is shown.
In the figure, a thin p-type SOI substrate 53 bonded to a p-type silicon substrate 51 via an oxide film 52 and insulated in an island shape by a trench for forming an element isolation region and a buried oxide film 54. The MIS field-effect transistor having an N-channel LDD structure is formed on the p-type SOI substrate 53.
Therefore, the junction capacitance can be reduced by forming a source / drain region surrounded by an insulating film, the depletion layer capacitance can be reduced by completely depleting the SOI substrate, and the threshold voltage can be reduced by improving the subthreshold characteristics. As compared with a semiconductor integrated circuit including MIS field-effect transistors formed on a normal bulk wafer by removing a contact region to the semiconductor device, high speed, low power, and high integration can be achieved.
However, since it is formed on a thin-film SOI substrate, a high speed has not been achieved despite miniaturization because the contact resistance of the source / drain region increases and the resistance of each element is not reduced. There was a disadvantage.
Further, as a means for improving the deterioration of the transmission conductance over the lifetime due to the hot carrier effect caused by the strong electric field near the drain, a short channel MIS field effect transistor is formed by forming a conventional LDD structure. For this reason, a low-concentration region is also formed in an unnecessary source region, and the resistance of the source region cannot be reduced, so that there is a disadvantage that further higher speed and higher integration cannot be achieved.
In addition, when a voltage different from the voltage applied to the gate electrode is applied to a conductor (semiconductor substrate or lower wiring) under the SOI substrate, a small back channel leak generated at the bottom of the SOI substrate cannot be prevented. There was also a disadvantage that the property was not achieved.
In addition, since the channel length that determines various characteristics of the MIS field-effect transistor depends on the control of the gate length by the photolithography technique, it is extremely difficult to control the manufacturing variation in a large-diameter wafer, and the characteristics of the MIS field-effect transistor may be reduced. There is also a disadvantage that it is difficult to achieve high speed and high performance because it is difficult to control to an allowable range.
Furthermore, in order to form such an SOI structure, a commercially available bonded SOI wafer must be purchased, and even if the cost reduction technology of a wafer maker is relied on, it is three times as large as a bulk wafer in a mass production stage. There is also a disadvantage that the cost is extremely high, about five times.
Further, as another means for forming an SOI structure, a so-called SIMOX method of forming an SOI substrate by using a bulk wafer, implanting oxygen ions and forming an oxide film inside the bulk wafer by high-temperature heat treatment, The problem of having to purchase very expensive high dose ion implantation machines and the cost of long manufacturing steps to implant high doses of oxygen, or the large size of 10 to 12 inches. There are disadvantages such as instability of characteristics due to repair of crystal defects due to oxygen ion implantation in the use of a large diameter wafer.
[0003]
[Problems to be solved by the invention]
The problem to be solved by the present invention is that, as shown in the prior art, a fully depleted thin-film SOI substrate is required to obtain a MIS field-effect transistor with improved high-speed performance. In order to form the source / drain region on the SOI substrate, the SOI substrate forming the source / drain region is inevitably over-etched when the interlayer insulating film for forming the conductive plug is etched. Although the contact can be removed, the contact resistance of the source / drain region increases, and the capacitance can be reduced but the resistance of the thin source / drain region and the resistance of the gate electrode cannot be reduced. High speed could not be achieved, applied to gate electrode under C-MOS or under SOI substrate When there is a lower wiring to which a voltage different from the voltage is applied, high reliability cannot be obtained because back channel leak cannot be prevented, and the channel length that determines various characteristics of the MIS field-effect transistor is determined by photolithography technology. , It is difficult to obtain a MIS field-effect transistor having stable characteristics due to poor controllability of manufacturing variations in a large-diameter wafer, and it is difficult to achieve high speed and high performance. That is, even if a bonded SOI wafer is used to form an SOI structure or an SOI substrate is formed by a SIMOX method, the yield is poor in the current technology and the cost is considerably increased. Can be used only for high value-added special-purpose products, and can be applied to inexpensive general-purpose products It is that it was poor in technology.
[0004]
[Means for Solving the Problems]
The object is to provide a semiconductor substrate selectively having a convex structure (a columnar structure or a cylindrical structure) and a semiconductor substrate provided on a side surface of the convex structure with a gate insulating film interposed therebetween. A drain region (or a source region) provided above the convex structure of the semiconductor substrate, and at least a distance from the drain region (or the source region). A source region (or a drain region) provided at the bottom of the convex structure portion of the semiconductor substrate, and a wiring body provided at the drain region, the source region, and the gate electrode. The problem is solved by the MIS field effect transistor of the present invention.
[0005]
[Operation]
That is, in the MIS field-effect transistor of the present invention, a trench for forming an element isolation region in which an insulating film is embedded in a semiconductor substrate is selectively provided, and a channel stopper region is formed at the bottom of the trench for forming the element isolation region. Is provided. A semiconductor layer having a fully depleted convex structure (a columnar structure or a cylindrical structure [a hollow columnar structure] on the semiconductor substrate) or a trench in the semiconductor substrate is selectively selectively depleted on the insulated semiconductor substrate. Is formed, a part of a semiconductor substrate formed in a columnar structure or a cylindrical structure is provided, and high-concentration and low-concentration drain regions are provided on the semiconductor layer having the convex structure. A high-concentration source region is provided on the upper surface, which is diffused in the horizontal direction (lateral direction) and fills the bottom of the semiconductor layer having a convex structure, and a side surface of the semiconductor layer having the convex structure is provided with a barrier via a gate insulating film. A gate electrode having metal is provided, and a conductive film wider than the high-concentration drain region is provided in contact with the high-concentration drain region provided over the semiconductor layer having the convex structure. Barrier vertical MIS field effect transistor of the structure being connected to a wiring having a barrier metal vertically via a conductive plug having a metal is formed. (Here, in order to form a pseudo SOI structure, the semiconductor layer having a convex structure is formed to have an extremely fine width (about 50 nm because it is a fully depleted semiconductor layer). Alternatively, the semiconductor layer having a convex structure (strictly speaking, a channel region) and a semiconductor substrate are formed so as not to be in contact with each other by a high-concentration source region which is completely filled by the diffusion of impurities from inside and outside and is integrated. Is essential.)
Therefore, a drain region, a channel region, and a source region can be formed in a semiconductor layer having a fully depleted convex structure selectively formed using a normal semiconductor substrate without using a semiconductor substrate having a bonded SOI structure. Since the semiconductor layer having a convex structure electrically isolated from the semiconductor substrate by the source region can be formed, a pseudo SOI structure can be formed, and the junction capacitance of the drain region can be reduced (substantially zero). it can. (The junction capacitance of the source region when the same voltage as that of the semiconductor substrate is applied is also zero, and the junction capacitance of the source region when a different voltage is applied cannot be reduced. (Since there is no silicon substrate, it is called a pseudo SOI structure instead of a so-called SOI structure.)
In addition, since a fully depleted pseudo SOI substrate can be easily formed, the capacitance of the depletion layer can be reduced and the threshold voltage can be reduced by improving the subthreshold characteristics.
Further, the channel length that determines various characteristics of the MIS field-effect transistor can be determined by the growth thickness of the epitaxial semiconductor layer with good controllability and the diffusion of impurities by heat treatment without depending on the control of the gate length by the photolithography technique. Thus, an MIS field-effect transistor having stable characteristics can be obtained even for a large-diameter wafer.
Further, since the channel region can be completely surrounded by the gate electrode, a high-performance and highly reliable MIS field-effect transistor having extremely excellent leakage characteristics can be obtained.
In addition, a low-concentration region formed as a means for improving the deterioration of transmission conductance over the lifetime due to a hot carrier effect caused by a strong electric field near the drain region can be formed only in the drain region and not in the source region. In addition, the resistance of the source region can be reduced, and the channel length can be reduced without deteriorating the breakdown voltage.
Ta having a high dielectric constant ₂ O ₅ Can be used as a gate insulating film, so that the thickness of the gate insulating film can be increased, a minute current leak between the half layers forming the gate electrode and the channel can be improved, and the gate capacitance can be reduced.
In addition, since the source / drain regions requiring high-temperature heat treatment to activate the impurity regions can be formed in a self-aligned manner before forming the gate electrode, a gate made of a low-resistance low-melting-point metal can be used without using a polycrystalline silicon film. Since the electrodes can be formed, the resistance of the gate electrode wiring can be reduced and the capacitance of the depletion layer at the gate electrode can be removed, so that the power consumption can be reduced by reducing the threshold voltage.
In addition, each element (low-concentration and high-concentration drain regions, high-concentration source regions, a gate oxide film, a gate electrode, and a barrier metal) can be formed by self-alignment with the semiconductor layer having a convex structure.
That is, high speed, low power, high reliability, high performance, and high integration can be achieved by using a semiconductor layer having a convex structure formed by an easy process on a semiconductor substrate without using a semiconductor substrate having an expensive SOI structure. And a vertical MIS field-effect transistor having a pseudo SOI structure and having a channel surrounding low-resistance metal gate electrode.
[0006]
【Example】
Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments.
FIG. 1 is a schematic side sectional view of a first embodiment of the MIS field effect transistor of the present invention, FIG. 2 is a schematic plan view of the first embodiment of the MIS field effect transistor of the present invention, and FIG. FIG. 4 is a schematic side sectional view of a second embodiment of the field effect transistor, FIG. 4 is a schematic plan view of the second embodiment of the MIS field effect transistor of the present invention, and FIG. FIG. 6 is a schematic plan view of a third embodiment of the MIS field-effect transistor of the present invention, and FIG. 7 is a schematic side cross-sectional view of a fourth embodiment of the MIS field-effect transistor of the present invention. FIG. 8 is a schematic plan view of a fourth embodiment of the MIS field effect transistor of the present invention, and FIG. 9 is a schematic plan view of a fifth embodiment of the MIS field effect transistor of the present invention. FIG. 10 is a schematic side sectional view of a sixth embodiment of the MIS field effect transistor of the present invention, FIG. 11 is a schematic side sectional view of a seventh embodiment of the MIS field effect transistor of the present invention, and FIG. FIG. 13 is a schematic plan view of a seventh embodiment of the MIS field-effect transistor of the present invention, FIG. 13 is a schematic side sectional view of an eighth embodiment of the MIS field-effect transistor of the present invention, and FIG. 14 is a MIS field-effect transistor of the present invention. , FIG. 15 is a schematic side sectional view of a ninth embodiment of the MIS field-effect transistor of the present invention, and FIG. 16 is a schematic plan view of a tenth embodiment of the MIS field-effect transistor of the present invention. FIG. 17 is a schematic side sectional view, FIG. 17 is a schematic plan view of a MIS field-effect transistor according to a tenth embodiment of the present invention, and FIGS. Sectional views of an embodiment of a manufacturing method in fruit transistor, FIGS. 26 32 are sectional views of another embodiment of the manufacturing method in the MIS field effect transistor of the present invention.
The same object is denoted by the same reference numeral throughout the drawings. However, the diagonal lines in the side sectional views are drawn only on the main insulating film, and the wiring is drawn with a slight shift before and after, and the size in the horizontal and vertical directions is accurate to show the main part of the invention. The dimensions are not shown.
1 and 2 show a first embodiment (FIG. 1 is a schematic side sectional view, FIG. 2 is a schematic plan view) of a vertical MIS field-effect transistor according to the present invention, in which a p-type epitaxial silicon layer having a columnar structure is formed. Shows a part of a semiconductor integrated circuit including a short-channel N-channel MIS field-effect transistor formed using a p-type silicon substrate described above, where 1 is 10 ^Fifteen cm ^-3 A p-type silicon substrate, and 2 is a trench for forming an element isolation region and a buried insulating film (SiO 2). ₂ ), 3 is 10 ¹⁷ cm ^-3 The p-type channel stopper region having a height of about 200 nm, a width of about 50 nm, and a concentration of 10 ¹⁶ cm ^-3 P-type epitaxial silicon layer having a columnar structure of ²⁰ cm ^-3 Degree n ⁺ Mold source region, 6 is 10 ¹⁷ cm ^-3 N-type drain region, 7 is 10 ²⁰ cm ^-3 Degree n ⁺ Type drain region 8 is an insulating film (SiO ₂ ), 9 is a conductive film (TiN 2), 10 is a gate oxide film (SiO 2) of about 10 nm. ₂ / Ta ₂ O ₅ ), 11 is a barrier metal (TiN) of about 20 nm, 12 is a gate electrode (Al) of about 200 nm in thickness, 13 is a phosphosilicate glass (PSG) film of about 600 nm, and 14 is a barrier metal (TiN) of about 20 nm. ) And 15 are conductive plugs (W), 16 is a barrier metal (TiN) of about 50 nm, 17 is an AlCu wiring of about 500 nm, and 18 is a barrier metal (TiN) of about 50 nm.
In FIG. 1, a trench 2 for forming an element isolation region in which an insulating film is buried in a p-type silicon substrate 1 is selectively provided, and a p-type channel stopper region 3 is formed at the bottom of the trench 2 for forming the element isolation region. Is provided. A p-type epitaxial silicon layer 4 having a columnar structure is selectively provided on the p-type silicon substrate 1 separated from the insulation, and an n-type epitaxial silicon layer 4 is formed on the p-type epitaxial silicon layer 4 having a columnar structure. ⁺ An n-type drain region 7 and an n-type drain region 6 are provided. The n-type drain region 6 is diffused in the horizontal direction (lateral direction) on the upper surface of the p-type silicon substrate 1 and fills the bottom of the p-type epitaxial silicon layer 4 having a columnar structure. ⁺ A source electrode 5 is provided, a gate electrode 12 having a barrier metal 11 is provided on a side surface of a p-type epitaxial silicon layer 4 having a columnar structure via a gate oxide film 10, and a p-type epitaxial silicon layer having a columnar structure is provided. N provided on top of layer 4 ⁺ N in contact with the drain region 7 ⁺ A conductive film 9 wider than the mold drain region 7 is provided, and is connected to an AlCu wiring 17 having barrier metals (16, 18) above and below via a conductive plug 15 having a barrier metal 14, respectively. N-channel MIS field-effect transistor is formed.
Therefore, a drain region, a channel region, and a source region can be formed in a fully depleted columnar structure epitaxial semiconductor layer selectively formed using a normal semiconductor substrate without using a bonded SOI structure semiconductor substrate. Since the source region can form an epitaxial semiconductor layer electrically insulated and separated from the semiconductor substrate, a fully depleted pseudo SOI structure can be easily formed, and the junction capacitance of the drain region can be reduced (substantially zero). In addition, the threshold voltage can be reduced by reducing the depletion layer capacitance and improving the sub-threshold characteristics.
Further, the channel length that determines various characteristics of the MIS field-effect transistor can be determined by the growth thickness of the epitaxial semiconductor layer with good controllability and the diffusion of impurities by heat treatment without depending on the control of the gate length by the photolithography technique. Thus, an MIS field-effect transistor having stable characteristics can be obtained even for a large-diameter wafer.
Further, since the channel region can be completely surrounded by the gate electrode, a high-performance and highly reliable MIS field-effect transistor having extremely excellent leakage characteristics can be obtained.
In addition, a low-concentration region formed as a means for improving the deterioration of transmission conductance over the lifetime due to a hot carrier effect caused by a strong electric field near the drain region can be formed only in the drain region and not in the source region. In addition, the resistance of the source region can be reduced, and the channel length can be reduced without deteriorating the breakdown voltage.
Ta having a high dielectric constant ₂ O ₅ Can be used as a gate oxide film, so that the thickness of the gate oxide film can be increased, minute current leakage between the gate electrode and the epitaxial semiconductor layer can be improved, and gate capacitance can be reduced.
In addition, since the source / drain region requiring high-temperature heat treatment for activation of the impurity region can be formed by self-alignment before forming the gate electrode, a low-resistance low melting point metal (Al) can be formed without using a polycrystalline silicon film. Since the gate electrode can be formed, the resistance of the gate electrode wiring can be reduced and the depletion layer capacitance at the gate electrode can be removed, so that the power consumption can be reduced by reducing the threshold voltage.
In addition, each element (a low-concentration and high-concentration drain region, a high-concentration source region, a gate oxide film, a gate electrode, and a barrier metal) can be formed by self-alignment with the epitaxial semiconductor layer having a columnar structure.
As a result, high speed, low power, high reliability, high performance, and high performance can be achieved by using a columnar epitaxial semiconductor layer formed by an easy process on a semiconductor substrate without using an expensive semiconductor substrate having an SOI structure. A vertical MIS field-effect transistor having a pseudo-SOI structure and having a channel-enclosed low-resistance metal gate electrode combined with integration can be obtained.
[0007]
3 and 4 show a vertical MIS field-effect transistor according to a second embodiment of the present invention (FIG. 3 is a schematic side sectional view, and FIG. 4 is a schematic plan view). 1 shows a part of a semiconductor integrated circuit including a short-channel N-channel MIS field-effect transistor formed using a formed p-type silicon substrate, and 1 to 18 show the same parts as those in FIG. (However, 4 has a cylindrical structure)
In FIG. 1, instead of forming a p-type epitaxial silicon layer 4 having a columnar structure on a p-type silicon substrate 1, a p-type epitaxial silicon layer 4 having a cylindrical structure is formed. The film 9 is buried, and n ⁺ A short-channel N-channel MIS field-effect transistor having substantially the same structure as that of FIG. 1 except that it is in contact with the drain region 7 is formed.
In this embodiment, the same effects as those of the first embodiment can be obtained, and it can be formed finer depending on the layout. Further, a MIS field effect transistor having a pseudo SOI structure is formed in the horizontal direction. I can understand that
[0008]
FIGS. 5 and 6 show a third embodiment (FIG. 5 is a schematic side sectional view, and FIG. 6 is a schematic plan view) of a vertical MIS field-effect transistor according to the present invention. 1 shows a part of a semiconductor integrated circuit including a short-channel N-channel MIS field-effect transistor formed using a formed p-type silicon substrate, and 1 to 18 show the same parts as those in FIG. (However, 4 has a cylindrical structure)
In FIG. 1, a p-type epitaxial silicon layer 4 having a cylindrical structure is formed on a p-type silicon substrate 1, and a gate electrode 12 having a barrier metal 11 is provided also on an inner side surface via a gate insulating film 10. A vertical short-channel N-channel MIS field-effect transistor having substantially the same structure as that of FIG. Here, in order to connect the gate electrode 12 formed on the inner side surface and the outer side surface of the p-type epitaxial silicon layer 4 having a cylindrical structure, one part of the epitaxial silicon layer 4 indicated by a broken line in FIG. Part (n ⁺ (A part of the mold drain region) is removed, and the gate electrode is connected above this portion.
In this embodiment, the same effects as those of the first embodiment can be obtained. Further, since the gate electrode is formed on the inner side surface, the transistor width can be increased, and higher speed can be expected.
[0009]
FIGS. 7 and 8 show a fourth embodiment (FIG. 7 is a schematic side sectional view and FIG. 8 is a schematic plan view) of a vertical MIS field-effect transistor according to the present invention. 1 shows a part of a semiconductor integrated circuit including a short-channel N-channel MIS field-effect transistor formed using a formed p-type silicon substrate, and 1 to 7 and 9 to 18 show the same thing as FIG. Is shown. (However, 4 has a cylindrical structure)
In the figure, n other than the connection with the wiring body is taken. ⁺ The mold source region 5 is provided only in the bottom and immediately below the p-type silicon substrate 1 of the p-type epitaxial silicon layer 4 having a cylindrical structure, and the remaining p-type silicon substrate 1 is used as the element isolation region 2. N inside the p-type epitaxial silicon layer 4 ⁺ Mold source region 5, n ⁺ Except that the connection between the mold drain region 7 and the gate electrode 12 and the wiring body is formed, it is formed with substantially the same concept as in the third embodiment.
In this embodiment, the same effects as those of the first embodiment can be obtained, and extremely high integration and high speed can be expected.
[0010]
FIG. 9 shows a vertical MIS field-effect transistor according to a fifth embodiment of the present invention, which is a short-channel N-channel MIS formed using a p-type silicon substrate on which a p-type epitaxial silicon layer having a columnar structure is formed. A part of a semiconductor integrated circuit including a field effect transistor is shown, wherein 1 to 18 are the same as those in FIG. 1, 19 is a barrier metal (TiN) of about 20 nm, and 20 is a metal layer (W).
In FIG. ⁺ A vertical short-channel N-channel MIS field-effect transistor having the same structure as that of FIG. 1 is formed except that a metal layer (W) 20 having a barrier metal (TiN) 19 is provided in the mold source region 5. .
In this embodiment, in addition to the same effects as those of the first embodiment, the resistance of the source region can be reduced, and the speed can be further increased.
[0011]
FIG. 10 shows a sixth embodiment of a vertical MIS field-effect transistor according to the present invention, which is a short-channel N-channel MIS formed using a p-type silicon substrate on which an n-type epitaxial silicon layer having a columnar structure is formed. 1 to 3, 5 and 7 to 18 are the same as those in FIG. 1, 21 is an n-type epitaxial silicon layer having a columnar structure, and 22 is a p-type impurity. 2 shows a region (channel region).
In FIG. 1, an n-type epitaxial silicon layer 21 having a columnar structure is formed on a p-type silicon substrate 1, and n-type epitaxial silicon layer 21 is formed on the n-type epitaxial silicon layer 21. ⁺ Type drain region 7 is provided, and p-type impurity region (channel region) 22 and n ⁺ A vertical short channel N-channel MIS field-effect transistor having the same structure as that of FIG. 1 except that the mold source region 5 is provided is formed. (This p-type impurity region is to be a channel region, and n ⁺ Implanted into the upper surface of the same p-type silicon substrate 1 as the p-type source region, but with a large diffusion coefficient, ⁺ It can be formed so as to include the mold source region. Also, unlike the LDD structure, since an n-type epitaxial silicon layer is formed instead of forming an n-type drain region, an enhancement / depletion type gate structure is formed, and the enhancement as in other embodiments is performed. It is different from the type gate structure. )
In the present embodiment, in addition to the same effects as those of the first embodiment, since the channel region can be formed finer, higher speed and higher integration can be achieved.
[0012]
FIGS. 11 and 12 show a seventh embodiment (FIG. 11 is a schematic side sectional view, and FIG. 12 is a schematic plan view) of a vertical MIS field-effect transistor according to the present invention. 1 to 18 show a part of a semiconductor integrated circuit including a short-channel N-channel MIS field-effect transistor formed using a formed p-type silicon substrate. Shows the same thing as FIG. (However, 4 has a cylindrical structure)
In the figure, only the bottom of the p-type epitaxial silicon layer 4 having a cylindrical structure and the p-type silicon substrate 1 directly underneath are n-type. ⁺ A source layer 5 is provided, a metal layer (W) 20 having a barrier metal 19 is provided on a p-type silicon substrate 1 immediately below the p-type epitaxial silicon layer 4 having a cylindrical structure, and the remaining p-type silicon is provided. A vertical short-channel N-channel MIS field-effect transistor having substantially the same structure as that of FIG. 3 except that an element isolation region 2 in which an oxide film is embedded is provided in a substrate 1 is formed.
In the present embodiment, in addition to the same effects as those of the first embodiment, the resistance of the source region can be reduced and the speed can be further increased. Since a potential can be applied, high integration can be achieved.
[0013]
13 and 14 show an eighth embodiment (FIG. 13 is a schematic side sectional view, and FIG. 14 is a schematic plan view) of a vertical MIS field-effect transistor according to the present invention. 1 shows a part of a C-MOS type semiconductor integrated circuit including short-channel N-channel and P-channel MIS field-effect transistors formed using a p-type silicon substrate on which an epitaxial silicon layer is formed; 18 is the same as FIG. 1 (4 is a cylindrical structure), 21 is the same as FIG. 10 (but a cylindrical structure), 23 is an n-type impurity well region, and 24 is a p-type impurity well region. ⁺ Mold source region, 25 is p ⁺ 5 shows a mold drain region.
In FIG. 1, a trench 2 for forming an element isolation region in which an insulating film is buried in a p-type silicon substrate 1 is selectively provided, and a p-type channel stopper region 3 is formed at the bottom of the trench 2 for forming the element isolation region. Is provided. A p-type epitaxial silicon layer 4 having a cylindrical structure is selectively provided on the right side of the insulated p-type silicon substrate 1, and an upper part of the p-type epitaxial silicon layer 4 having a cylindrical structure is provided on the right side. n ⁺ An n-type drain region 7 and an n-type drain region 6 are provided. The n-type drain region 6 is laterally diffused on the upper surface of the p-type silicon substrate 1 and fills the bottom of the p-type epitaxial silicon layer 4 having a cylindrical structure. ⁺ A source electrode 5 is provided, a gate electrode 12 having a barrier metal 11 is provided on a side surface of the p-type epitaxial silicon layer 4 having a cylindrical structure via a gate oxide film 10, and a p-type epitaxial silicon layer 4 having a cylindrical structure is provided. N provided on the epitaxial silicon layer 4 ⁺ N in contact with the drain region 7 ⁺ A conductive film 9 wider than the mold drain region 7 is provided, and is connected to an AlCu wiring 17 having barrier metals (16, 18) above and below via a conductive plug 15 having a barrier metal 14, respectively. N-channel MIS field-effect transistor is formed. On the other hand, an n-type impurity well region 23 is provided on the left side of the insulated p-type silicon substrate 1, and an n-type epitaxial silicon layer 21 having a cylindrical structure is selectively formed on the n-type impurity well region 23. Is provided above the n-type epitaxial silicon layer 21 having the cylindrical structure. ⁺ A p-type drain region 25 is provided, and p is filled laterally on the upper surface of n-type impurity well region 23 to fill the bottom of n-type epitaxial silicon layer 21 having a cylindrical structure. ⁺ A gate electrode 12 having a barrier metal 11 via a gate oxide film 10 on a side surface of an n-type epitaxial silicon layer 21 having a cylindrical structure, and an n-type epitaxial silicon layer 21 having a cylindrical structure. P provided on the epitaxial silicon layer 21 ⁺ In contact with the drain region 25, ⁺ A conductive film 9 wider than the mold drain region 25 is provided, and is connected to an AlCu wiring 17 having barrier metals (16, 18) above and below via a conductive plug 15 having a barrier metal 14, respectively. Are formed. (However, the gate electrode 12 is connected by the common AlCu wiring 17)
In the present embodiment, the same effects as in the first embodiment can be obtained also in the C-MOS.
[0014]
FIG. 15 shows a ninth embodiment of a vertical MIS field-effect transistor according to the present invention, which is a short channel formed using a p-type silicon substrate on which p-type and n-type epitaxial silicon layers having a cylindrical structure are formed. 1 to 18 show a part of a C-MOS type semiconductor integrated circuit including N-channel and P-channel MIS field-effect transistors, wherein 1 to 18 are the same as those in FIG. 1 (4 is a cylindrical structure), and 21 is The same thing as FIG. 10 (however, cylindrical structure), 23 to 25 show the same thing as FIG.
13, the n-channel epitaxial layer and the n-channel epitaxial layer have substantially the same structure as that of FIG. 13 except that the n-type epitaxial silicon layer is longer than the p-type epitaxial silicon layer, that is, the channel length of the p-channel MIS field-effect transistor is increased. A channel MIS field-effect transistor is formed.
Also in this embodiment, the same effect as in the eighth embodiment can be obtained, and the channel length of the source / drain region can be optimized by the p-type impurity having a large diffusion coefficient as compared with the source / drain region by the n-type impurity. In addition, it is possible to prevent deterioration of the breakdown voltage of the source / drain region.
[0015]
16 and 17 show a tenth embodiment (FIG. 16 is a schematic side sectional view, and FIG. 17 is a schematic plan view) of a vertical MIS field-effect transistor according to the present invention. 1 shows a part of a C-MOS type semiconductor integrated circuit including short-channel N-channel and P-channel MIS field-effect transistors formed using a p-type silicon substrate on which an epitaxial silicon layer is formed; Reference numeral 18 denotes the same object as in FIG. 1 (4 is a cylindrical structure), 21 denotes the same object as in FIG. 10 (but a cylindrical structure), and 23 to 25 denote the same objects as in FIG.
In the same figure, in order to finely form the source regions (5, 24) other than the portions where the connection with the AlCu wiring 17 is made, only the bottom of the n-type epitaxial silicon layer 21 has ⁺ Type source region 24 is formed only at the bottom of p type epitaxial silicon layer 4 by n. ⁺ An N-channel and P-channel MIS field-effect transistor having substantially the same structure as that of FIG. 13 except that the mold source region 5 is provided is formed.
Also in this embodiment, the same effects as in the eighth embodiment can be obtained, and higher integration can be achieved.
[0016]
Next, one embodiment of the method of manufacturing the MIS field-effect transistor according to the present invention will be described with reference to FIGS. 18 to 25 and FIG. 1, and another embodiment will be described with reference to FIGS. 26 to 32 and FIG. I do. However, here, only the manufacturing method relating to the formation of the MIS field effect transistor of the present invention will be described, and the description of the manufacturing method relating to the formation of various elements (other transistors, resistors, capacitors, etc.) mounted on a general semiconductor integrated circuit will be described. Is omitted.
FIG.
Using a normal photolithography technique and using a resist (not shown) as a mask layer, the p-type silicon substrate 1 is selectively anisotropically dry-etched by about 1000 nm to form a trench 2 for forming an element isolation region. . Next, boron ions are implanted to form a p-type channel stopper region 3 at the bottom of the trench 2 for forming an element isolation region. Next, the resist (not shown) is removed. Next, an oxide film (SiO 2) of about 500 nm is formed by chemical vapor deposition. ₂ Grow). Next, chemical mechanical polishing ( C he-mical M technical P (hereinafter, abbreviated as CMP), and an oxide film is buried flat in the trench 2 for forming an element isolation region.
FIG.
Next, an oxide film (SiO 2) of about 200 nm is formed by chemical vapor deposition. ₂ ) Grow 26. Next, the oxide film 26 is selectively anisotropically dry-etched by using a resist (not shown) as a mask layer using a normal photolithography technique. Next, the resist (not shown) is removed.
FIG.
Next, a p-type epitaxial silicon layer 4 is grown on the exposed p-type silicon substrate 1 to a thickness of about 250 nm. Next, chemical mechanical polishing (CMP) is performed to remove and planarize the p-type epitaxial silicon layer 4 protruding from the flat surface of the oxide film 26. Next, an oxide film (not shown) for ion implantation of about 10 nm is grown by chemical vapor deposition. Next, ion implantation of phosphorus for forming the n-type drain region 6 is performed.
FIG.
Next, an oxide film (not shown) for ion implantation and the oxide film 26 are subjected to anisotropic dry etching. (Thus, the p-type epitaxial silicon layer 4 having a columnar structure is formed.) Then, an oxide film (not shown) for ion implantation of about 10 nm is grown by chemical vapor deposition. Then n ⁺ Arsenic ions for forming the source / drain regions 5 and 7 are implanted. (Thus, without a mask layer, n-type epitaxial silicon layer 4 having a columnar structure and n-type ⁺ Arsenic for forming the source / drain regions 5 and 7 is ion-implanted in a self-aligned manner. ) Then at about 800 ° C ₂ By performing the annealing, n is diffused vertically in the upper part of the p-type epitaxial silicon layer 4 having the columnar structure. ⁺ An n-type drain region 7 and an n-type drain region 6 diffuse laterally on the upper surface of the p-type silicon substrate 1 to fill the bottom of the p-type epitaxial silicon layer 4 having a columnar structure. ⁺ A mold source region 5 is formed. Next, an oxide film (not shown) for ion implantation is isotropically dry-etched.
FIG.
Next, a gate oxide film (SiO ₂ / Ta ₂ O ₅ ) Grow ten. Next, a barrier metal (TiN) 11 of about 20 nm and Al12 to be a gate electrode of about 200 nm are grown by continuous sputtering. Next, using a normal photolithography technique, using a resist (not shown) as a mask layer, Al, a barrier metal (TiN 2), and a gate oxide film (SiO 2) ₂ / Ta ₂ O ₅ ) Are sequentially subjected to anisotropic dry etching. (The reason why the etching is performed using the mask layer here is to form a gate electrode wiring portion other than the side surface of the p-type epitaxial silicon layer 4 having a columnar structure.) Then, the resist (not shown) is removed. I do.
FIG.
Next, chemical mechanical polishing (CMP) is performed, and Al, a barrier metal (TiN 2) and a gate oxide film (SiO 2) remaining on the p-type epitaxial silicon layer 4 are left. ₂ / Ta ₂ O ₅ ). Next, Al is anisotropically dry-etched by about 50 nm. Next, anisotropic dry etching is performed on the barrier metal (TiN) by about 50 nm. Next, a gate oxide film (SiO ₂ / Ta ₂ O ₅ ) Is subjected to anisotropic dry etching. (Thus n ⁺ The upper surface of the gate electrode is made lower than the upper surface of the mold drain region 7. However, the gate oxide film need not be removed by etching. )
FIG.
Next, an oxide film (SiO 2) of about 200 nm is formed by chemical vapor deposition. ₂ ) Grow 8. Next, chemical mechanical polishing (CMP) is performed to form an oxide film (SiO 2) on the p-type epitaxial silicon layer 4 having a columnar structure. ₂ ) 8 is removed and flattened. Then, about 30 nm of TiN 9 is grown by sputtering. Next, using an ordinary photolithography technique, TiN 9 is anisotropically dry-etched using a resist (not shown) as a mask layer. Next, the resist (not shown) is removed.
FIG.
Next, a phosphosilicate glass (PSG) film 13 of about 600 nm is grown by chemical vapor deposition. Next, the PSG film 13 is anisotropically dry-etched using a resist (not shown) as a mask layer, and a via is selectively opened using a normal photolithography technique. Next, the resist (not shown) is removed. Next, TiN 14 serving as a barrier metal is grown by sputtering. Next, tungsten (W) 15 is grown by chemical vapor deposition. Next, the via is flatly buried in the via by chemical mechanical polishing (CMP) to form a conductive plug (W) 15.
FIG.
Next, TiN 16 serving as a barrier metal is grown to a thickness of about 50 nm by sputtering. Next, Al (containing several% of Cu) 17 serving as a wiring is grown to a thickness of about 500 nm by sputtering. Next, TiN 18 serving as a barrier metal is grown to a thickness of about 50 nm by sputtering. Next, using a resist (not shown) as a mask layer, anisotropic dry etching is performed on the barrier metal (TiN 2), Al (including several percent of Cu), and the barrier metal (TiN 2) using a normal photolithography technique. An AlCu wiring 17 is formed to complete a vertical MIS field effect transistor having a pseudo SOI structure having a channel-enclosed low-resistance metal gate electrode of the present invention.
[0017]
Next, another embodiment of the method of manufacturing the MIS field-effect transistor according to the present invention will be described with reference to FIGS. 26 to 32 and FIG.
FIG.
An oxide film (SiO 2) of about 250 nm is formed on a p-type silicon substrate 1 by chemical vapor deposition. ₂ ) Growing 27. Next, the oxide film 27 is selectively anisotropically dry-etched using a resist (not shown) as a mask layer by using a usual photolithography technique. Next, the resist (not shown) is removed.
FIG.
Next, a p-type epitaxial silicon layer 4 is grown on the exposed p-type silicon substrate 1 to a thickness of about 300 nm. Next, chemical mechanical polishing (CMP) is performed to remove and planarize the p-type epitaxial silicon layer 4 protruding from the flat surface of the oxide film 27. Next, the p-type epitaxial silicon layer 4 is anisotropically dry-etched by 50 nm to form a concave portion. Next, by chemical vapor deposition, a nitride film (Si ₃ N ₄ ) Grow 28. Next, chemical mechanical polishing (CMP) is performed to form a nitride film (Si ₃ N ₄ ) 28 is removed and buried flat in the recess. Next, ion implantation of phosphorus for forming the n-type drain region 6 is performed.
FIG.
Next, oxide film 27 is anisotropically dry-etched. (Thus, the p-type epitaxial silicon layer 4 having a cylindrical structure is formed.) Then, an oxide film (not shown) for ion implantation of about 10 nm is grown by chemical vapor deposition. Then n ⁺ Arsenic ions for forming the source / drain regions 5 and 7 are implanted. (Thus, without the mask layer, n-type epitaxial silicon layer 4 having a cylindrical structure and n-type ⁺ Arsenic for forming the source / drain regions 5 and 7 is ion-implanted in a self-aligned manner. ) Then at about 800 ° C ₂ By annealing, n is diffused vertically in the upper part of the p-type epitaxial silicon layer 4 having a cylindrical structure. ⁺ The n-type drain region 7 and the n-type drain region 6 are diffused laterally on the upper surface of the p-type silicon substrate 1 to fill the bottom of the p-type epitaxial silicon layer 4 having a cylindrical structure. ⁺ A mold source region 5 is formed. Next, an oxide film (not shown) for ion implantation is isotropically dry-etched.
FIG.
Next, using a normal photolithography technique, a resist (not shown) and a nitride film (Si ₃ N ₄ 2.) Using the mask 28 as a mask layer, the p-type silicon substrate 1 is selectively anisotropically dry-etched to about 1000 nm to form a trench 2 for forming an element isolation region. Next, boron ions are implanted to form a p-type channel stopper region 3 at the bottom of the trench 2 for forming an element isolation region. Next, the resist (not shown) is removed. Next, a nitride film (Si ₃ N ₄ ) 28 is anisotropically dry-etched.
FIG.
Next, an oxide film (SiO 2) of about 500 nm is formed by chemical vapor deposition. ₂ Grow). Next, chemical mechanical polishing (CMP) is performed to form an oxide film (SiO 2) on the p-type epitaxial silicon layer 4 having a cylindrical structure. ₂ ) Is removed and flattened. Then, using an ordinary photolithography technique, a resist (not shown) is used as a mask layer to selectively form an oxide film (SiO 2). ₂ ) Is anisotropically dry-etched by about 30 nm to form a concave portion. Next, the resist (not shown) is removed. Then, about 30 nm of TiN 9 is grown by sputtering. Next, chemical mechanical polishing (CMP) is performed to fill the recesses and flatten. Next, an oxide film of about 200 nm is anisotropically dry-etched to form an element isolation region 2.
FIG.
Next, a gate oxide film (SiO ₂ / Ta ₂ O ₅ ) Grow ten. Next, a barrier metal (TiN) 11 of about 20 nm and Al12 to be a gate electrode of about 200 nm are grown by continuous sputtering. Next, using a normal photolithography technique, using a resist (not shown) as a mask layer, Al, a barrier metal (TiN 2), and a gate oxide film (SiO 2) ₂ / Ta ₂ O ₅ ) Are sequentially subjected to anisotropic dry etching. (The reason why the etching is performed using the mask layer here is to form a gate electrode wiring portion other than the side surface of the p-type epitaxial silicon layer 4 having a cylindrical structure.) Then, a resist (not shown) is formed. Remove. Next, chemical mechanical polishing (CMP) is performed, and Al, a barrier metal (TiN 2) and a gate oxide film (SiO 2) remaining on the p-type epitaxial silicon layer 4 are left. ₂ / Ta ₂ O ₅ ).
FIG.
Next, a phosphor silicate glass (PSG) film 13 of about 800 nm is grown by chemical vapor deposition. Next, the PSG film 13 is anisotropically dry-etched using a resist (not shown) as a mask layer, and a via is selectively opened using a normal photolithography technique. Next, the resist (not shown) is removed. Next, TiN 14 serving as a barrier metal is grown by sputtering. Next, tungsten (W) 15 is grown by chemical vapor deposition. Next, the via is flatly buried in the via by chemical mechanical polishing (CMP) to form a conductive plug (W) 15.
FIG.
Next, TiN 16 serving as a barrier metal is grown to a thickness of about 50 nm by sputtering. Next, Al (containing several% of Cu) 17 serving as a wiring is grown to a thickness of about 500 nm by sputtering. Next, TiN 18 serving as a barrier metal is grown to a thickness of about 50 nm by sputtering. Next, using a resist (not shown) as a mask layer, anisotropic dry etching is performed on the barrier metal (TiN 2), Al (including several percent of Cu), and the barrier metal (TiN 2) using a normal photolithography technique. An AlCu wiring 17 is formed to complete a vertical MIS field effect transistor having a pseudo SOI structure having a channel-enclosed low-resistance metal gate electrode of the present invention.
[0018]
In the above description, the case where an epitaxial silicon layer is formed on a silicon substrate is described. However, a compound semiconductor layer may be formed on a silicon substrate, and the present invention is not limited to a silicon substrate. Good. When forming the semiconductor layer having a convex structure, an epitaxial semiconductor layer is used.However, by providing a trench in the semiconductor substrate, a semiconductor substrate formed in a columnar structure or a cylindrical structure may be used, When stacking semiconductor layers, not only by chemical vapor deposition, but also by molecular beam epitaxy (MBE), metal organic chemical vapor deposition (MOCVD), atomic layer crystal epitaxy (ALE), and others. May be used. Further, the planar shape of the columnar structure or the cylindrical structure may be a straight line, a curved line, a circle, a rectangle, another geometric shape, or a double shape. The invention of the present application is satisfied even if the number is three or three. Further, the conductive film, the metal layer, the gate electrode, the barrier metal, the conductive plug, the wiring, and the like are not limited to those in the above-described embodiment, and any material having similar characteristics may be used. In all of the above embodiments, the drain region is formed on the upper portion of the epitaxial semiconductor layer and the source region is formed on the bottom portion. However, in this case, the junction capacitance of the source region can be reduced, but the junction capacitance of the drain region cannot be reduced. In addition, although the sixth embodiment is easier to manufacture, the other embodiments are slightly more difficult. It gets messy. (Complicating the top of the epitaxial semiconductor layer is easier to manufacture than complicating the bottom.) All of the above embodiments describe the case of forming an enhancement-type MIS field-effect transistor. A depletion-type MIS field-effect transistor may be formed. In this case, an epitaxial semiconductor layer of the opposite conductivity type is grown, or an epitaxial semiconductor layer having a similar structure is formed by growing the epitaxial semiconductor layer and then ion-implanting impurities of the opposite conductivity type to convert the conductivity type. An MIS field-effect transistor may be formed.
[0019]
【The invention's effect】
As described above, according to the present invention, a fully depleted semiconductor layer (semiconductor substrate) selectively formed using a normal semiconductor substrate without using a semiconductor substrate having a bonded SOI structure is used. An epitaxial semiconductor layer or a part of a semiconductor substrate formed in a columnar structure or a cylindrical structure by forming a trench in a semiconductor substrate or an epitaxial semiconductor layer stacked in a columnar structure or a cylindrical structure on the semiconductor substrate. Since the drain region, the channel region, and the source region having the pseudo SOI structure can be formed, the junction capacitance of the drain region (or the source region) can be reduced (substantially zero).
In addition, since a fully depleted pseudo SOI substrate can be easily formed, the capacitance of the depletion layer can be reduced and the threshold voltage can be reduced by improving the subthreshold characteristics.
Further, the channel length of the MIS field-effect transistor can be determined by the growth thickness of the epitaxial semiconductor layer having good controllability and the diffusion of impurities by heat treatment without depending on the control of the gate length by the photolithography technique.
Further, since the channel region can be completely surrounded by the gate electrode, a MIS field effect transistor having extremely excellent leakage characteristics can be obtained.
In addition, since a low-concentration region formed as a measure for improving the hot carrier effect can be formed only in the necessary drain region, the resistance of the source region can be reduced, and the channel length can be reduced without deteriorating the breakdown voltage. It is also possible.
In addition, high dielectric constant Ta ₂ O ₅ Is used as a gate oxide film, so that the thickness of the gate oxide film can be increased, a minute current leak between the gate electrode and the semiconductor layer in the channel formation portion can be improved, and the gate capacitance can be reduced.
In addition, since a gate electrode made of a low-resistance low-melting-point metal can be formed, the resistance of the gate electrode wiring can be reduced and the depletion layer capacitance at the gate electrode can be eliminated.
Further, each element of the MIS field-effect transistor can be finely formed by self-alignment with the semiconductor layer formed in the convex structure. It is also possible to form a highly integrated C-MOS.
That is, by using a semiconductor layer having a convex structure formed on a semiconductor substrate without using a semiconductor substrate having an expensive SOI structure, a semiconductor integrated circuit capable of supporting high-speed, large-capacity communication, a portable information terminal, and the like. It is possible to obtain a vertical MIS field-effect transistor having a pseudo SOI structure having a channel-enclosed low-resistance metal gate electrode having high speed, low power, high reliability, high performance, and high integration, which enables manufacturing.
[Brief description of the drawings]
FIG. 1 is a schematic side sectional view of a first embodiment of a MIS field-effect transistor of the present invention.
FIG. 2 is a schematic plan view of a first embodiment of the MIS field-effect transistor of the present invention.
FIG. 3 is a schematic side sectional view of a MIS field-effect transistor according to a second embodiment of the present invention.
FIG. 4 is a schematic plan view of a second embodiment of the MIS field-effect transistor of the present invention.
FIG. 5 is a schematic side sectional view of a third embodiment of the MIS field-effect transistor of the present invention.
FIG. 6 is a schematic plan view of a third embodiment of the MIS field-effect transistor of the present invention.
FIG. 7 is a schematic side sectional view of a fourth embodiment of the MIS field-effect transistor of the present invention.
FIG. 8 is a schematic plan view of a MIS field-effect transistor according to a fourth embodiment of the present invention.
FIG. 9 is a schematic side sectional view of a fifth embodiment of the MIS field-effect transistor of the present invention.
FIG. 10 is a schematic side sectional view of a sixth embodiment of the MIS field-effect transistor of the present invention.
FIG. 11 is a schematic side sectional view of a MIS field-effect transistor according to a seventh embodiment of the present invention.
FIG. 12 is a schematic plan view of a MIS field-effect transistor according to a seventh embodiment of the present invention.
FIG. 13 is a schematic side sectional view of an eighth embodiment of the MIS field-effect transistor of the present invention.
FIG. 14 is a schematic plan view of an MIS field-effect transistor according to an eighth embodiment of the present invention.
FIG. 15 is a schematic side sectional view of a ninth embodiment of the MIS field-effect transistor of the present invention.
FIG. 16 is a schematic side sectional view of a tenth embodiment of the MIS field-effect transistor of the present invention.
FIG. 17 is a schematic plan view of a MIS field-effect transistor according to a tenth embodiment of the present invention.
FIG. 18 is a process sectional view of one embodiment of a method for manufacturing a MIS field-effect transistor of the present invention.
FIG. 19 is a process sectional view of one embodiment of a method for manufacturing a MIS field-effect transistor of the present invention.
FIG. 20 is a process cross-sectional view of one embodiment of a method for manufacturing a MIS field-effect transistor of the present invention.
FIG. 21 is a process cross-sectional view of one embodiment of a method for manufacturing a MIS field-effect transistor of the present invention.
FIG. 22 is a process sectional view of an embodiment of a method for manufacturing a MIS field-effect transistor of the present invention.
FIG. 23 is a process cross-sectional view of one embodiment of a method for manufacturing a MIS field-effect transistor of the present invention.
FIG. 24 is a process sectional view of an embodiment of a method for manufacturing a MIS field-effect transistor of the present invention.
FIG. 25 is a process sectional view of an embodiment of a method for manufacturing a MIS field-effect transistor of the present invention.
FIG. 26 is a process sectional view of another example of the method for manufacturing the MIS field-effect transistor of the present invention.
FIG. 27 is a process sectional view of another embodiment of the method of manufacturing the MIS field-effect transistor of the present invention.
FIG. 28 is a process sectional view of another embodiment of the method of manufacturing the MIS field-effect transistor of the present invention.
FIG. 29 is a process cross-sectional view of another embodiment of the method of manufacturing the MIS field-effect transistor of the present invention.
FIG. 30 is a process cross-sectional view of another example of the method for manufacturing the MIS field-effect transistor of the present invention.
FIG. 31 is a process sectional view of another embodiment of the method of manufacturing the MIS field-effect transistor of the present invention.
FIG. 32 is a process sectional view of another example of the method for manufacturing the MIS field-effect transistor of the present invention.
FIG. 33 is a schematic side sectional view of a conventional MIS field-effect transistor.
[Explanation of symbols]
1p type silicon substrate
2 Trench and buried insulating film (SiO ₂ )
3 p-type channel stopper region
4 p-type epitaxial silicon layer with convex structure (columnar structure or cylindrical structure)
5 n ⁺ Type source area
6 N-type drain region
7 n ⁺ Drain region
8 Buried insulating film (SiO ₂ )
9 Connecting conductive film (TiN)
10 Gate oxide film (SiO ₂ / Ta ₂ O ₅ )
11 Barrier metal (TiN)
12 Gate electrode (Al)
13. Phosphosilicate glass (PSG) film
14 Barrier metal (TiN)
15 Conductive plug (W)
16 Barrier metal (TiN)
17 AlCu wiring
18 Barrier metal (TiN)
19 Barrier metal (TiN)
20 Metal (W)
21 n-type epitaxial silicon layer with convex structure (columnar structure or cylindrical structure)
22 p-type impurity region (channel region)
23 n-type impurity well region
24p ⁺ Type source area
25 p ⁺ Drain region
26 Oxide film (SiO ₂ )
27 Oxide film (SiO ₂ )
28 Nitride film (Si ₃ N ₄ )

Claims (3)

A semiconductor substrate formed selectively having a convex structure portion (a columnar structure portion or a cylindrical structure portion); and a gate electrode provided on a side surface of the convex structure portion of the semiconductor substrate via a gate insulating film. And a drain region (or a source region) provided above the convex structure portion of the semiconductor substrate, and at least separated from the drain region (or the source region) and opposed to the drain region (or the source region). The semiconductor device includes a source region (or a drain region) provided at the bottom of the convex structure portion of the semiconductor substrate, and a wiring body provided at the drain region, the source region, and the gate electrode. MIS field effect transistor. 2. The MIS field-effect transistor according to claim 1, wherein the convex structure portion of the semiconductor substrate is a semiconductor layer laminated on the semiconductor substrate or is a part of the semiconductor substrate. . After the semiconductor substrate having the convex structure portion is formed, impurities are introduced into the upper surface of the convex structure portion and the flat portion of the semiconductor substrate, and heat treatment is performed, so that the semiconductor substrate has A drain region (or a source region) diffused in a vertical direction and a source region (or a drain region) that is horizontally diffused in a flat portion of the semiconductor substrate and fills the bottom of the convex structure portion of the semiconductor substrate. A method for forming a source / drain region of a MIS field-effect transistor, characterized in that:

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