JPH11214684A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device with a MOS transistor which has a desired operating speed. SOLUTION: An n-type diffused wiring layer 8 is formed on a p-type well 7. An n<+> -type silicone epitaxial growth layer as a source region, a p<-> -type selective silicon epitaxial growth layer 13 as a channel region, and an n<+> -type selective silicon epitaxial growth layer 23 as a drain region are laminated on the n-type diffused wiring layer 8. A gate electrode 19 is formed only on the side surface of the p<-> -type selective silicon epitaxial growth layer 13 via a gate insulation film 18.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device including a field-effect transistor and a method for manufacturing the same.

[0002]

2. Description of the Related Art As a conventional field effect transistor,
Regarding an example of a semiconductor device including a MOS transistor,
This will be described with reference to the drawings. Referring to FIG. 34, a p-type well 107 is formed on the surface of silicon substrate 101.
On the main surface of the p-type well 107, an n-type diffusion wiring layer 108 serving as a wiring is formed. Also, p-type well 1
Reference numeral 07 is electrically insulated from other regions by the element isolation oxide film 102.

On the n-type diffusion wiring layer 108, an n ⁺ -type selective silicon epitaxial growth layer 11 as a source region is provided.
2 are formed. On the n ⁺ type selective silicon epitaxial growth layer 112, p ⁻ as a channel region is provided.
A type-selective silicon epitaxial growth layer 113 is formed. On the p ⁻ type selective silicon epitaxial growth layer 113, an n ⁺ type selective silicon epitaxial growth layer 123 as a drain region is formed.

The side surfaces of the n ⁺ type selective silicon epitaxial growth layer 112, p ⁻ type selective silicon epitaxial growth layer 113 and n ⁺ type selective silicon epitaxial growth layer 123 are interposed with a silicon oxide film 118 as a gate insulating film to form a gate electrode. 119 are formed.

The gate electrode 119 is formed on the silicon substrate 1
01 is formed so as to cover the silicon nitride film 120 formed thereon. A silicon oxide film 127 is formed to cover gate electrode 119 and n ⁺ type selective silicon epitaxial growth layer 123. On the silicon oxide film 127, a metal wiring layer 129 electrically connected to the n ⁺ type selective silicon epitaxial growth layer 123 is formed.

In the structure described above, n ⁺ -type selective silicon epitaxial growth layers 112 and 123 as source or drain regions, p ⁻ -type selective silicon epitaxial growth layer 113 as channel regions and gate electrode 11
9 forms a MOS transistor. In particular, since the source, drain and channel regions have a laminated structure, a MOS transistor having such a structure is called a “vertical MOS transistor”.

Next, an example of a method for manufacturing a semiconductor device including the above-described vertical MOS transistor will be described with reference to the drawings. Referring to FIG. 35, an element isolation oxide film 102 having a thickness of about 4000 ° is formed on the main surface of silicon substrate 101 by LOCOS or the like. Next, referring to FIG.
By implanting boron ions or the like into the surface of the silicon substrate 101 by ion implantation or the like, the p-type well 107 is formed.
To form By implanting arsenic ions into the surface of the p-type well 107 by an ion implantation method or the like, an n-type diffusion wiring layer 108 serving as a wiring is formed.

Referring to FIG. 37, element isolation oxide film 1
A silicon nitride film 120 is formed on the silicon substrate 101 so as to cover the substrate 02. In the silicon nitride film 120,
An opening 131 exposing the surface of the n-type diffusion wiring layer 108 is formed. Next, referring to FIG. 38, an n ⁺ -type source region having a thickness of about 4000 ° is selectively formed on the surface of n-type diffusion wiring layer 108 exposed at the bottom of opening 131 by silicon epitaxial growth. A silicon epitaxial growth layer 112 is formed.

On the n ⁺ -type selective silicon epitaxial growth layer 112, a p ⁻ -type selective silicon epitaxial growth layer 113 having a thickness of about 4000 ° is formed as a channel region by a silicon epitaxial growth method. On the p ⁻ -type selective silicon epitaxial growth layer 113, an n ⁺ -type selective silicon epitaxial growth layer 123 having a thickness of about 4000 ° is formed as a drain region by a silicon epitaxial growth method.

Referring to FIG. 39, openings are formed in silicon nitride film 120 so as to expose n ⁺ type selective silicon epitaxial growth layers 112 and 123, p ⁻ type selective silicon epitaxial growth layer 113 and n type diffusion wiring layer 108. A part 132 is formed. Then, n ⁺
Type selective silicon epitaxial growth layers 112, 123,
A silicon oxide film 118 as a gate insulating film is formed on surfaces of p ⁻ type selective silicon epitaxial growth layer 113 and n type diffusion wiring layer 108.

Referring to FIG. 40, a conductive film (not shown) is formed on silicon nitride film 120 so as to fill opening 132. A predetermined photoresist pattern (not shown) is formed on the conductive film. Using the photoresist pattern as a mask, anisotropic etching is performed on the conductive film to form an opening 1 exposing the surface of silicon oxide film 118.
33 are formed. Thereby, the conductive film becomes the gate electrode 11.
It becomes 9. Thereafter, a predetermined metal film (not shown) is formed on gate electrode 119 so as to fill opening 133. A predetermined photoresist pattern (not shown) is formed on the metal film. Using the photoresist pattern as a mask, the metal film is anisotropically etched to form a metal wiring layer 129. Thus, the semiconductor device including the vertical MOS transistor shown in FIG. 34 is completed.

[0012]

A conventional semiconductor device including a vertical MOS transistor can be relatively easily formed by using the above-described manufacturing method. In the structure of this MOS transistor, as shown in FIG. 34, gate electrode 119 is also in contact with n ⁺ type selective silicon epitaxial growth layers 112 and 123 as source or drain regions with silicon oxide film 118 interposed therebetween.

In particular, when the gate electrode and the drain region approach each other, the electric field (fringe electric field) between the gate electrode and the drain region is strengthened, and the effective channel length is increased. That is, in this case, the p ⁻ type selective silicon epitaxial growth layer 113 as the channel region and the n ⁺ type selective silicon epitaxial growth layer 12 as the drain region
3 moves to the n ⁺ type selective silicon epitaxial growth layer 123 side. Therefore, as a result, the channel length becomes longer than the length corresponding to the thickness of p ⁻ type selective silicon epitaxial growth layer 113.

This means that the desired effective gate length cannot be obtained, which affects the operating speed of the MOS transistor. The channel length is a length corresponding to the thickness of the p ⁻ type selective silicon epitaxial growth layer 113, and the thickness is about 4000 ° in a semiconductor device based on a design rule of about 0.3 μm as in this structure. is there.
With such a thickness, it is considered that this effect can be ignored.

However, further miniaturization has progressed, and 0.
In a semiconductor device based on a design rule of about 15 μm, since the thickness of the p ⁻ -type selective silicon epitaxial growth layer 113 is further reduced, it is considered that this influence cannot be ignored. That is, the ratio of the increment of the channel length due to the fringe electric field becomes relatively large with respect to the length corresponding to the thickness of the p ⁻ -type selective silicon epitaxial growth layer 113 as the channel length. It will not be possible to do so.

Therefore, the structure of the conventional semiconductor device is
When applied to a semiconductor device having a design rule of about 0.15 μm, there is a problem that a desired operation speed of a vertical MOS transistor cannot be obtained.

The present invention has been made to solve the above-mentioned problem, and one object is to provide a semiconductor device including a MOS transistor capable of obtaining a desired operation speed. Is to provide a method for its manufacture.

[0018]

According to one aspect of the present invention, a semiconductor device includes a first impurity layer of a first conductivity type and a second impurity layer.
The semiconductor device includes a second impurity layer of a conductivity type, a third impurity layer of a first conductivity type, and a conductive layer. The first impurity layer is formed on a main surface of the semiconductor substrate. The second impurity layer includes a first impurity layer.
It is stacked on the impurity layer. The third impurity layer is stacked on the second impurity layer. The conductive layer is formed only on the side surface of the second impurity layer with an insulating layer interposed.

According to this structure, a transistor including the first and third impurity layers as the source or drain region, the second impurity layer as the channel region, and the conductive layer as the gate electrode is formed. The conductive layer is formed only on the side surface of the second impurity layer with the insulating layer interposed. Therefore, the electric field between the conductive layer and the first impurity layer or between the conductive layer and the third impurity layer is weakened. Thereby, the bonding surface between the first impurity layer and the second impurity layer moves toward the first impurity layer, or the bonding surface between the second impurity layer and the third impurity layer moves toward the third impurity layer. Thus, the effective channel length between the first impurity layer and the third impurity layer is suppressed from being longer than the length corresponding to the thickness of the second impurity layer. As a result, an increase in the effective channel length of the transistor is suppressed, and a semiconductor device having a desired operation speed can be obtained.

According to another aspect of the present invention, there is provided a field effect transistor including a source region including a first impurity layer of a first conductivity type, a channel region including a second impurity layer of a second conductivity type, and a first conductivity type. A drain region made of the third impurity layer, and a gate electrode. The source region is formed on the main surface of the semiconductor substrate. The channel region is stacked on the source region. The drain region is stacked on the channel region. The gate electrode is formed only on the side surface of the channel region with an insulating layer interposed.

According to this structure, the gate electrode of the field effect transistor is formed only on the side surface of the channel region with the insulating layer interposed. Therefore, the electric field between the gate electrode and the drain region is weakened. This allows
The junction surface between the channel region and the drain region moves to the drain region side, preventing the effective channel length between the drain region and the source region from becoming longer than the length corresponding to the thickness of the channel region. Is done. As a result, an increase in the effective channel length of the field-effect transistor is suppressed, and a field-effect transistor having a desired operation speed can be obtained.

Preferably, a fourth impurity layer of a first conductivity type formed between the first impurity layer and the second impurity layer and having an impurity concentration lower than that of the first impurity layer; And a fifth impurity layer of the first conductivity type having a lower impurity concentration than the third impurity layer.

In this case, the electric field between the first impurity layer and the second impurity layer is reduced by the fourth impurity layer, and the electric field between the second impurity layer and the third impurity layer is reduced by the fifth impurity layer. The electric field is reduced. Thereby, generation of hot electrons is suppressed, and the electrical characteristics of the semiconductor device are improved.

Preferably, the semiconductor substrate is a silicon single crystal substrate, and the first to fifth impurity layers contain silicon or a silicon germanium alloy.

In this case, the first to fifth impurity layers can be selectively and easily formed on the semiconductor substrate by the epitaxial growth method.

A method of manufacturing a semiconductor device according to still another aspect of the present invention includes the following steps. A first insulating film is formed on a main surface of a semiconductor substrate. A first opening exposing the surface of the semiconductor substrate is formed in the first insulating film. A first conductivity type first impurity layer is formed in the first opening. A second conductivity type second impurity layer is formed on the first impurity layer. A conductive layer is formed over the first insulating film with the second insulating film interposed therebetween so as to cover the side surface and the upper surface of the second impurity layer. The second insulating film and the conductive layer are left only on the side surfaces of the second impurity layer. A third insulating film is formed so as to cover the conductive layer, the second insulating film, and the second impurity layer. For the third insulating film,
A second opening exposing the surface of the second impurity layer is formed.
A third impurity layer of the first conductivity type is formed in the second opening.

According to this manufacturing method, a transistor including the first and third impurity layers as the source or drain region, the second impurity layer as the channel region, and the conductive layer as the gate electrode is formed. The conductive layer is the second
It is formed only on the side surface of the second impurity layer with the insulating layer interposed. Therefore, the electric field between the conductive layer and the first impurity layer or between the conductive layer and the third impurity layer is weakened. Thereby, the bonding surface between the first impurity layer and the second impurity layer moves toward the first impurity layer, or the bonding surface between the second impurity layer and the third impurity layer moves toward the third impurity layer. Then, the effective channel length between the first impurity layer and the third impurity layer becomes
It is suppressed that the length becomes longer than the length corresponding to the thickness of the second impurity layer. As a result, an increase in the effective channel length of the transistor is suppressed, and a semiconductor device having a desired operation speed can be manufactured.

Preferably, a step of forming a fourth impurity layer of a first conductivity type having an impurity concentration lower than that of the first impurity layer between the first impurity layer and the second impurity layer; Forming a fifth impurity layer of the first conductivity type having an impurity concentration lower than that of the third impurity layer between the first impurity layer and the second impurity layer.

In this case, the electric field between the first impurity layer and the second impurity layer is reduced by the fourth impurity layer.
Further, the electric field between the second impurity layer and the third impurity layer is reduced by the fifth impurity layer. Accordingly, generation of hot electrons is suppressed, and a semiconductor device having excellent electrical characteristics can be manufactured.

Preferably, the step of forming the first to fifth impurity layers using a silicon single crystal substrate as a semiconductor substrate includes a step of epitaxially growing silicon or a silicon germanium alloy.

In this case, the first to fifth impurity layers can be selectively and easily formed by the silicon epitaxial growth method.

Preferably, the method further includes the step of etching the semiconductor substrate exposed at the bottom of the first opening and the second impurity layer exposed at the bottom of the second opening.

In this case, when the first and second openings are formed, crystal defects and the like generated in the semiconductor substrate and the second impurity layer are removed by etching. Thus, a semiconductor device in which a leak current or the like at a junction portion such as a junction between the semiconductor substrate and the first impurity layer is reduced can be easily manufactured.

Preferably, the step of forming each of the first to fifth impurity layers includes a step of implanting an impurity of the first conductivity type or the second conductivity type by an ion implantation method.

In this case, after a silicon or silicon germanium alloy containing no impurity of a predetermined conductivity type is epitaxially grown in advance, a predetermined first conductivity type or second conductivity type impurity is removed by a photoresist pattern or the like. By introduction, first to fifth impurity layers are formed. For this reason, especially when forming a semiconductor device including a complementary transistor, each impurity layer can be formed more easily as compared with the case where silicon or a silicon germanium alloy containing impurities of a predetermined conductivity type is formed from the beginning. be able to.

[0036]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 A semiconductor device including a vertical MOS transistor as a field effect transistor according to Embodiment 1 of the present invention will be described with reference to the drawings. Referring to FIG. 1, a p-type well 7 having a concentration of 10 ¹⁵ to 10 ¹⁶ / cm ³ is formed on the main surface of silicon substrate 1. On the surface of the p-type well 7, an n-type diffusion wiring layer 8 having a concentration of 10 ¹⁹ to 10 ²⁰ / cm ^{3 serving as} a wiring is formed. The p-type well 7 is electrically insulated from other regions by the isolation oxide film 2 formed by the trench isolation method.

An n ⁺ -type selective silicon epitaxial growth layer 1 as a first impurity layer having a concentration of 10 ²⁰ / cm ³ electrically connected to an n-type diffusion wiring layer 8 on a silicon substrate 1.
2 are formed. On the silicon substrate 1 so as to fill the n ⁺ type selective silicon epitaxial growth layer 12,
A silicon nitride film 9 is formed.

On the n ⁺ type selective silicon epitaxial growth layer 12, a p ⁻ type selective silicon epitaxial growth layer 13 as a second impurity layer having a concentration of 10 ¹⁶ to 10 ¹⁷ / cm ³ is formed. Only on the side surface of the p ⁻ type selective silicon epitaxial growth layer 13, the gate insulating film 18 is formed.
, A gate electrode 19 is formed. On the gate electrode 19, a silicon nitride film 20 is formed. On the p ^- type selective silicon epitaxial growth layer 13, n ⁺ as a third impurity layer having a concentration of 10 ²⁰ / cm ³ is provided.
A type-selective silicon epitaxial growth layer 23 is formed. A silicon oxide film 27 is formed so as to cover silicon nitride film 20. On the silicon oxide film 27, a metal wiring layer 29 electrically connected to the n ⁺ type selective silicon epitaxial growth layer 23 is formed.

In this structure, the n ⁺ type selective silicon epitaxial growth layer 1 as a source or drain region
2, 23, a vertical MOS transistor including ap ⁻ type selective silicon epitaxial growth layer 13 as a channel region and a gate electrode 19 is formed. The gate electrode 1
Reference numeral 9 is formed only on the side surface of the p ⁻ type selective silicon epitaxial growth layer 13 with the gate insulating film 18 interposed therebetween.

Thus, the electric field (fringe electric field) between the gate electrode 19 and the n ⁺ type selective silicon epitaxial growth layer 12 or between the gate electrode 19 and the n ⁺ type selective silicon epitaxial growth layer 23 is reduced. Therefore, the n ⁺ type selective silicon epitaxial growth layer 12 and the p ⁻ type selective silicon epitaxial growth layer 13
Move to the n ⁺ -type selective silicon epitaxial growth layer 12 side bonding surface with, or, p ^- -type selective silicon epitaxial growth layer 13 and the bonding surface n ⁺ -type selective silicon epitaxial growth layer and the n ⁺ -type selective silicon epitaxial growth layer 23 Movement to the 23 side is suppressed.

Thus, the effective channel length between the n ⁺ -type selective silicon epitaxial growth layer 12 and the n ⁺ -type selective silicon epitaxial growth layer 23 is larger than the length corresponding to the thickness of the p ⁻ -type selective silicon epitaxial growth layer 13. Is also suppressed from becoming longer. As a result, 0.1
In order to cope with the design rule of about 5 μm, even if the thickness of the p ⁻ type selective silicon epitaxial growth layer 13 as the channel region becomes, for example, about 1000 to 2000 °, the effective channel of the vertical MOS transistor is reduced. An increase in length is suppressed, and a semiconductor device having a desired operation speed can be obtained.

Second Embodiment A semiconductor device according to a second embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIG. FIG. 2 shows a cross section taken along the line AA shown in FIG.

Referring to FIGS. 2 and ^3, a p-type well 7 having a concentration of 10 ¹⁵ to 10 ¹⁶ / cm ³ is formed on the main surface of silicon substrate 1. Further, the concentration is 10 ¹⁵ to 10 ¹⁶ / c.
An n-type well 4 of m ³ is formed. The p-type well 7 and the n-type well 4 are electrically insulated from each other by the isolation oxide film 2. On the surface of the p-type well 7, an n-type diffusion wiring layer 8 serving as a wiring layer is formed. On the n-type diffusion wiring layer 8, n having a thickness of about 500 ° and a concentration of 10 ²⁰ / cm ^{3
A +} type selective silicon epitaxial growth layer 12 is formed. Further, a silicon nitride film 9 having substantially the same thickness is formed so as to fill the n ⁺ -type selective silicon epitaxial growth layer 12.

On the n ⁺ type selective silicon epitaxial growth layer 12, a thickness of about 1500 ° and a concentration of 10 ¹⁶ to 10 ¹⁷
/ Cm ³ p ^- type selective silicon epitaxial growth layer 1
3 are formed. On the silicon nitride film 9, a gate electrode 19a is formed. The gate electrode 19a
Is in contact only with the side surface of the p ⁻ type selective silicon epitaxial growth layer 13 via the gate insulating film 18a. p
^{On the −} type selective silicon epitaxial growth layer 13, an n ⁺ type selective silicon epitaxial growth layer 23 having a thickness of about 500 ° and a concentration of 10 ²⁰ / cm ³ is formed.

On the other hand, a wiring layer is formed on the surface of the n-type well 4.
P type diffusion wiring layer 5 is formed. Its p-type expansion
A thickness of about 500 ° and a concentration of 10²⁰/ Cm^Three
P ⁺Forming type selective silicon epitaxial growth layer 16
Have been. That p⁺Type selective silicon epitaxial growth
On the long layer 16, a thickness of about 1500 ° and a concentration of 10¹⁶-10 ¹⁷
/ Cm^ThreeN^-Type selective silicon epitaxial growth layer 1
7 are formed. A gate electrode is formed on the silicon nitride film 9.
A pole 19b is formed. The gate electrode 19b is
N through the insulating film 18b.^-Type selection silicon epitaxy
It is in contact only on the side surface of the char growth layer 17. Gate power
A silicon nitride film 20 is formed to cover pole 19b.
ing.

On the n ⁻ -type selective silicon epitaxial growth layer 17, a thickness of about 500 ° and a concentration of 10 ²⁰ / cm ^{3 are provided.}
P ⁺ -type selective silicon epitaxial growth layer 26 is formed. Silicon oxide film 2 on silicon nitride film 20
1 is formed. On the silicon oxide film 21, a silicon oxide film 27 is further formed.

In the silicon oxide films 21 and 27 and the silicon nitride films 20 and 9, contact holes 55a exposing the surface of the n-type diffusion wiring layer 8 are formed. Further, a contact hole 55f exposing the surface of the p-type diffusion wiring layer 5 is formed. Contact holes 55b exposing the surface of the gate electrode 19a are formed in the silicon oxide films 27 and 21, and the silicon nitride film 20. Further, a contact hole 55e exposing the surface of the gate electrode 19b is formed.

In the silicon oxide film 27, a contact hole 55c exposing the surface of the n ⁺ type selective silicon epitaxial growth layer 27 is formed. Further, a contact hole 55d exposing the surface of the p ⁺ type selective silicon epitaxial growth layer 26 is formed. Metal wiring 5 is filled so as to fill contact holes 55a and 55b, respectively.
6a and 56b are formed respectively. A metal wiring 56c is formed to fill contact holes 55c and 55d. Metal wires 56d and 56e are formed to fill the contact holes 55e and 55f, respectively.

According to this structure, a semiconductor device including complementary MOS transistors (CMOS transistors) is formed. That is, in the region of the p-type well 7, an n-channel type vertical MOS transistor including the n ⁺ -type selective silicon epitaxial growth layers 12 and 23, the p ⁻ -type selective silicon epitaxial growth layer 13 and the gate electrode 19 a is formed. In the region of the n-type well 4, a p-channel type vertical MOS transistor including the p ⁺ -type selective silicon epitaxial growth layers 16 and 26, the n ⁻ -type selective silicon epitaxial growth layer 17 and the gate electrode 19 b is formed.

In an n-channel MOS transistor,
A gate electrode 19a is formed only on the side surface of p ^- type selective silicon epitaxial growth layer 13 as a channel region via gate insulating film 18a. On the other hand, in the p-channel type MOS transistor, the gate electrode 19 is formed only on the side surface of the n ⁻ type selective silicon epitaxial growth layer 17 as the channel region via the gate insulating film 18b.
b is formed.

Thus, as described in the first embodiment, in the n-channel type MOS transistor, between the gate electrode 19a and the n ⁺ type selective silicon epitaxial growth layer 12, or between the gate electrode 19a and n
⁺ Because the electric field between the type selective silicon epitaxial growth layer 23 (fringe field) is weakened, the effective channel length between the n ⁺ -type selective silicon epitaxial growth layer 12 and the n ⁺ -type selective silicon epitaxial growth layer 23 is, p ^- length corresponding to the thickness of the mold selective silicon epitaxial growth layer 13 (in this case, 1500 Å) is suppressed to be longer than.

In a p-channel type MOS transistor, an electric field (fringe) between gate electrode 19b and p ⁺ type selective silicon epitaxial growth layer 16 or between gate electrode 19b and p ⁺ type selective silicon epitaxial growth layer 26 is formed. Since the electric field is weakened, the effective channel length between the p ⁺ type selective silicon epitaxial growth layer 16 and the p ⁺ type selective silicon epitaxial growth layer 26 is a length corresponding to the thickness of the n ⁻ type selective silicon epitaxial growth layer 17. (In this case, 1500 °).

As a result, even with a design rule of about 0.15 μm, an increase in the effective channel length of the CMOS transistor is suppressed, and a semiconductor device having a desired operation speed can be obtained.

Third Embodiment A method of manufacturing a semiconductor device according to a third embodiment of the present invention will be described.
And a method of manufacturing the semiconductor device described in the second embodiment.
An example of the method will be described with reference to the drawings. First, refer to FIG.
Light, the surface of the silicon substrate 1 is
An isolation oxide film 2 is formed. Next, referring to FIG.
Photoresist on one region sandwiched by oxide film 2
Form 3 is formed. Using the photoresist 3 as a mask
Energy 50-150 KeV, dose 1 × 10¹²
~ 1 × 10¹³/ Cm^TwoTo implant phosphorus ions at
Than 10^Fifteen-10¹⁶/ Cm^ThreeForming n-well 4
I do. Thereafter, the energy is 10 to 50 KeV and the dose is 1
× 10^Fifteen~ 5 × 10^Fifteen/ Cm ^TwoImplant boron ions at
Thereby, the p-type diffusion wiring layer 5 is formed. That
Thereafter, the photoresist 3 is removed.

Next, referring to FIG. 6, a photoresist 6 is formed on the other region sandwiched between isolation oxide films 2. Using the photoresist 6 as a mask, the energy 5
0-100 KeV, dose 1 × 10 ¹² -1 × 10 ¹³ /
By implanting boron ions in cm ² , a p-type well 7 is formed. After that, the energy is 10-50 Ke
The n-type diffusion wiring layer 8 is formed by implanting phosphorus ions at V and a dose of 1 × 10 ^{15 to} 5 × 10 ¹⁵ / cm ² . Next, referring to FIG. 7, the photoresist is removed.

Next, referring to FIG. 8, the p-type diffusion wiring layer 5 and the n-type diffusion wiring layer 8 are covered by a CVD method so as to cover them.
A silicon nitride film 9 having a thickness of about 500 ° is formed. Next, referring to FIG. 9, a silicon oxide film 10 is formed on silicon nitride film 9. A photoresist 11 is formed on the silicon oxide film 10. Using the photoresist 11 as a mask, the silicon oxide film 10 is anisotropically etched to form an opening 50 exposing the surface of the n-type diffusion wiring layer 8. After that, the photoresist 11 is removed.

Referring to FIG. 10, disilane (Si ₂ H ₆ ) and phosphine (PH ₃ ) were introduced under the conditions of a silicon substrate temperature of 750 ° C. and a pressure of 10 ⁻³ Torr (hereinafter, these conditions are referred to as “conditions”). A "), a thickness of about 500 ° and a concentration of 10 ²⁰ / cm are formed on the n-type diffusion wiring layer 8.
The ^third n ⁺ -type selective silicon epitaxial growth layer 12 is epitaxially grown. It is desirable that the thickness of the n ⁺ -type selective silicon epitaxial growth layer 12 be substantially the same as the thickness of the silicon nitride film 9. Thereafter, at a silicon substrate temperature of 750 ° C. and a pressure of 10 ⁻³ Torr, disilane and diborane (B ₂ H ₆ ) are introduced (hereinafter, these conditions are referred to as “condition B”) to obtain a thickness of about 1500.
{Circle around ( ³⁾ }, a p ⁻ -type selective silicon epitaxial growth layer 13 having a concentration of 10 ¹⁶ to 10 ¹⁷ / cm ³ is epitaxially grown.

Next, referring to FIG. 11, silicon oxide film 1
Further, a silicon oxide film 14 is formed on zero. On the silicon oxide film 14, a photoresist 15 is formed. Using the photoresist 15 as a mask, the silicon oxide films 14 and 10 and the silicon nitride film 9 are anisotropically etched to form openings 51 exposing the surface of the p-type diffusion wiring layer 5. Next, referring to FIG. 12, under the condition B, on the p-type diffusion wiring layer 5, a thickness of about 500.degree.
A p ⁺ -type selective silicon epitaxial growth layer 16 of ²⁰ / cm ³ is epitaxially grown. Under the condition A, an n ⁻ -type selective silicon epitaxial growth layer 17 having a thickness of about 1500 ° and a concentration of 10 ¹⁶ to 10 ¹⁷ / cm ³ is epitaxially grown on the p ⁺ -type selective silicon epitaxial growth layer 16.

Next, referring to FIG. 13, silicon oxide film 1
4, 10 are removed. Next, referring to FIG.
By performing an oxidation treatment in a steam atmosphere at 0 ° C., a silicon oxide film 18 as a gate insulating film having a thickness of 60 to 80 ° is formed. Next, referring to FIG. 15, a polysilicon film 19 is formed on silicon nitride film 9 so as to cover silicon oxide film 18. At this time, the polysilicon film 19 has a thickness of the p ⁻ type selective silicon epitaxial growth layer 13.
Alternatively, it is desirable that the thickness of the n ⁻ -type selective silicon epitaxial growth layer 17 be substantially the same as
Desirably, it is 500 °. The polysilicon film 1
9, a photoresist 52 is formed. Next, referring to FIG. 16, anisotropic etching is performed on polysilicon film 19 using photoresist 52 shown in FIG.
Gate electrodes 19a and 19b are formed.

Referring to FIG. 17, gate insulating films 18 a and 18 b are formed by removing silicon oxide film 18 on p ⁻ type selective silicon epitaxial growth layer 13 and n ⁻ type selective silicon epitaxial growth layer 17. . Thereafter, a silicon nitride film 20 is formed so as to cover the gate electrodes 19a and 19b. Next, referring to FIG. 18, a silicon oxide film 21 is formed on silicon nitride film 20. Next, referring to FIG.
A photoresist 22 is formed thereon. Using the photoresist 22 as a mask, the silicon oxide film 21 is anisotropically etched to form an opening 53 exposing the surface of the p ⁻ -type selective silicon epitaxial growth layer 13.

Next, referring to FIG.
^{On the} -type selective silicon epitaxial growth layer 13, an n ⁺ -type selective silicon epitaxial growth layer 23 having a thickness of about 500 ° and a concentration of 10 ²⁰ / cm ³ is epitaxially grown. It is desirable that the thickness of the n ⁺ -type selective silicon epitaxial growth layer 23 be substantially the same as the thickness of the silicon nitride film 20.

Next, referring to FIG. 21, silicon oxide film 2
1, a silicon oxide film 24 is formed. A photoresist 25 is formed on the silicon oxide film 24. Using the photoresist 25 as a mask, the silicon oxide film 2
An opening 5 exposing the surface of n ⁻ -type selective silicon epitaxial growth layer 17 by performing anisotropic etching on
4 is formed. After that, the photoresist 25 is removed. Next, referring to FIG. 22, under the condition B, on the n ⁻ -type selective silicon epitaxial growth layer 17, a thickness of about 500
( ⁴⁾ A p ⁺ -type selective silicon epitaxial growth layer 26 having a concentration of 10 ²⁰ / cm ³ is epitaxially grown. After that, the silicon oxide film 24 is removed.

Referring to FIG. 23, silicon oxide film 2
On top of this, a silicon oxide film 27 is further formed. Next, referring to FIG. 24, a photoresist 28 is formed on silicon oxide film 27. Using the photoresist 28 as a mask, the silicon oxide films 27 and 21 and the silicon nitride film 9 are anisotropically etched to expose the surface of the n-type diffusion wiring layer 8 or the p-type diffusion wiring layer 5 to the contact hole 55a. , 55f, respectively. Also,
By performing anisotropic etching on silicon oxide films 27 and 21 and silicon nitride film 20, contact holes 55b and 55e exposing the surface of gate electrode 19 are formed, respectively. By performing anisotropic etching on silicon oxide film 27, contact holes 55 exposing the surface of n ⁺ -type selective silicon epitaxial growth layer 23 or p ⁺ -type selective silicon epitaxial growth layer 26 are exposed.
c and 55d are respectively formed. After that, the photoresist 28 is removed.

Next, referring to FIG. 25, metal wirings 56a, 56b, 56f are filled so as to fill contact holes 55a, 55b, 55c, 55d, 55e, 55f, respectively.
c, 56d and 56e are formed. Thus, the semiconductor device shown in FIG. 2 is completed.

According to the above-described manufacturing method, a silicon substrate is used as a semiconductor substrate, and n ⁺ , p ⁻ , p ⁺ and n ⁻ type selective silicon epitaxial growth layers 12, 23, 13, 16, 26, and 17 are formed by epitaxial growth. Was formed. Thereby, each selective silicon epitaxial growth layer can be selectively and easily formed at a predetermined location.

The gate electrode 19a is formed only on the side surface of the p ^- type selective silicon epitaxial growth layer 13 via the gate insulating film 18a. Also,
Gate electrode 19b is formed only on the side surface of n ⁻ -type selective silicon epitaxial growth layer 17 via gate insulating film 18b. Thus, the second embodiment
As described in the above, even with a design rule of about 0.15 μm, an increase in the effective channel length of the CMOS transistor is suppressed, and a semiconductor device having a desired operation speed can be manufactured.

Fourth Embodiment As an example of a method of manufacturing a semiconductor device according to a fourth embodiment of the present invention, a method of manufacturing a semiconductor device including a MOS transistor having an LDD structure will be described with reference to the drawings. First,
The steps up to the step shown in FIG. 26 are the same as the steps shown in FIGS. 4 to 9 described in the third embodiment, and a detailed description thereof will be omitted. In this case, the thickness of silicon nitride film 9 is desirably about 1000 °. Next, referring to FIG. 27, under conditions A, an n ⁺ -type selective silicon epitaxial growth layer 12 having a thickness of about 500 ° and a concentration of 10 ²⁰ / cm ³ is formed on n-type diffusion wiring layer 8. Under the condition A, an n ⁻ -type selective silicon epitaxial growth layer 30 having a thickness of about 500 ° and a concentration of 10 ¹⁷ / cm ³ is formed on the n ⁺ -type selective silicon epitaxial growth layer 12. That n
^A thickness of about 1500 ° and a concentration of 10 ¹⁶ to 10 ¹⁷ / c on the type-selective silicon epitaxial growth layer 30 under the condition B;
An m ³ p ^- type selective silicon epitaxial growth layer 13 is formed.

Referring to FIG. 28, silicon oxide film 1
Further, a silicon oxide film 14 is formed on zero. A photoresist 15 is formed on the silicon oxide film 14.
Using the photoresist 15 as a mask, the silicon oxide films 14 and 10 and the silicon nitride film 9 are subjected to anisotropic etching, and the opening 5 exposing the surface of the p-type
Form one.

Next, referring to FIG.
The thickness is about 500 ° and the concentration is 10 ²⁰ / c on the diffusion wiring layer 5
An m ³ p ⁺ type selective silicon epitaxial growth layer 16 is formed. On condition that the p ⁺ type selective silicon epitaxial growth layer 16 has a thickness of about 500
A p ^- type selective silicon epitaxial growth layer 31 of ¹⁷ / cm ³ is formed. On the p ⁻ type selective silicon epitaxial growth layer 31, under the condition A, a thickness of about 1500 °
An n ⁻ -type selective silicon epitaxial growth layer 17 having a concentration of 10 ¹⁶ to 10 ¹⁷ / cm ³ is formed.

Thereafter, the same processes as those shown in FIG. 12 to the process shown in FIG. 19 described in the third embodiment are performed up to the process shown in FIG. After that, the photoresist 22 is removed. Next, referring to FIG. 31, on the p ⁻ type selective silicon epitaxial growth layer 13, under the condition A,
An n ⁻ -type selective silicon epitaxial growth layer 32 having a thickness of about 500 ° and a concentration of 10 ¹⁷ / cm ³ is formed. Under the condition A, an n ⁺ -type selective silicon epitaxial growth layer 23 having a thickness of about 500 ° and a concentration of 10 ²⁰ / cm ³ is formed on the n ^-- type selective silicon epitaxial growth layer 32.

Referring to FIG. 32, a silicon oxide film 24 is further formed on silicon oxide film 21. A photoresist 25 is formed on the silicon oxide film 24. Using the photoresist 25 as a mask, the silicon oxide films 24 and 21 are anisotropically etched to form openings 54 exposing the surface of the n ⁻ -type selective silicon epitaxial growth layer 17. After that, the photoresist 25 is removed.

Referring to FIG. 33, p ^- type selective silicon epitaxial growth layer 33 having a thickness of about 500 ° and a concentration of 10 ¹⁷ / cm ³ is formed on n ⁻ type selective silicon epitaxial growth layer 17 under condition B. . Under the condition B, a p ⁺ -type selective silicon epitaxial growth layer 26 having a thickness of about 500 ° and a concentration of 10 ²⁰ / cm ³ is formed on the p ^-- type selective silicon epitaxial growth layer 33. Thereafter, by performing the same processing as the steps shown in FIGS. 23 to 25 described in the third embodiment, a semiconductor device having a MOS transistor having an LDD structure is completed.

According to this semiconductor device, the electric field between the p ⁻ type selective silicon epitaxial growth layer 13 and the n ⁺ type selective silicon epitaxial growth layer 12 is reduced by the n ⁻ type selective silicon epitaxial growth layer 30. Further, the electric field between the p ⁻ type selective silicon epitaxial growth layer 13 and the n ⁺ type selective silicon epitaxial growth layer 23 is reduced by the n ⁻ type selective silicon epitaxial growth layer 32. Furthermore, the electric field between the n ⁻ type selective silicon epitaxial growth layer 17 and the p ⁺ type selective silicon epitaxial growth layer 16 is reduced by the p ⁻ type selective silicon epitaxial growth layer 31. Furthermore, the electric field between the n ⁻ type selective silicon epitaxial growth layer 17 and the p ⁺ type selective silicon epitaxial growth layer 26 is reduced by the p ⁻ type selective silicon epitaxial growth layer 33.

As a result, in the n-channel and p-channel MOS transistors, generation of hot electrons is suppressed, and the electrical characteristics are improved.

In the third or fourth embodiment, immediately after forming the opening 50 in the step shown in FIG.
In the step shown in ( ¹ ), an n ⁺ type selective silicon epitaxial growth layer 12 was formed. Immediately after forming the opening 53 in the step shown in FIG. 19, the n ⁺ -type selective silicon epitaxial growth layer 23 was formed in the step shown in FIG. Further, in the step shown in FIG.
Immediately after the formation, a p ⁺ -type selective silicon epitaxial growth layer 16 was formed in the step shown in FIG. Immediately after forming the opening 54 in the step shown in FIG. 21, the p ⁺ -type selective silicon epitaxial growth layer 26 was formed in the step shown in FIG.

In these cases, the n-type diffusion wiring layer 8, the p-type diffusion wiring layer 5, the p ⁻ type selective silicon epitaxial growth layer 13 and the n ⁻ type selective silicon epitaxial growth are formed by etching when forming the openings 51 to 54. Layer 1
The surface of 7 is easily damaged by crystal defects and the like. Therefore, immediately after forming the openings 51 to 54, the n-type diffusion wiring layer 8, the p-type diffusion wiring layer 5, the p ⁻ -type selective silicon epitaxial growth layer 13, and the n ⁻ -type selective silicon The surface of the epitaxial growth layer 17 may be appropriately etched to remove a damaged layer such as a crystal defect. In that case, it is possible to reduce a leak current or the like at each joint surface.

Although the selective silicon epitaxial growth layer of a predetermined conductivity type is formed as a source region, a drain region or a channel region, a silicon germanium alloy may be selectively epitaxially grown.

Further, after selectively epitaxially growing silicon or a silicon germanium alloy containing no impurity of a predetermined conductivity type, an impurity of a predetermined conductivity type may be added by ion implantation. In this case, each selective silicon epitaxial growth layer is formed by introducing impurities of a predetermined conductivity type using a photoresist pattern or the like as a mask. For this reason, in particular, when forming the semiconductor device including the complementary MOS transistor described in the second embodiment, each of the semiconductor devices is more easily compared with the case where a selective silicon epitaxial growth layer of a predetermined conductivity type is formed from the beginning. A selective silicon epitaxial growth layer can be formed.

Further, the source region, drain region or channel region is not limited to an epitaxially grown layer of silicon or a silicon-germanium alloy, but may be an impurity layer of a predetermined conductivity type obtained by another method.

Although a polysilicon film is used as the gate electrodes 19, 19a and 19b, a silicide film such as tungsten silicide, a two-layer film of tungsten and polysilicon or a metal film may be used. Good. In particular, an n-channel transistor has n
Alternatively, a polysilicon film to which a p-type impurity is added may be used, and a polysilicon film to which a p-type impurity is added may be applied to a p-type transistor.

The embodiments disclosed this time are to be considered in all respects as illustrative and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the range described above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

[0082]

According to the semiconductor device of one aspect of the present invention, a transistor including first and third impurity layers as source or drain regions, a second impurity layer as a channel region, and a conductive layer as a gate electrode Is configured. The conductive layer is formed only on the side surface of the second impurity layer with the insulating layer interposed. Therefore, the electric field between the conductive layer and the first impurity layer or between the conductive layer and the third impurity layer is weakened. Thereby, the bonding surface between the first impurity layer and the second impurity layer moves to the first impurity layer side,
Alternatively, the bonding surface between the second impurity layer and the third impurity layer is
Moving to the impurity layer side, the effective channel length between the first impurity layer and the third impurity layer is suppressed from becoming longer than the length corresponding to the thickness of the second impurity layer. As a result, an increase in the effective channel length of the transistor is suppressed, and a semiconductor device having a desired operation speed can be obtained.

According to the field-effect transistor in another aspect of the present invention, the gate electrode of the field-effect transistor is formed only on the side surface of the channel region with the insulating layer interposed. Therefore, the electric field between the gate electrode and the drain region is weakened. Thereby, the junction surface between the channel region and the drain region moves toward the drain region, and the effective channel length between the drain region and the source region becomes longer than the length corresponding to the thickness of the channel region. Is suppressed. As a result, an increase in the effective channel length of the field-effect transistor is suppressed, and a field-effect transistor having a desired operation speed can be obtained.

Preferably, a fourth impurity layer of the first conductivity type formed between the first impurity layer and the second impurity layer and having an impurity concentration lower than that of the first impurity layer; A first conductivity type fifth impurity layer having a lower impurity concentration than the third impurity layer formed between the first impurity layer and the second impurity layer; Is relaxed by the fourth impurity layer, and the electric field between the second impurity layer and the third impurity layer is relaxed by the fifth impurity layer. Thereby, generation of hot electrons is suppressed, and the electrical characteristics of the semiconductor device are improved.

Preferably, the semiconductor substrate is a silicon single crystal substrate, and the first to fifth impurity layers contain silicon or a silicon germanium alloy.
The first to the first on the semiconductor substrate by the epitaxial growth method
The fifth impurity layer can be selectively and easily formed.

According to the method of manufacturing a semiconductor device in still another aspect of the present invention, the first and third impurity layers as source or drain regions, the second impurity layer as a channel region, and the conductive layer as a gate electrode are formed. A transistor is formed. The conductive layer is formed only on the side surface of the second impurity layer with the second insulating layer interposed. Therefore, the electric field between the conductive layer and the first impurity layer or between the conductive layer and the third impurity layer is weakened. Thereby, the bonding surface between the first impurity layer and the second impurity layer moves toward the first impurity layer, or the bonding surface between the second impurity layer and the third impurity layer moves toward the third impurity layer. Then, the first impurity layer and the third
The effective channel length with the impurity layer is suppressed from becoming longer than the length corresponding to the thickness of the second impurity layer. As a result, an increase in the effective channel length of the transistor is suppressed, and a semiconductor device having a desired operation speed can be manufactured.

Preferably, a step of forming a fourth impurity layer of a first conductivity type having an impurity concentration lower than that of the first impurity layer between the first impurity layer and the second impurity layer; Forming a first impurity-type fifth impurity layer having an impurity concentration lower than that of the third impurity layer between the second impurity layer and the second impurity layer, thereby forming a fourth impurity layer. The electric field between the first impurity layer and the second impurity layer is reduced. In addition, a fifth impurity layer is formed, and an electric field between the second impurity layer and the third impurity layer is reduced. Accordingly, generation of hot electrons is suppressed, and a semiconductor device having excellent electrical characteristics can be manufactured.

Preferably, the step of forming the first to fifth impurity layers using a silicon single crystal substrate as the semiconductor substrate includes the step of epitaxially growing silicon or a silicon-germanium alloy. Five impurity layers can be selectively and easily formed.

Preferably, the method further includes the step of etching the semiconductor substrate exposed at the bottom of the first opening and the second impurity layer exposed at the bottom of the second opening.
When the first and second openings are formed, crystal defects and the like generated in the semiconductor substrate and the second impurity layer are removed by etching. Thereby, the semiconductor substrate and the first
It is possible to easily manufacture a semiconductor device in which a leakage current or the like at a junction portion such as a junction with an impurity layer is reduced.

Preferably, the step of forming each of the first to fifth impurity layers includes a step of implanting an impurity of the first conductivity type or the second conductivity type by an ion implantation method. After epitaxially growing silicon or silicon germanium alloy that does not contain impurities of the conductivity type, by a photoresist pattern, etc.
The first to fifth impurity layers are formed by introducing a predetermined first conductivity type or second conductivity type impurity. For this reason, especially when forming a semiconductor device including a complementary transistor, each impurity layer can be formed more easily as compared with the case where silicon or a silicon germanium alloy containing impurities of a predetermined conductivity type is formed from the beginning. be able to.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention;

FIG. 2 is a sectional view of a semiconductor device according to a second embodiment of the present invention;

FIG. 3 is a plan view of a semiconductor device according to a second embodiment of the present invention;

FIG. 4 is a cross-sectional view showing a step of a method for manufacturing a semiconductor device according to a third embodiment of the present invention.

FIG. 5 is a cross-sectional view showing a step performed after the step shown in FIG. 4 in the embodiment.

FIG. 6 is a cross-sectional view showing a step performed after the step shown in FIG. 5 in the embodiment.

FIG. 7 is a cross-sectional view showing a step performed after the step shown in FIG. 6 in the embodiment.

FIG. 8 is a cross-sectional view showing a step performed after the step shown in FIG. 7 in the embodiment.

FIG. 9 is a cross-sectional view showing a step performed after the step shown in FIG. 8 in the embodiment.

FIG. 10 is a cross-sectional view showing a step performed after the step shown in FIG. 9 in the embodiment.

FIG. 11 is a cross-sectional view showing a step performed after the step shown in FIG. 10 in the embodiment.

FIG. 12 is a cross-sectional view showing a step performed after the step shown in FIG. 11 in the embodiment.

FIG. 13 is a cross-sectional view showing a step performed after the step shown in FIG. 12 in the embodiment.

FIG. 14 is a cross-sectional view showing a step performed after the step shown in FIG. 13 in the embodiment.

FIG. 15 is a cross-sectional view showing a step performed after the step shown in FIG. 14 in the embodiment.

FIG. 16 is a cross-sectional view showing a step performed after the step shown in FIG. 15 in the embodiment.

FIG. 17 is a cross-sectional view showing a step performed after the step shown in FIG. 16 in the embodiment.

FIG. 18 is a cross-sectional view showing a step performed after the step shown in FIG. 17 in the embodiment.

FIG. 19 is a cross-sectional view showing a step performed after the step shown in FIG. 18 in the embodiment.

FIG. 20 is a cross-sectional view showing a step performed after the step shown in FIG. 19 in the embodiment.

FIG. 21 is a cross-sectional view showing a step performed after the step shown in FIG. 20 in Embodiment 1;

FIG. 22 is a cross-sectional view showing a step performed after the step shown in FIG. 21 in Embodiment 1;

FIG. 23 is a cross-sectional view showing a step performed after the step shown in FIG. 22 in the embodiment.

FIG. 24 is a cross-sectional view showing a step performed after the step shown in FIG. 23 in the embodiment.

FIG. 25 is a cross-sectional view showing a step performed after the step shown in FIG. 24 in the embodiment.

FIG. 26 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device according to the fourth embodiment of the present invention.

FIG. 27 is a cross-sectional view showing a step performed after the step shown in FIG. 26 in the embodiment.

FIG. 28 is a cross-sectional view showing a step performed after the step shown in FIG. 27 in the embodiment.

FIG. 29 is a cross-sectional view showing a step performed after the step shown in FIG. 28 in the embodiment.

FIG. 30 is a cross-sectional view showing a step performed after the step shown in FIG. 29 in the embodiment.

FIG. 31 is a cross-sectional view showing a step performed after the step shown in FIG. 30 in the embodiment.

FIG. 32 is a cross-sectional view showing a step performed after the step shown in FIG. 31 in the embodiment.

FIG. 33 is a cross-sectional view showing a step performed after the step shown in FIG. 32 in Embodiment 3;

FIG. 34 is a cross-sectional view of a conventional semiconductor device.

FIG. 35 is a cross-sectional view showing one step of a conventional method for manufacturing a semiconductor device.

FIG. 36 is a cross-sectional view showing a step performed after the step shown in FIG. 35.

FIG. 37 is a cross-sectional view showing a step performed after the step shown in FIG. 36.

FIG. 38 is a cross-sectional view showing a step performed after the step shown in FIG. 37.

FIG. 39 is a cross-sectional view showing a step performed after the step shown in FIG. 38.

40 is a cross-sectional view showing a step performed after the step shown in FIG. 39.

[Explanation of symbols]

1 silicon substrate, 2 isolation oxide film, 4 n-type well,
5 p-type diffusion wiring layer, 7 p-type well, 8 n-type diffusion wiring layer, 9 silicon nitride film, 12 n ⁺ type selective silicon epitaxial growth layer, 13 p ⁻ type selective silicon epitaxial growth layer, 16 p ⁺ type selective silicon epitaxial growth layer , 17 n ⁻ selective silicon epitaxial growth layer, 18 gate insulating film, 23 n ⁺ selective silicon epitaxial growth layer, 26 p ⁺ selective silicon epitaxial growth layer, 29 metal wiring layer, 30, 32
n ⁻ type selective silicon epitaxial growth layer, 31, 3
3p ^- type selective silicon epitaxial growth layer, 56a,
56b, 56c, 56d, 56e Metal wiring.

Claims (9)

[Claims] A first substrate formed on a main surface of the semiconductor substrate;
A first impurity layer of a conductivity type; a second impurity layer of a second conductivity type stacked on the first impurity layer; and a third impurity layer of the first conductivity type stacked on the second impurity layer. And a conductive layer formed only on a side surface of the second impurity layer with an insulating layer interposed therebetween. A first substrate formed on a main surface of the semiconductor substrate;
A source region formed of a first impurity layer of a conductivity type; a channel region formed of a second impurity layer of a second conductivity type stacked on the first impurity layer; and a first region stacked on the second impurity layer. A field-effect transistor comprising: a drain region formed of a conductive third impurity layer; and a gate electrode formed only on a side surface of the second impurity layer with an insulating layer interposed. 3. A first conductivity type fourth impurity layer formed between the first impurity layer and the second impurity layer and having an impurity concentration lower than that of the first impurity layer; 3. The semiconductor device according to claim 1, further comprising: a first conductivity type fifth impurity layer formed between the first impurity layer and the third impurity layer and having a lower impurity concentration than the third impurity layer. 4. 4. The semiconductor device according to claim 3, wherein said semiconductor substrate is a silicon single crystal substrate, and said first to fifth impurity layers contain silicon or a silicon germanium alloy. 5. A step of forming a first insulating film on a main surface of a semiconductor substrate; a step of forming a first opening exposing a surface of the semiconductor substrate in the first insulating film; Forming a first conductivity type first impurity layer in one opening; forming a second conductivity type second impurity layer on the first impurity layer; and forming a second conductivity type second impurity layer on the first insulating film. Forming a conductive layer with a second insulating film interposed therebetween so as to cover a side surface and a top surface of the second impurity layer; and forming the second insulating film and the conductive layer only on the side surface of the second impurity layer. Leaving a step; forming a third insulating film so as to cover the conductive layer, the second insulating film and the second impurity layer; and forming a surface of the second impurity layer on the third insulating film. Forming a second opening to be exposed; and a third impurity of a first conductivity type in the second opening. And a step of forming a layer, a method of manufacturing a semiconductor device. 6. a step of forming a fourth impurity layer of a first conductivity type having a lower impurity concentration than the first impurity layer, between the first impurity layer and the second impurity layer; 6. The method according to claim 5, further comprising: forming a fifth impurity layer of the first conductivity type having a lower impurity concentration than the third impurity layer between the third impurity layer and the second impurity layer. A method for manufacturing a semiconductor device. 7. The semiconductor device according to claim 6, wherein a single crystal silicon substrate is used as the semiconductor substrate, and the step of forming the first to fifth impurity layers includes a step of epitaxially growing silicon or a silicon germanium alloy. Manufacturing method. 8. The method according to claim 6, further comprising etching the semiconductor substrate exposed at the bottom of the first opening and the second impurity layer exposed at the bottom of the second opening. A method for manufacturing a semiconductor device. 9. The step of forming each of the first to fifth impurity layers includes the step of forming the first conductivity type or the second conductivity type by ion implantation.
9. The method for manufacturing a semiconductor device according to claim 7, further comprising a step of implanting a conductive type impurity.