KR100985107B1 - Method for Complete removal of trapped charges in the sourceor drain and bulk region of vertical transistors - Google Patents
Method for Complete removal of trapped charges in the sourceor drain and bulk region of vertical transistors Download PDFInfo
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- KR100985107B1 KR100985107B1 KR1020080078664A KR20080078664A KR100985107B1 KR 100985107 B1 KR100985107 B1 KR 100985107B1 KR 1020080078664 A KR1020080078664 A KR 1020080078664A KR 20080078664 A KR20080078664 A KR 20080078664A KR 100985107 B1 KR100985107 B1 KR 100985107B1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
Abstract
The present invention discloses a method for completely eliminating the vertical charge source (or drain) and trap charge in the bulk region that can significantly improve the switch characteristics of the vertical transistor and the performance of the vertical transistor.
The method according to the invention comprises the steps of: a) implanting an impurity for source / channel / drain formation in the front of the substrate and activating the impurity; b) forming a pillar or silicon pillar for forming a vertical transistor on the front surface of the wafer using a photoresist pattern and a dry etching method; c) depositing an oxide film on the entire surface of the substrate by a CVD method and planarization by a CMP method; d) etching back the oxide film on the front surface of the substrate by dry etching, growing the thermal oxide film to a suitable thickness on the front surface of the substrate, and then etching back until the drain terminal is exposed to form a gate electrode; ; e) depositing an oxide film or a nitride film, planarizing the region by a CMP process, and forming a contact hole; f) forming a contact metal by etchback and forming a metal layer using a photoresist pattern and a dry etching method.
Vertical, transistor, trap, charge, removal, impurity, etch back, contact metal
Description
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the fabrication of sig transistors, and more particularly, oxides are deposited on the entire surface of a substrate just before the formation of gate oxides, and the planarization of the oxide layers is carried out using a CMP process. An etchback using an easy-to-remove carbon film or an organic anti-reflective coating (ARC) film is used to trap the bulk (source or drain) and bulk portions of the vertical MOSFET. The present invention relates to a vertical transistor source (or drain) capable of completely eliminating trapped charges and a method for completely eliminating trap charge in a bulk region.
In general, various fabrication techniques are used to configure transistors, bit lines, and the like formed in semiconductor devices. Recently, a MOS type field effect transistor (MOS FET: Metal Oxide) is applied to form an oxide film on a silicon substrate to produce an electric field effect. Semiconductor Field Effect Transistors) are increasingly being used.
The MOS transistor is divided into a cell region and a peripheral circuit region to apply a process of forming a transistor, respectively. The MOS transistor is formed by stacking a gate insulating film and a gate conductive film on a silicon substrate. In this case, the gate conductive film is usually made of a polysilicon film or a laminated film of a polysilicon film and a metal-based film.
On the other hand, as the design rule of the semiconductor device is reduced, the semiconductor industry in recent years has moved toward improving the integration degree of the semiconductor device and increasing the operation speed and yield. Accordingly, a vertical transistor has been proposed to overcome the limitations in terms of the degree of integration and current of the semiconductor device of the conventional transistor.
The vertical transistor has a source / drain formed in the vertical direction of the gate and the gate, unlike a conventional transistor composed of a source / drain region formed in the gate and the substrate on both sides of the gate. It consists of an area to form a channel in the vertical direction.
However, the conventional vertical transistor manufacturing technology, unlike the planar transistor manufacturing, does not leave gate oxide and polysilicon only in the channel region of the transistor, but leaves oxide and polysilicon in the channel region, source (or drain), bulk region and field region. There is a problem.
Therefore, the vertical transistor has a severe weakness in the application of the vertical transistor because of its poor switch characteristics or poor transistor performance. At present, attempts have been made to minimize the width of the polysilicon gate electrode, but the process constraints are clear and there are still disadvantages in that charge traps in the source and bulk portions.
Solutions using the isolation between vertical and vertical transistors (eg LOCOS) have been proposed and studied, but they are not a complete solution. Therefore, despite the many advantages of the vertical transistor is a situation that acts as a big obstacle to the practical use or application.
The present invention was created to solve this problem, and an object of the present invention is to completely eliminate charges trapped in the source (or drain, source and drain) and bulk portions of a vertical MOSFET. A method is provided for completely removing the trap charge in the vertical transistor source (or drain) and bulk region.
Another object of the present invention is to apply an oxide thin film deposition technique, a CMP technique, and an etching technique immediately before the gate oxidation process without an additional photo mask, so that the polysilicon gate electrode is formed only in the channel region by proceeding in the conventional process sequence. The present invention provides a method for completely eliminating trap charge in a bulk region and a vertical transistor source (or drain) that can provide complete transistor characteristics.
In order to completely remove the trap charge in the vertical transistor source (or drain) and the bulk region according to the aspect of the present invention for achieving the above object, in the trap charge removal method in the vertical transistor process, a) the front of the substrate Implanting impurities into the source / channel / drain formation; b) activating the impurity using a rapid heat treatment process after the impurity implantation; c) forming a pillar or silicon pillar for forming a vertical transistor on the entire surface of the wafer by using a photoresist pattern and a dry etching method; d) depositing an oxide film on the entire surface of the substrate by a CVD method and wide area planarization by a CMP method; e) etching back the oxide film on the front surface of the substrate by dry etching; f) growing a thermal oxide film to an appropriate thickness on the entire surface of the substrate; g) depositing a gate polysilicon layer doped by a CVD method on the entire surface of the substrate and etching back to the step of exposing the drain terminal by dry etching; h) depositing an oxide film or a nitride film by a CVD method or an LPCVD method or a combination of both methods on the entire surface of the substrate, and wide-area planarization by a CMP process; i) forming a contact hole in the gate electrode / source / drain region using a photoresist pattern and a dry etching method; j) depositing and etchback a metal barrier film and a metal tungsten in the formed hole to form a contact metal; And k) depositing a metal layer for forming metal wiring on the entire surface of the substrate and forming a metal layer by using a photoresist pattern and a dry etching method.
In view of the technical effect, firstly, an overlap capacitance is completely removed in a source (or drain) region and a bulk region of a vertical transistor made by a conventional process, and secondly, switch characteristics of a vertical transistor. And the effect of greatly improving the performance of the vertical transistor. Thirdly, it provides the effect of completely adjusting transistor characteristics to make transistors exhibiting desired characteristics.
As the economic effect of the present invention, the vertical transistor technology is expanded and industrialized in more fields in the future due to the above-described technical effects, thereby providing enormous ripple effect directly and indirectly, and technology preoccupation effect by directly securing advanced technology and IP And market entry and market preoccupation effects.
Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
1 to 6 illustrate a process for removing trap charge in a vertical transistor source, drain, and bulk region according to a first embodiment of the present invention. 7 is a flowchart for explaining a process according to the first embodiment of the present invention.
As illustrated, in step S701, impurities for forming the source 2, the
For example, when the ion implantation method is used, it may be injected into the substrate by accelerating by applying a high voltage to ions such as B, As, and P separated in a vacuum state. As shown in FIG. 2, a vertical transistor forming pillar or silicon pillar 5 is formed on the entire wafer surface by using a photoresist pattern and a dry etching method.
In step S703, the trap charge in the source (or drain) region and the bulk region is removed through the method of forming an insulating layer, which deposits an
Thereafter, the process proceeds to step S705, and wide-area planarization through a CMP process for efficiently polishing the unnecessary thin film layer using a chemical or mechanical method as shown in FIG. In operation S707, after etching the oxide film on the entire surface of the wide area planarized substrate by dry etching, the gate electrode is formed in operation S709. As shown in FIG. 4, after the
In operation S711, when the
FIG. 8 shows another embodiment of a process for removing trap charge in a vertical transistor source (drain) chuck region according to the present invention. 9 is a flowchart illustrating a process description thereof.
In addition to the method of etching back the CVD oxide film to leave the oxide film by dry etching when the insulating layer is inserted before the thermal oxide film is formed, the wet etching method of the insertion layer removed by the etchback by distinguishing the insulating layer to be inserted and the type of insulating layer to be removed is performed. In addition, the vertical transistor formation method also implements CMOS by forming both NMOS and PMOS at once including STI for isolation between devices.
In the present invention, when only one type of NMOS or only one type of PMOS is made, not only a part of the present embodiment can be obtained, but also a thermal oxide film itself is not left on the drain surface of the filler.
First, the process proceeds to step S901 to form a
In operation S907, the
Subsequently, in operation S911, a nitride film (or an oxide film) 118 is deposited on the entire surface of the substrate including the N + source / drain layer (or P + source / drain layer), the NLDD layer (or PLDD layer), and the field oxide layer as shown in FIG. 8C. And planarized by the CMP process, and deposits the
In operation S919, epitaxially grow high quality silicon in the exposed silicon region to form a primary
In operation S929, the
Subsequently, through dry etching, the gate polysilicon is etched back to form a
In step S943, the wafer is rapidly heat-treated to activate implanted impurities, and in step S945, an oxide film is deposited on the entire surface of the wafer, and a
In step S951, as shown in FIG. 8E, the metal barrier layer and the metal tungsten are deposited and etched back into the oxide layer and the contact hole to form the
Therefore, as described above, the present invention is directed to the source (or drain) and bulk portions near the channel region when vertically implementing a silicon device having a minimum line width of less than a deep submicron. It is a technique that completely removes trapped charges. This is accomplished by chemical vapor deposition on the entire surface of the substrate immediately prior to gate oxide formation, wide area planarization by the CMP process, and etch-back of the oxide layer, thereby reducing the source (or drain) and bulk portions of the vertical MOSFET. By completely eliminating the trapped charges to fully implement the switch characteristics of the vertical transistor, it is expected to play a major role in the vertical transistor industrialization and application fields.
1 to 6 are diagrams illustrating a trap charge removing process according to a first embodiment of the present invention.
7 is a process flowchart according to the first embodiment of the present invention.
8A to 8E illustrate a trap charge removing process according to a second embodiment of the present invention.
9 is a process flowchart according to a second embodiment of the present invention.
<Explanation of symbols for main drawings>
11
13
15: filler 16: oxide layer
17
19: PMD oxide film 20: contact metal
21: pattern metal layer 111: substrate
112: field oxide film (STI) 113: photoresist pattern
114: N + source / drain region 115: NLDD layer
116: P + source / drain region 117: PLDD
118: nitride film 119: oxide film
120: primary epi silicon for NMOS 121: primary epi silicon for PMOS
122: gate oxide film 123: gate electrode
124: PMD1 oxide film 125-1: NMOS source / drain
125-2: PMOS source / drain 126: PMD2 oxide film
127: contact metal 128: pattern metal layer
Claims (11)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020080078664A KR100985107B1 (en) | 2008-08-11 | 2008-08-11 | Method for Complete removal of trapped charges in the sourceor drain and bulk region of vertical transistors |
| PCT/KR2009/002095 WO2010018912A1 (en) | 2008-08-11 | 2009-04-22 | Method for completely eliminating charge trap from the source (or drain) and the bulk region of a vertical transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020080078664A KR100985107B1 (en) | 2008-08-11 | 2008-08-11 | Method for Complete removal of trapped charges in the sourceor drain and bulk region of vertical transistors |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20100019909A KR20100019909A (en) | 2010-02-19 |
| KR100985107B1 true KR100985107B1 (en) | 2010-10-05 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020080078664A KR100985107B1 (en) | 2008-08-11 | 2008-08-11 | Method for Complete removal of trapped charges in the sourceor drain and bulk region of vertical transistors |
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| Country | Link |
|---|---|
| KR (1) | KR100985107B1 (en) |
| WO (1) | WO2010018912A1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10418271B2 (en) | 2014-06-13 | 2019-09-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of forming isolation layer |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11214684A (en) | 1998-01-26 | 1999-08-06 | Mitsubishi Electric Corp | Semiconductor device and its manufacture |
| KR20020076386A (en) * | 2001-03-28 | 2002-10-11 | 한국전자통신연구원 | Ultra small size vertical mosfet device and fabrication method of the mosfet device |
| KR100618875B1 (en) | 2004-11-08 | 2006-09-04 | 삼성전자주식회사 | Semiconductor memory device having vertical channel MOS transistor and method for manufacturing the same |
| US20070148939A1 (en) | 2005-12-22 | 2007-06-28 | International Business Machines Corporation | Low leakage heterojunction vertical transistors and high performance devices thereof |
-
2008
- 2008-08-11 KR KR1020080078664A patent/KR100985107B1/en not_active IP Right Cessation
-
2009
- 2009-04-22 WO PCT/KR2009/002095 patent/WO2010018912A1/en active Application Filing
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11214684A (en) | 1998-01-26 | 1999-08-06 | Mitsubishi Electric Corp | Semiconductor device and its manufacture |
| KR20020076386A (en) * | 2001-03-28 | 2002-10-11 | 한국전자통신연구원 | Ultra small size vertical mosfet device and fabrication method of the mosfet device |
| KR100618875B1 (en) | 2004-11-08 | 2006-09-04 | 삼성전자주식회사 | Semiconductor memory device having vertical channel MOS transistor and method for manufacturing the same |
| US20070148939A1 (en) | 2005-12-22 | 2007-06-28 | International Business Machines Corporation | Low leakage heterojunction vertical transistors and high performance devices thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2010018912A1 (en) | 2010-02-18 |
| KR20100019909A (en) | 2010-02-19 |
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