JPH0964359A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To relax a high electric field near a drain and to improve hot carrier resistance by connecting the high-concentration impurity region of a source/drain diffused layer to a channel region via a low-concentration impurity region. SOLUTION: A high-concentration impurity region 13a of a source/drain diffused layer 13 is connected to a channel region via a low-concentration impurity region 13b. To realize the structure, a process for forming a gate electrode 31 and a source/drain low-concentration diffused region 13b at the side of the gate electrode 31 in the substrate of the gate electrode 31, a process for forming an overhang body 32 which is wider than the gate electrode 31 and is overlapped with the source/drain low-concentration diffusion layer on the gate electrode 31, and a process for performing ion implantation of a high- concentration impurity region 13a of the source/drain diffusion layer with the overhang body 32 as a mask are used to manufacture a semiconductor device.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a so-called stacked diffusion type MOSFET which is an advanced type of MOSFET and a method for manufacturing the same.

[0002]

2. Description of the Related Art In a miniaturized MOSFET, a shallow junction of a source / drain diffusion layer is attempted in order to suppress a short channel effect. However, in the conventional structure, it is difficult to form a sufficiently shallow junction, and as a structure for realizing this, a so-called stacked diffusion layer type (elevated diffusion layer) having source / drain diffusion layer regions on the sides of the gate electrode is used.
(Rce and drain) MOSFETs are attracting attention.

An example of such a MOSFET is shown in FIG.
Shown in (A) and (B). The MOSFET of (A) uses a trench type for element isolation, and the substrate is planarized by a planarization technique such as CMP, while the MOSFET of (B) uses a field oxide film for element isolation. There are differences.

Such a stacked diffusion layer type MOSFE
Briefly explaining the manufacturing method of T, first, referring to FIG.
As shown in (1), after the element isolation oxide film 201 is grown on the substrate 101 by using the selective oxidation method, polycrystalline silicon 301 is deposited. Impurities are ion-implanted into this polycrystalline silicon layer, and an insulating film 202 is further deposited. In addition,
In this example of the manufacturing method, no well is formed.

Next, as shown in FIG. 5B, the stacked insulating film and the polycrystalline silicon layer are patterned by photolithography and separated by a groove 400 having a width of about 0.3 μm. Then, as shown in FIG. 5C, the sidewall 2 is formed on the sidewall of the groove 400 by depositing an insulating layer and etching back.
03 is formed to insulate the side wall of the diffusion layer. The gate length is determined by the thickness of the sidewall 203. Furthermore,
Impurities are ion-implanted for the punch stopper 104.
In this figure, the source / drain diffusion layer 103 is further formed by impurity diffusion from the stacked polycrystalline silicon layer 301.

After that, a gate oxide film 204 is formed, a gate electrode 302 is formed by depositing polycrystalline silicon, an interlayer insulating film is deposited, and a wiring layer is formed to form a MOSFET having a structure as shown in FIG. Can be obtained. According to such a MOSFET, the problem of punch-through due to miniaturization can be solved, and by making the MOSFET three-dimensional, a 0.1 μm MOSFET can be realized.

[0007]

However, the conventional stacked diffusion layer type MOSFET is a so-called single source / drain type in which the source / drain diffusion layer is composed of only a high-concentration impurity region, and is high in the vicinity of the drain. There is a concern that the resistance to hot carriers may be inferior instead of the LDD structure that relaxes the electric field. Therefore, in the stacked diffusion layer as well, it has been desired to reduce the high electric field in the vicinity of the drain by a structure such as an LDD structure.

The present invention has been made in view of the above circumstances. In a so-called stacked diffusion layer type semiconductor device having a source / drain diffusion layer region on the side of a gate electrode, a high electric field near the drain is relaxed. An object of the present invention is to provide a semiconductor device having improved hot carrier resistance and a method for manufacturing the same.

[0009]

In order to achieve the above object, the present invention provides the following semiconductor device and its manufacturing method. (1) In a semiconductor device in which a gate electrode is embedded in a trench on the surface of a substrate and a source / drain diffusion layer is formed on the side of the gate electrode via an insulating layer located on the side of the gate electrode. A semiconductor device having a structure in which a high concentration impurity region of a source / drain diffusion layer is connected to a channel region via a low concentration impurity region. (2) In a semiconductor device in which a gate electrode is formed by being buried in a trench on the surface of a substrate, and source / drain diffusion layers are formed on the side of the gate electrode through an insulating layer located on the side of the gate electrode. A semiconductor device having a high-concentration impurity region of a source / drain diffusion layer and a low-concentration impurity region deeper in the substrate vertical direction than the high-concentration impurity region. (3) The high-concentration impurity regions of the source / drain diffusion layers are
The semiconductor device according to (1) or (2) above, which is lateral to the gate electrode with a low-concentration impurity region in between. (4) Any of the above (1) to (3), wherein an eaves body is formed that is connected to overlap with an embedded gate electrode embedded in the substrate, protrudes from the side surface of the gate electrode in the width direction, and is wider than the gate electrode. The semiconductor device according to 1. (5) A semiconductor device in which a gate electrode is formed by being buried in a trench on the surface of a substrate, and source / drain diffusion layers are formed on the sides of the gate electrode through an insulating layer located on the side of the gate electrode. A method of manufacturing a semiconductor device, comprising: forming a high-concentration impurity region of a source / drain diffusion layer and a low-concentration impurity region deeper in the substrate vertical direction than the high-concentration impurity region in a self-aligning manner. (6) A step of forming a gate electrode buried in the surface of the substrate and a low-concentration impurity region of a source / drain diffusion layer on the substrate on the side of the gate electrode, and a source wider than the gate electrode on the gate electrode. A semiconductor device comprising: a step of forming an eaves body overlapping the low concentration drain diffusion layer; and a step of ion-implanting a high concentration impurity region of the source / drain diffusion layer using the eaves body as a mask. Manufacturing method. (7) The method for manufacturing a semiconductor device according to (6), wherein the eaves body is formed by selectively growing on the gate electrode. (8) The method for manufacturing a semiconductor device according to (6) or (7), wherein the eaves body is a metal or a semiconductor. (9) The method for manufacturing a semiconductor device according to any of (6) to (8), wherein the ion implantation for forming the high-concentration impurity region is oblique ion implantation.

In the semiconductor device of the present invention, the gate electrode is formed by burying it in the trench on the surface of the substrate, and the source / drain diffusion layer is provided on the side of the gate electrode via the insulating layer located on the side of the gate electrode. In the formed semiconductor device,
A structure in which the high-concentration impurity region of the source / drain diffusion layer is connected to the channel region through the low-concentration impurity region is introduced, and a so-called LDD structure is adopted for a so-called stacked diffusion layer type MOSFET.

In order to realize this, the present invention provides two kinds of manufacturing methods. One is to obtain an LDD structure in the depth direction in a self-aligned manner by ion implantation or double diffusion. Another is to form a low concentration region of the source / drain diffusion layer before and after forming the gate electrode, and then selectively grow tungsten, for example, on the gate electrode to form an eaves body wider than the gate electrode. By implanting ions using this eaves body as a mask, an LDD structure can be realized in a self-aligned manner.

Further, when ions are implanted using the eaves body as a mask, the ion implantation is performed obliquely so that the channel end and the high-concentration impurity region are brought close to each other, and the current capability of the MOSFET due to the parasitic resistance in the high-concentration impurity region is increased. The decrease can be suppressed.

[0013]

Embodiments of the present invention will be specifically described below with reference to the drawings. The present invention is not limited to the embodiments described below. FIG.
FIG. 6 is a cross-sectional view showing an example of some structures of a semiconductor device of the present invention.

The structure shown in (A-1) and (A-2) of FIG. 1 (A) shows that (A-1) has a flattened substrate using a flattening technique such as CMP. The difference is that the isolation is a trench structure ((A-2) is a selective oxidation method) (hereinafter, the same applies to (B) and (C)). This MOSFET
Is a so-called stacked type, and the high-concentration impurity region 1 of the source / drain diffusion layer 13 is formed on the substrate on the side of the gate electrode 31 embedded in the substrate 11 via the insulating sidewall 22.
3a, and the low-concentration impurity region 13b is below the high-concentration impurity region. The gate electrode 31 and the well 12 of the substrate are insulated by the gate insulating film 23, and the well 12 below the gate insulating film 23 is provided with a punch-through stopper 14. This MOSFET
Then, the high concentration impurity region 13 of the source / drain diffusion layer
a is the channel region 15 via the low-concentration impurity region 13b.
It has a structure connected with. These diffusion layers are electrically isolated from adjacent regions by a trench element isolation or selective oxide film 21, and further, in this example, the source / drain diffusion layers 13 of the MOSFET are formed in the well.

[0015] MOSFET of this structure, both ends of the channel 15 of low impurity concentration n ^- a layer 13b, has a LDD-like structure connected to the high impurity concentration of the n ⁺ layer 13a through which the drain Since the high electric field in the vicinity is relaxed, the hot carrier resistance is excellent. This Figure 1 (A)
The method of manufacturing the MOSFET will be described later.

In the structure shown in (A), the high electric field in the vicinity of the drain is relaxed, but the current density in the n ⁻ layer 13b is higher on the gate electrode side, so that the insulating film 22 next to the n ⁻ layer is hot. Degradation due to carrier injection remains. A structure that avoids this is the structural example of FIG. By separating the n ⁺ layer 13a from the insulating film 22 beside the gate electrode, the path of the drain current is separated from the insulating film 22. Therefore, the hot carrier generation position is determined by the insulating film 22.
It is difficult for hot carriers to be injected into this insulating film 22 away from. Further, in this structure, the overlap capacitance between the gate and the source or the drain is further reduced, and the speed is increased.

The structure in which the end on the gate electrode side of the high-concentration impurity region of FIG. 1B is closer to the carrier region is shown in FIG.
It is an example shown in (C). This allows the channel edge and n ⁺
By reducing the distance from the layer 13a, it is possible to suppress the decrease in the current capability of the MOSFET due to the parasitic resistance in the n ⁻ layer 13b.

Next, a manufacturing method for realizing these structures will be described. First, a method for realizing the structure shown in FIG. 1B-1 will be described with reference to FIGS. First, FIG.
As shown in (1), for example, a trench element isolation region 21 having a depth of 0.5 μm and an n ⁻ / p ⁻ well 12 deeper than this are formed on the surface of the Si substrate 11 by RIE of Si and flattening by oxide film CVD and CMP, respectively. And formed by a method such as ionization and ion implantation. Also, for example, the depth is 0.2μ
For example, an n ⁻ layer 13b of m is formed on the surface of the p ⁻ well 12 by ion implantation. It should be noted that the pMOSFET can be easily manufactured separately from the nMOSFET by selecting the ion species and the implantation region at the time of ion implantation. For simplification of the description, it is omitted in the drawings and the following description.

Next, as shown in FIG. 2B, after depositing a first insulating film 24 having a thickness of 0.1 μm, for example, a depth of 0.2 μm for burying the gate electrode is formed in the well region 12.
Forming a trench 40 of Si. As a result, the source / drain diffusion layer 13b is separated. In this case, a trench for the wiring layer in the same layer as the gate electrode may be formed in the element isolation region 21 at the same time, but it is also omitted in the drawings and the following description. It should be noted that the corners between the side wall and the bottom of the trench 40 may be rounded.

After that, as shown in FIG. 2C, the channel stopper 14 is formed in the substrate below the bottom of the trench 40 by ion implantation, and the gate insulating film 23 is further formed. Further, here, the sidewall insulating film 22 inside the trench 40 may be formed in advance by depositing an insulating layer in the trench 40 and etching back. The side wall insulating film 22 separates the gate electrode 31 from the source / drain layer 13b.

Then, as shown in FIG. 2 (4), after depositing polysilicon or amosphasic silicon, the upper ends of these are flattened by, for example, CMP so that they do not remain on the first insulating film 24 until they are aligned. Thus, the gate electrode 31 (and the wiring) embedded in the trench is formed. Here, the polysilicon or the amorphous silicon is doped with P at the same time as the deposition.

Next, as shown in FIG. 2 (5), a tungsten W (overhang body) 32 is selectively grown on the gate electrode exposed on the surface. At this time, W grows in the lateral direction as well as in the upward direction, and therefore has a shape symmetrical with respect to the center of the gate electrode 31 and has an overlap on the first insulating film 24. Here, not only W but also metals such as Mo and Al that can be selectively grown, refractory metal silicides such as TaSi ₂ and TiSi ₂ , or semiconductors such as polysilicon and amorphous silicon may be used. Further, the selective growth is performed by, for example, depositing W by CVD using WF ₆ gas at a deposition rate of Si.
The fact that it is large on a metal surface and small on an insulating film such as a silicon oxide film is used.

Then, as shown in FIG. 2 (6), for example, As is selected from above the W 32 selectively grown on the gate electrode 31.
^By implanting ⁺ ions to form the n ⁺ layer 13a, the source / drain diffusion layer 13 having an LDD-like impurity concentration gradient is obtained, the high electric field near the drain is relaxed, and the generation of hot carriers is suppressed. It And
Since the n ⁺ layer 13a is not in contact with the gate sidewall insulating film 22, the drain current flows at a position away from this,
The generated hot carriers are hard to reach the insulating film 22, and the hot carrier resistance is further improved. Where n ⁺ layer 1
The depth of 3a does not necessarily have to be shallow as in the embodiment of FIG. 1 with respect to the depth of the n ⁻ layer 13b, and may be the same or deep.

Finally, after depositing the second insulating film 25, a contact hole (not shown in the sectional view) is formed on the source / drain diffusion layer 13 or to the gate electrode 31, and n ⁺ is formed by contact compensation ion implantation. After the layer 16 is formed, the impurity ions are activated, and the metal wiring layer 33 such as Al is formed, a semiconductor device is formed as shown in FIG.

The method of manufacturing the structure shown in FIG. 1A can be performed, for example, as follows. The formation of the gate electrode 31 and the formation of the n ⁻ layer 13b may be the same as in FIGS. 2 (1) to 2 (4). After that, the n ⁺ layer 13a is formed by adjusting the implantation energy by As ⁺ or P ⁺ ion implantation or the like so that its lower end is shallower than the lower end of the n ⁻ layer 13b to realize an LDD-like structure. In the structure of FIG. 1A-2, in order to reduce the wiring resistance of the gate electrode, the gate electrode 31 is covered with a metal such as W (tungsten), a semiconductor such as polysilicon or an alloy such as silicide, and patterned. Then, the wiring layer 36 is formed. As shown in FIG. 3 (1), in this structure, after the formation of the n ⁻ layer 13b and the n ⁺ layer 13a of the source / drain diffusion layers, as shown in FIG. ⁺ Layer 13a
Alternatively, the trench 40 for separating the n ⁻ layer 13b and the n ⁻ layer 13b may be formed, and then the sidewall insulating film 22 and the gate oxide film 23 may be formed.

In order to obtain a MOSFET having a structure in which the channel side end of the high concentration region of the source / drain diffusion layer shown in FIG. 1C is close to the channel region, as shown in FIG. During ion implantation for formation (Fig. 2
(6)), by ion implantation from the normal, for example, 30 degrees tilted (oblique ion implantation), the channel ends and the n ⁺
By shortening the distance from the layer 13a, it is possible to suppress the decrease in the current capability of the MOSFET due to the parasitic resistance in the n ⁻ layer 13b.

[0027]

According to the semiconductor device of the present invention, in a so-called stacked diffusion layer type MOSFET having source / drain diffusion layer regions on the substrate on the side of the gate electrode, a high electric field near the drain is relaxed to withstand hot carriers. Is an improvement.

Further, according to the method of manufacturing a semiconductor device of the present invention, such a semiconductor device can be manufactured easily and reliably.

[Brief description of drawings]

1A to 1C are cross-sectional views each showing an example of a semiconductor device of the present invention.

2 (1) to (7) are cross-sectional views showing an example of a manufacturing process of a semiconductor device of the present invention.

3 (1) and 3 (2) are cross-sectional views showing another example of steps of the method for manufacturing a semiconductor device of the present invention.

4A and 4B are sectional views showing an example of a conventional so-called stacked MOSFET.

5 (1) to (4) are cross-sectional views showing a manufacturing process of a conventional so-called stacked MOSFET.

[Explanation of symbols]

11 substrate 12 well 13a low concentration impurity region of source / drain diffusion layer 13b high concentration impurity region of source / drain diffusion layer 14 punch through stopper 22 side wall insulating film 23 gate insulating film 31 gate electrode 32 W selective growth layer (overhanging body)

Claims (9)

[Claims] 1. A semiconductor in which a gate electrode is formed by burying it in a trench on the surface of a substrate, and source / drain diffusion layers are formed on the sides of the gate electrode through an insulating layer located on the side of the gate electrode. A semiconductor device having a structure in which a high concentration impurity region of a source / drain diffusion layer is connected to a channel region via a low concentration impurity region. 2. A semiconductor in which a gate electrode is formed by burying it in a trench on the surface of a substrate, and source / drain diffusion layers are formed on the sides of the gate electrode via an insulating layer located on the side of the gate electrode. A semiconductor device having a high-concentration impurity region of a source / drain diffusion layer and a low-concentration impurity region deeper in the substrate vertical direction than the high-concentration impurity region. 3. The semiconductor device according to claim 1, wherein the high-concentration impurity region of the source / drain diffusion layer is lateral to the gate electrode with the low-concentration impurity region interposed therebetween. 4. An eaves body which is connected to overlap with an embedded gate electrode embedded in a substrate, is protruded in a width direction from a side surface of the gate electrode and is wider than the gate electrode. The semiconductor device according to. 5. A semiconductor in which a gate electrode is formed by burying it in a trench on the surface of a substrate, and source / drain diffusion layers are formed on the side of the gate electrode through an insulating layer located on the side of the gate electrode. A method of manufacturing a semiconductor device, characterized in that a high-concentration impurity region of a source / drain diffusion layer and a low-concentration impurity region deeper in the substrate vertical direction than the high-concentration impurity region are formed in a self-aligned manner. . 6. A step of forming a gate electrode buried in the surface of the substrate and a low concentration impurity region of a source / drain diffusion layer in the substrate on the side of the gate electrode, and forming a gate electrode wider than the gate electrode on the gate electrode. And a step of forming an eaves body overlapping the source / drain low-concentration diffusion layer, and a step of ion-implanting the high-concentration impurity regions of the source / drain diffusion layer using the eaves body as a mask. Manufacturing method of semiconductor device. 7. The method of manufacturing a semiconductor device according to claim 6, wherein the eaves body is formed by selectively growing on the gate electrode. 8. The method for manufacturing a semiconductor device according to claim 6, wherein the eaves body is a metal or a semiconductor. 9. The method for manufacturing a semiconductor device according to claim 6, wherein the ion implantation for forming the high-concentration impurity regions is oblique ion implantation.