JPH0832063A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form a conductive layer for a gate electrode inside a trench in self-alignment only by a method wherein, after the formation of a trench in a substrate, a silicon oxide film is formed on the bottom of the trench and then a metallic film deposited on the whole substrate surface is heat-treated. CONSTITUTION:Sidewalls 61 comprising nitride film are formed and after forming a trench 62 in a substrate, an oxide film 63 is formed on the trench surface through oxidation process. Successively, a metallic film 71 is deposited on the whole substrate so as to leave the metallic film 71 in an electrode forming part using photolithography. Next, by finishing heat treatment, a titanium silicide film 81 is formed between the silicon oxide film 63 and a titanium film 71 while titanium oxide film 82 is formed on the surface of the trench bottom. Successively, a tungsten 91 is selectively grown on the exposed titanium silicide film only, A gate electrode is composed of this tungsten 91 and the titanium silicide film 81 by selective growing process. Accordingly, a conductive layer for a gate electrode can be self-aligned inside the trench only.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having an advantage in miniaturization, and particularly to a MOS (Metal-Oxide-Semico) having an advantage of excellent short channel characteristics.
nductor) relates to a method for manufacturing a transistor.

[0002]

2. Description of the Related Art A MOS transistor using a silicon substrate has been improved in performance by miniaturization in accordance with a scaling rule. However, the promotion of miniaturization causes a phenomenon called a short channel effect, which is represented by a decrease in threshold voltage and punch through, and makes it difficult to control transistor characteristics.

As a device structure advantageous for suppressing the short channel effect, a groove gate type MOS transistor shown in FIG. 2 (for example, described in JP-A-59-99771) is conventionally known. The greatest feature of the trench gate type MOS transistor is that the trench is formed in the substrate and the gate electrode 91 is formed in that portion, so that the junction of the source / drain 36 is located above the channel. As a result, there is no path through which the punch-through current flows, and the short channel effect is suppressed.

Here, 11 is an interlayer insulating film, 12 is a metal filling the contact hole, 13 is a wiring, 31 is a p-type silicon substrate, 32 is a p-type well region, 33 is an element isolation oxide film,
35 is a high-concentration impurity region for improving isolation between elements, 41
Is a source / drain extraction electrode, 42 is a nitride film serving as a source / drain extraction electrode processing mask, 61 is a silicon nitride film sidewall, and 63 is a gate oxide film.

[0005]

However, in the conventional manufacturing method of the trench gate type MOS transistor, since the gate electrode has the structure overhanging the extraction electrode 41 of the source / drain, the gate electrode and the contact hole are formed. The spacing determines the device dimensions, and even if fine grooves can be formed,
The size of the entire device is not necessarily reduced. This problem can be solved by embedding the gate electrode inside the groove. The most common method of realizing this structure is to use the well-known planarization blanket etching method. This is a method in which the groove is completely backfilled with a conductive film to be the gate electrode and then the entire surface is etched to leave the gate electrode only inside the groove. However, in this method, if the dimensions of the groove are different, there is a portion filled with the conductive film and a portion not filled with the conductive film, so that the degree of freedom in device design is lost.

It is an object of the present invention to provide a method of forming a conductive layer which becomes a gate electrode only inside the groove in a self-aligned manner.

Another object of the present invention is to provide a fine groove gate MOS transistor excellent in short channel characteristics and a manufacturing method thereof.

[0008]

As one of the means for solving the above-mentioned problems, it is conceivable to utilize a known tungsten selective CVD method. However, unlike the formation of the gate electrode intended by the present invention, tungsten does not grow on the silicon oxide film. Therefore, in the present invention, after forming a groove, a silicon oxide film is formed on the bottom surface of the groove, and a metal film having an electronegativity (Poling scale) of 1.5 or less (for example, titanium, vanadium, zirconium, etc.) is formed on the entire surface of the substrate. After depositing, heat treatment is performed. As a result, a reaction occurs in the portion where the metal film and the silicon oxide film are in contact with each other, and the portion having the two-layer structure of the metal film and the silicon oxide film is, in order from the top, the metal oxide film, the metal film, the silicide film, and the silicon oxide film. Changes to a four-layer structure. If the metal oxide film and the metal film are removed and the silicide film is exposed, tungsten grows only on the silicide film by the well-known tungsten selective growth method, so that the metal gate electrode is formed only in the groove. To be done.

[0009]

According to the present invention, since the gate electrode can be selectively formed only in the trench, a fine trench gate MOS transistor excellent in short channel characteristics can be manufactured without increasing the device size. It will be possible. As a result, it is possible to realize a MOS transistor which is free from punch-through and reduction in threshold voltage due to miniaturization.

[0010]

【Example】

(Embodiment 1) FIG. 1 shows an MO according to an embodiment of the present invention.
It is an element sectional view of an S transistor. Since the tungsten gate electrode is selectively formed only inside the trench, a photolithography process is not required for patterning the gate electrode, and a fine trench gate MOS transistor can be realized as the entire device.

Here, 11 is an interlayer insulating film, 12 is a metal filling contact holes, 13 is a wiring, 31 is a p-type silicon substrate, 32 is a p-type well region, 33 is an element isolation oxide film, and 35 is an element-to-element isolation film. High-concentration impurity region for improving isolation characteristics, 41 is a source / drain extraction electrode, 42 is a nitride film serving as a mask for processing the source / drain extraction electrode, 6
Reference numeral 1 is a silicon nitride film sidewall, 63 is a gate oxide film, 81 is titanium silicide, and 91 is a gate electrode.

The MO channel of this embodiment will be described below for the n channel.
A method of manufacturing the S transistor will be described. The p-channel can also be manufactured in the same process by reversing the conductivity type of the impurities, and the MO channel having different conductivity types can be formed on the same substrate.
If the S transistor is formed, a complementary circuit can be constructed.

First, as shown in FIG. 3A, a well region 32 is formed in a semiconductor substrate 31 by using a known surface oxidation method and ion implantation method. Specifically, the semiconductor substrate is a p-type silicon substrate containing boron at a concentration of 1 × 10 ¹⁵ / cm ³ , and the well 32 is about 5 × 10 ¹⁶ boron.
/ Cm ³ included. After forming the well, an oxide film 33 for element isolation is formed to a thickness of about 500 nm by using a known selective oxidation method, and an oxide film 34 is further formed to a thickness of about 20 nm on the substrate surface. An impurity region 35 having the same conductivity type as that of the well region is formed by an ion implantation method so that the concentration is maximized just below the element isolation oxide film. Specifically, boron is implanted so that the peak concentration is about 1 × 10 ¹⁸ / cm ³ . Further, an impurity region 36 having a conductivity type different from that of the well region, which will be a part of the source / drain later, is formed by the ion implantation method.

Specifically, the peak concentration of arsenic is about 1 × 1.
Implantation was performed so that the junction depth was 0 ²⁰ / cm ³ and the junction depth was 100 nm.

Next, after removing the oxide film 34 on the surface of the element region, as shown in FIG. 3B, a polycrystalline silicon film 41 of 100 nm is formed on the surface of the substrate by a known CVD (Chemicl Vapor Depo).
sition) method. Then, ion implantation is also performed on this film to form an impurity region having a conductivity type different from that of the well region. Specifically, phosphorus has a peak concentration of about 1 × 10 ²⁰ /
Drive so that it becomes cm ³ . Then, the silicon nitride film 4
2 is deposited to a thickness of about 100 nm by a known CVD method. The silicon nitride film 42 is used here so that a silicidation reaction does not occur with a metal film deposited thereon later.

Subsequently, as shown in FIG. 3C, the nitride film 42 and the polycrystalline silicon film 41 are processed by a known dry etching method to separate them into a pair of stacked diffusion layers. At this time, the etching amount was controlled so that the underlying silicon substrate was not dug much, that is, the impurity region 36 having a conductivity type different from that of the well region was not removed.
After that, the silicon nitride film 53 is formed to a thickness of 100 nm by a known CV method.
Deposit by method D. The film thickness deposited at this time determines the width of the groove in which the gate electrode is embedded. The silicon nitride film 53 also does not cause a silicidation reaction with the metal film to be deposited thereon later.

Next, as shown in FIG. 4A, the side wall 6 of the nitride film is formed by using known anisotropic dry etching.
1 is formed. Further, by using known anisotropic dry etching, the groove 62 is formed in the substrate at a depth of 150 n from the substrate surface.
It is formed so that it becomes m. The impurity region 36 having a conductivity type different from that of the well region described above is divided by the trench 62 to become the source / drain 36. After that, an oxide film 63 of 20 nm is formed on the groove surface by a known thermal oxidation method.

Subsequently, a metal film having a thickness of 40 nm is deposited on the entire surface of the substrate, and as shown in FIG. 4B, a portion of the metal film 71 for forming an electrode is left by using a photolithography process. Metal film 71
The reason why only a part of the above is left is to prevent a reaction on the element isolation oxide film 33. The metal film 71 is a metal having an electronegativity (Poling scale) of 1.5 or less (for example, titanium, vanadium, zirconium, etc.) and reacts with the underlying silicon oxide film to form a silicide film.
Titanium was used in this embodiment.

Next, when a heat treatment of 800 ° C. is applied, as shown in FIG.
As shown in (C), the silicon oxide film 63 and the titanium film 7
1 and a titanium silicide film 81 is formed between them and a titanium oxide film 82 is formed on the surface of the bottom of the groove. In this embodiment, the titanium silicide film 81 has a thickness of 15 nm and the silicon oxide film 63 has a thickness of 5 nm. Subsequently, when the unreacted titanium 71 is removed by using hydrogen peroxide, the titanium silicide film 81 is exposed. At this time, the titanium oxide film 82 is lifted off because the underlying titanium film 71 is removed. Before using hydrogen peroxide, only the titanium oxide film 82 may be previously removed by dry etching.

Then, using a known selective growth method of tungsten, as shown in FIG. 5, tungsten 91 is selectively grown only on the exposed titanium silicide film.
The tungsten 91 and the titanium silicide film 81 form a gate electrode.

Subsequently, after cleaning the surface of the substrate, as shown in FIG. 1, an interlayer insulating film 11 is deposited on the entire substrate by a CVD method,
Subsequently, heat treatment is applied to flatten the surface. In particular,
First, an oxide film containing no impurities is deposited to a thickness of about 100 nm, an oxide film containing boron and phosphorus at a high concentration is deposited thereon, and heat treatment is performed to cause reflow. Finally, insulating film 1
A contact hole is opened in 1 and a metal such as tungsten is backfilled by a known selective CVD method, and then a wiring 13 is formed to complete the transistor of the present invention.

(Embodiment 2) FIG. 6 is a sectional view of an element of a trench gate MOS transistor according to a second embodiment of the present invention. This embodiment is characterized in that after the gate electrode is formed in the groove, the insulating film used for forming the groove is removed and then the source / drain is formed by ion implantation using the gate electrode as a mask. The bottom of the groove is rounded to increase the drain current.

Here, 11 is an interlayer insulating film, 12 is a metal filling the contact hole, 13 is a wiring, 31 is a p-type silicon substrate, 32 is a p-type well region, 33 is an element isolation oxide film,
34 is a silicon oxide film, 35 is a high-concentration impurity region for improving isolation characteristics between devices, 63 is a silicon oxide film (gate insulating film), 81 is titanium silicide, 91 is tungsten, 101 and 112 are n-type impurity regions (source). ) 10
Reference numerals 2 and 113 are n-type impurity regions (drains), and 111 is a gate sidewall sidewall (silicon oxide film).

In the following, regarding the n-channel, the MO of this embodiment is used.
A method of manufacturing the S transistor will be described. Similar to the first embodiment, the p-channel and the complementary circuit can be manufactured in the same manner.

First, as shown in FIG. 7A, the well region 32 is formed in the semiconductor substrate 31 by using the well-known surface oxidation method and ion implantation method. Specifically, the semiconductor substrate is a p-type silicon substrate containing boron at a concentration of 1 × 10 ¹⁵ / cm ³ , and the well 32 is about 5 × 10 ¹⁶ boron.
/ Cm ³ included. After forming the well, an oxide film 33 for element isolation is formed to a thickness of about 500 nm by using a known selective oxidation method, and an oxide film 34 is further formed to a thickness of about 20 nm on the substrate surface. An impurity region 35 having the same conductivity type as that of the well region is formed by the ion implantation method so that the concentration is maximized immediately below the element isolation oxide film. Specifically, boron is implanted so that the peak concentration is about 1 × 10 ¹⁸ / cm ³ .

Next, a silicon nitride film 42 is formed on the surface of the substrate.
It is deposited by a known CVD (Chemicl Vapor Deposition) at 00 nm. The silicon nitride film 42 is used here so that a silicidation reaction does not occur with a metal film deposited later on the silicon nitride film 42. Then, as shown in FIG. 7B, a groove is opened in a portion to be a gate electrode later. Further, well region 32 is exposed on the bottom surface of the groove by using known anisotropic dry etching. In this embodiment, the bottom surface of the groove is located at a depth of 100 nm from the surface of the element region and has a rounded shape. Further, after cleaning the surface, a silicon oxide film 63 is formed on the bottom surface of the groove by a known thermal oxidation method.
Of 20 nm is formed.

Subsequently, as shown in FIG. 7C, a metal film 71 having a thickness of 40 nm is deposited on the entire surface of the substrate. The metal film 71 is a metal having an electronegativity (Poling scale) of 1.5 or less (for example, titanium, vanadium, zirconium, etc.) and reacts with the underlying silicon oxide film to form a silicide film. Titanium was also used in this example.

Next, when a heat treatment of 800 ° C. is applied, as shown in FIG.
As shown in (A), the silicon oxide film 63 and the titanium film 7
1 and a titanium silicide film 81 are formed between them, and a titanium oxide film 82 is formed on the surface of the bottom of the groove. In this embodiment, the titanium silicide film 81 has a thickness of 15 nm and the silicon oxide film 63 has a thickness of 5 nm. Subsequently, hydrogen peroxide is used to remove the unreacted titanium 71 to expose the titanium silicide film 81. At this time, the titanium oxide film 82 is lifted off because the underlying titanium film 71 is removed. Before using hydrogen peroxide, only the titanium oxide film 82 may be previously removed by dry etching.

Then, by using a known tungsten selective growth method, as shown in FIG. 8B, tungsten 91 is selectively grown only on the exposed titanium silicide film. This tungsten 91 and titanium silicide film 81
Form the gate electrode.

Next, the silicon nitride film 42 is removed, and FIG.
As shown in (C), using the gate electrode as a mask, an impurity having a conductivity type different from that of the well region 32 is introduced into the well region by a known ion implantation method, and the source 101 / drain 1 is formed.
02. Specifically, the concentration of arsenic is about 1 × 10 ²⁰ / cm
Ion implantation is performed with an implantation energy of about 25 KeV so as to be ³ . The implantation energy was adjusted so that the junction depth between the source 101 and the drain 102 was above the bottom surface of the gate oxide film 63.

Subsequently, after depositing a silicon oxide film on the entire surface of the substrate by a known CVD method, a sidewall 111 is formed on the side wall of the gate electrode by using a known anisotropic dry etching as shown in FIG. Further, using the gate electrode and the side wall 111 as a mask, a deep source 112 / drain 113 having a junction is formed by a known ion implantation method to reduce the resistance. Specifically, the concentration of arsenic is about 5 × 1
Ion implantation is performed so that the amount becomes 0 ²⁰ / cm ³ .

Finally, after cleaning the substrate surface, an interlayer insulating film 11 is deposited on the entire substrate by the CVD method as shown in FIG.
Subsequently, heat treatment is applied to flatten the surface. In particular,
First, an oxide film containing no impurities is deposited to a thickness of about 100 nm, an oxide film containing boron and phosphorus at a high concentration is deposited thereon, and heat treatment is performed to cause reflow. The impurities implanted at this time are also activated. Then, a contact hole is opened in the insulating film 11 and a metal such as tungsten is backfilled by a known selective CVD method, and then a wiring 13 is formed to complete the transistor of the present invention.

(Embodiment 3) FIG. 10 is a sectional view of an element of a MOS transistor according to an embodiment of the present invention. In this embodiment, a silicon oxide film is formed in advance on the surface of the element region, a groove is formed in the nitride film deposited thereon to expose the silicon oxide film, and a silicidation reaction occurs with the metal deposited there. There is a feature in making it. This embodiment is an example of forming a fine metal gate with a normal MOS transistor that is not a groove gate.

Here, 11 is an interlayer insulating film, 12 is a metal filling contact holes, 13 is wiring, 31 is a p-type silicon substrate, 32 is a p-type well region, 33 is an element isolation oxide film,
34 is a silicon oxide film (gate insulating film), 35 is a high-concentration impurity region for improving isolation between elements, 81 is titanium silicide, 91 is tungsten, 101 and 112 are n-type impurity regions (source), and 102 and 113 are n. The type impurity region (drain) 111 is a gate sidewall sidewall (silicon oxide film).

The MO of this embodiment will be described below for the n channel.
A method of manufacturing the S transistor will be described. Similar to the first embodiment, the p-channel and the complementary circuit can be manufactured in the same manner.

The process until the silicon nitride film is deposited on the substrate surface is exactly the same as that in the second embodiment. And FIG.
As shown in (A), a groove is opened in the silicon nitride film 42.
At this time, unlike the second embodiment, the silicon oxide film 34 formed on the surface of the element region before the silicon nitride film 42 is deposited is exposed on the bottom surface of the groove. In other words, the MOS transistor manufactured in this embodiment has the source / drain junction deeper than the channel, and although the groove forming process is used, the transistor structure is the conventional MOS transistor of the normal structure. Is the same as.

Subsequently, as in Example 2, titanium was deposited on the entire surface of the substrate and heat-treated, and as shown in FIG. 11B, the titanium oxide film 82 and unreacted titanium oxide film 82 were formed on the bottom of the groove in order from the top. A laminated film structure including four layers of the titanium film 71, the titanium silicide film 81, and the silicon oxide film 34 is formed. After the unreacted titanium 71 is removed by using hydrogen peroxide to expose the titanium silicide film 81, tungsten is selectively grown only on the titanium silicide film 81 by using the known tungsten selective growth method. , Silicon nitride film 4
Similarly to the second embodiment, 2 is removed, and as shown in FIG. 11C, an impurity having a conductivity type different from that of the well region 32 is introduced into the well region by a known ion implantation method using the gate electrode as a mask. is there.

The side wall formation, the source / drain ion implantation, the impurity activation by heat treatment, the interlayer insulating film deposition, the contact formation, and the wiring are carried out in the same manner as in the second embodiment, as shown in FIG. The transistor of the present invention is completed.

[0039]

According to the present invention, the metal film is selected by using the well-known technique of selective growth of tungsten, and on the material on which the growth of tungsten does not occur in principle such as on the oxide film. Can be made to grow. A MOS transistor can be manufactured by using this metal film as a gate electrode and using a previously formed oxide film as a gate oxide film. Moreover, in order to utilize the groove formed on the substrate, a fine gate electrode is formed in a self-aligned manner, and by further forming the groove on the silicon substrate, the source and drain are completely separated. It is possible to manufacture a MOS transistor in which punch-through does not occur even when miniaturized.

[Brief description of drawings]

FIG. 1 is a sectional view showing an embodiment of a groove gate MOS transistor according to the present invention.

FIG. 2 is a sectional view showing an example of a conventional groove gate MOS transistor.

FIG. 3 is a cross-sectional view showing a manufacturing process of the groove gate MOS transistor of FIG.

FIG. 4 is a cross-sectional view showing a manufacturing process of the groove gate MOS transistor of FIG.

5A and 5B are cross-sectional views showing a manufacturing process of the trench gate MOS transistor of FIG.

FIG. 6 is a sectional view showing an embodiment of a groove gate MOS transistor according to the present invention.

FIG. 7 is a cross-sectional view showing a manufacturing process of the MOS transistor of FIG.

FIG. 8 is a cross-sectional view showing a manufacturing process of the MOS transistor of FIG.

FIG. 9 is a cross-sectional view showing a manufacturing process of the MOS transistor of FIG.

FIG. 10 is a sectional view showing an embodiment of a MOS transistor according to the present invention.

11 is a cross-sectional view showing a manufacturing process of the MOS transistor of FIG.

[Explanation of symbols]

11 ... Interlayer insulating film, 12 ... Metal, 13 ... Wiring, 31 ... p
Type silicon substrate, 32 ... P type well region, 33 ... Element isolation oxide film, 35 ... High concentration impurity region, 36 ... N type impurity region, 41 ... Polycrystalline silicon, 42 ... Nitride film, 61 ...
Nitride film side wall, 63 ... Oxide film, 91 ... Tungsten.

Claims (8)

[Claims] 1. A step of growing an insulating film for electrically isolating each element on a semiconductor substrate, a step of forming an impurity region having a conductivity type different from that of the substrate, and an extraction electrode to the impurity region. A step of forming, a step of forming a silicon nitride film on the side wall of the extraction electrode, a step of forming a groove in the substrate using the extraction electrode and the silicon nitride film as a mask, and dividing the impurity region into two by the groove. A step of forming a silicon oxide film in the groove, a step of depositing a metal film on the groove and leaving a metal film covering a portion corresponding to the gate electrode, and removing the other metal films; A step of reacting a silicon oxide film to form a silicide film at an interface between the metal film and the silicon oxide film,
A step of removing the unreacted metal film and the metal oxide film, a step of selectively forming the metal film on the exposed silicide film to form the gate electrode, and an interlayer insulating film as a base of the wiring layer And a step of forming a hole in the interlayer insulating film to expose a conductive layer in a semiconductor substrate, a gate electrode, and an impurity region having a conductivity type different from that of the substrate, and a step of forming a wiring layer. Manufacturing method of semiconductor device. 2. A step of forming a plurality of well regions containing impurities of the first conductivity type and a well region containing impurities of the second conductivity type on a semiconductor substrate, and an insulating film for electrically isolating each element. Growing, a step of forming a first insulating film on the surface of the semiconductor substrate, a step of forming a silicon nitride film on the surface, a groove is opened in the first insulating film and the silicon nitride film, and silicon is formed. A step of digging a groove in the substrate, a step of forming a silicon oxide film on the bottom surface of the groove, a step of depositing a metal film on the groove, and a step of reacting the metal film with the silicon oxide film to cause the metal film and the silicon film to react. A step of forming a silicide film on the interface of the oxide film, a step of removing the unreacted metal film and the metal oxide film, and a step of selectively forming a metal film on the exposed silicide film to form a gate electrode, The silicon with grooves formed Removing the oxide film, forming an impurity layer having a conductivity type different from that of the well region in the well region by using the gate electrode as a mask, and depositing an interlayer insulating film as a base of the wiring layer And a step of forming a hole in the interlayer insulating film to expose a conductive layer such as a semiconductor substrate, a gate electrode, and a region containing an impurity having a conductivity type different from that of the well region, and a step of forming a wiring layer. And a method for manufacturing a semiconductor device. 3. A step of forming a plurality of well regions containing impurities of a first conductivity type and a well region containing impurities of a second conductivity type on a semiconductor substrate, and an insulating film for electrically isolating each element. , A step of forming a silicon oxide film on the surface of the semiconductor substrate, a step of forming a silicon nitride film thereon, and a step of opening a groove in the silicon nitride film to expose the silicon oxide film A step of depositing a metal film thereon, a step of reacting the metal film with the silicon oxide film to form a silicide film at an interface between the metal film and the silicon oxide film, and an unreacted metal film A step of removing the metal oxide film; a step of selectively forming the metal film on the exposed silicide film to form a gate electrode; a step of removing the nitride film having a groove formed therein; and a mask of the gate electrode. Then The step of forming an impurity layer having a conductivity type different from that of the well region in the well region, the step of depositing an interlayer insulating film as a base of the wiring layer, the step of forming a hole in the interlayer insulating film, the semiconductor substrate, the gate A method of manufacturing a semiconductor device, comprising: a step of exposing a conductive layer such as a region containing impurities having different conductivity types from electrodes and a well area; and a step of forming a wiring layer. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the metal film that reacts with the silicon oxide film to form the silicide film at the interface is titanium. 5. The method of manufacturing a semiconductor device according to claim 1, wherein the metal film that reacts with the silicon oxide film to form the silicide film at the interface is vanadium. 6. The method of manufacturing a semiconductor device according to claim 1, wherein the metal film which reacts with the silicon oxide film to form a silicide film at the interface is zirconium. 7. The method of manufacturing a semiconductor device according to claim 1, wherein the metal film which reacts with the silicon oxide film to form a silicide film at the interface is niobium. 8. The method of manufacturing a semiconductor device according to claim 1, wherein the metal film which reacts with the silicon oxide film to form a silicide film at the interface is hafnium.