JP2739849B2 - Method for manufacturing semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a semiconductor integrated circuit, and more particularly to a method of forming a polycrystalline silicon film which partially contacts a semiconductor substrate such as a direct contact.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit, from the viewpoint of high integration, a process of directly connecting an electrode layer or a wiring layer made of a polycrystalline silicon film to a diffusion layer on a substrate surface is often used. For example, in a method for manufacturing a high-speed bipolar transistor, the emitter region and the base region are self-aligned (Self-Align) in order to reduce parasitic resistance and parasitic capacitance.
There is a technology formed by. Also, in a highly integrated static memory (SRAM) mainly composed of MOS transistors, there is a portion where the gate electrode wirings of a pair of MOS transistors constituting a flip-flop in a memory cell are connected to each other's drain region. In order to reduce the cell area, a direct contact is formed using a polycrystalline silicon film serving as a gate electrode.

An up-to-date example of the structure and fabrication method of the base contact of the former self-aligned bipolar transistor is given by the IEEE International Electro Devices Meeting Technical Digest (IEEE International Election).
electron Devices Meeting Te
Chemical Digest,), 1994, pp. 441-444. In this technique, a method of forming an external base contact is devised in order to adjust a difference in heat treatment required to form a MOS transistor and a bipolar transistor in a BiCMOS device. A method of forming the external base contact will be described with reference to FIG.

The surface of a P type silicon substrate is selectively N
^{A +} type region is provided, and as shown in FIG.
A P-type region (not shown) for element isolation is formed on the silicon substrate 101 on which the N-type epitaxial layer 101-1 of μm is grown, a P-well and an N-well (not shown) are formed, and element isolation is performed by selective oxidation. Oxide film 102
It is formed to a thickness of 400 nm. After the gate oxide film 103 of the CMOS transistor is grown, the polycrystalline silicon film 104 serving as the CMOS gate electrode and the bipolar base electrode is formed by a known CVD technique to 150 to 3 nm.
It grows to a thickness of 00 nm. At this time, no impurity is added to the polycrystalline silicon film 104. Next, in order to electrically insulate the emitter electrode and the base electrode, an insulating film 105 such as a silicon nitride film is grown on the polycrystalline silicon film 104 to a thickness of 100 to 200 nm. Thereafter, using a known light exposure technique, a mask is applied to a region other than the region where the base and the emitter of the bipolar transistor are formed,
The insulating film 105 and the polycrystalline silicon film 104 are removed by a known dry etching technique. As a result, a hole for connecting the emitter electrode, that is, an emitter contact hole 106 is opened. However, the gate oxide film 10
Since 3 serves as a stopper for etching the polycrystalline silicon film 104, the CMOS gate oxide film 103 remains on the upper surface of the region where the base and the emitter of the bipolar transistor are formed. Therefore, the gate oxide film 3 under the polycrystalline silicon film 104 is horizontally etched by 100 to 200 nm by a known wet etching technique.
To remove. Thereby, the polycrystalline silicon film 104
A gap 107 having a gate oxide film thickness is formed in the lower part of the substrate in the horizontal direction. Next, as shown in FIG.
V-CVD (Ultra High Vacuum CVD (Ultra High
Vacuum Vapor Deposition))
Technology, using Si ₂ H ₆ gas and B ₂ H ₆ gas,
A silicon film 108 containing boron at a high concentration of about × 10 ²⁰ cm ^-3 and becoming a single crystal in the opening and the gap is grown on the entire surface of the substrate. Next, as shown in FIG. 3C, the silicon film 108 is removed by known isotropic etching while leaving the single crystal silicon film 108a (which serves as a link base) embedded in the gap 107.

Next, as shown in FIG. 3D, BF ₂ ⁺ implantation for forming an intrinsic base region 112 and phosphorus ion implantation for forming a collector extraction region (not shown) are performed. Next, a spacer 109 made of a silicon oxide film is formed, and an N ⁺ -type polycrystalline silicon film 110 and a silicon oxide film 111 are sequentially deposited and patterned to form an emitter electrode. Next, FIG.
As shown in FIG. 7, the gate electrode 1 of the pMOS transistor is formed by patterning the polycrystalline silicon film 108.
14. A base electrode 113 is formed, a spacer 115 made of a silicon oxide film is formed, and BF ₂ ⁺ is implanted.
Next, by performing a heat treatment at 900 ° C., an emitter region 117, a graft base region 118, and a source / drain region 116 are formed.

On the other hand, a conventional example of direct contact of a highly integrated static memory (SRAM) mainly composed of MOS transistors will be described. A typical example of this is “Basics of LSI technology” published by the Telecommunications Association of Japan.
(Edited by Kotaro Kato) from page 190 to page 192.

FIG. 4A is a plan view showing a typical example of a high resistance load type SRAM cell, and FIG. 4B is a circuit diagram. M
OS transistors T _{1 to} T ₄ are a P-type silicon substrate 201
Has an N-type diffusion layer 209 formed on the surface portion thereof and a gate electrode composed of polycrystalline silicon films 206-1, 206-2, and 206. The bit lines B ₁ and B ₂ formed by the first layer aluminum wiring 211 are connected to one of the source / drain regions of T ₃ and T ₄ via a contact hole C ₁ , respectively. The gate electrodes T _{3 to} T ₄ are connected and also serve as a part of the word line W. That is, word line W is formed of polycrystalline silicon film 206 and second-layer aluminum interconnection 212 connected to polycrystalline silicon film 206. The gate electrodes (206-1 and 206-2) of T ₁ and T ₂ are in direct contact with the N-type diffusion layers by direct contact DC. High resistance load element R
_1, R ₂ is made, a polycrystalline silicon film 210a that is heavily doped high-resistance polycrystalline silicon film 210 (connected to the gate electrode (206-1 and 206-2) in the through hole C ₂₎ Power supply line V _CC .

Next, a method of forming the SRAM cell will be described.

As shown in FIG. 5A, the surface of a P-type silicon substrate 201 is selectively oxidized (LOC), which is a known technique.
OS) method to form an element isolation oxide film 202 of 300 to 400 nm.
Formed to a thickness of After the gate oxide film 203 of the CMOS transistor is grown, a resist mask 204 is applied using a known light exposure technique to remove the portion of the gate oxide film 203 that will be in direct contact, and the silicon surface is removed by wet etching. The resist mask 204 is removed, and the resist mask 204 is removed as shown in FIG. Next, as shown in FIG. 5C, a polycrystalline silicon film 206 serving as a CMOS gate electrode is grown to a thickness of 150 to 300 nm by a known CVD technique. At this time, phosphorus is thermally diffused into the polycrystalline silicon film 206 to have an n conductivity type. Next, using a known light exposure technique, FIG.
As shown in FIG. 5C, a resist mask 207 is applied to leave a portion of the polycrystalline silicon film 206 to be a gate electrode, and the polycrystalline silicon film 206 is patterned by a well-known dry etching technique.
As shown in (d), the gate electrodes 206-1, 206-
Form 2 Next, arsenic ions or the like are implanted and heat treatment is performed to form an N-type diffusion layer 209 and a direct contact DC. Next, a first interlayer insulating film (not shown) is deposited, a through hole C ₂ is formed, a high-resistance polycrystalline silicon film 210 is deposited, and arsenic ions are selectively implanted to form a power supply line V _CC. To form high resistance load elements R ₁ and R ₂ by forming an N ⁺ type polycrystalline silicon film 210a and patterning. Next, the second not shown
Depositing the interlayer insulating film (not shown), to form a contact hole C _1, the first layer aluminum wiring 211
(B ₁ ) is formed, a third interlayer insulating film (not shown) is deposited, a through hole (not shown) reaching a gate electrode (206) also serving as a part of a word line is provided at a predetermined position, and a second layer aluminum wiring 212 is formed. (W) is formed.

[0010]

In the first conventional example, after a polycrystalline silicon film is deposited on the entire surface of the substrate, it is necessary to perform isotropic etching to leave the single crystal silicon film 108a in the gap. In addition to increasing the number of steps, the surface of the substrate on which the intrinsic base region 112 is formed is necessarily etched. However, it is difficult to control the dimensions of the substrate.
There is a problem that the yield of bipolar transistors is easily reduced. On the other hand, in the formation of the direct contact of the second conventional example, when patterning the gate electrode,
Unnecessary grooves are formed by always etching the silicon substrate around the direct contact, so that there is a problem that the parasitic resistance between the direct contact and the source / drain is easily increased.

Therefore, an object of the present invention is to form a polycrystalline silicon electrode or wiring partially contacting the surface of the semiconductor substrate at an opening provided in an insulating film covering the surface of the semiconductor substrate. It is an object of the present invention to provide a method for manufacturing a semiconductor integrated circuit which can be formed without etching.

[0012]

According to a method of manufacturing a semiconductor integrated circuit of the present invention, an insulating film having a predetermined thickness is formed on a surface of a semiconductor substrate, and a polycrystalline silicon film is deposited. Forming a gap of a predetermined dimension between the polycrystalline silicon film and the semiconductor substrate by wet-etching the patterned and exposed insulating film; and 1 × 10 ^−7.
Heating the polycrystalline silicon film to a semiconductor substrate by heating at a temperature of 700 ° C. or more under an ultra-high vacuum of less than Pa to eliminate the gap. In this case, a polycrystalline silicon film can be deposited without intentionally doping impurities.

[0013] Further, heating is performed while supplying B ₂ H ₆ gas to bring the polycrystalline silicon film into contact with the semiconductor substrate. After doping the polycrystalline silicon film with a P-type impurity, the polycrystalline silicon film is heated again and heated. A P-type diffusion layer can be selectively formed in the portion as a graft base region of the bipolar transistor.

Further, after the polycrystalline silicon film is brought into contact with the semiconductor substrate, an N-type impurity is introduced into the polycrystalline silicon film, and the polycrystalline silicon film is heated again to selectively deposit N-type on the surface of the semiconductor substrate.
The type diffusion layer can be formed as a direct contact connecting to the source / drain region of the MOS transistor.

The insulating film is wet-etched to form a gap, and the polycrystalline silicon film is brought into contact with the semiconductor substrate surface by heat treatment under ultrahigh vacuum, so that the semiconductor substrate surface is hardly etched.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described.

An N ⁺ -type region is selectively provided on the surface of a P-type silicon substrate having a (100) surface, and an N-type epitaxial layer 1 having a thickness of 1.0 μm is formed as shown in FIG.
A P-type region (not shown) for element isolation is formed on the silicon substrate 101 on which the element 01-1 has been grown, a P-well (not shown) and an N-well 10-2 (not shown) are formed. It is formed to a thickness of 400 nm. Then, the gate oxide film 10 of the CMOS transistor
3 is grown from 7 nm to 15 nm, for example, 7 nm, and then CMOS
The polycrystalline silicon film 104A serving as a gate electrode and a bipolar base electrode is formed by a known CVD technique.
It grows with a thickness of 0-300 nm. At this time, no impurity is added to the polycrystalline silicon film 104A. Next, in order to electrically insulate the emitter electrode and the base electrode, an insulating film 105 such as a silicon nitride film is grown on the polycrystalline silicon film 104A to a thickness of 100 to 200 nm.
Thereafter, a mask is applied to a region other than the region where the base and the emitter of the bipolar transistor are formed by using a known light exposure technique, and the insulating film 1 is formed by a known dry etching technique.
05 and the polycrystalline silicon film 104A are removed. As a result, a hole for connecting the emitter electrode, that is, an emitter contact 106 is opened. However, since the gate oxide film 103 serves as a stopper for etching the polycrystalline silicon film 104A, a CMOS is formed on the upper surface of the region where the base and the emitter of the bipolar transistor are formed.
Of the gate oxide film 103 remains. Therefore, the gate oxide film 103 under the polycrystalline silicon film 104A is formed.
In the horizontal direction by a known wet etching technique.
About 200 to 200 nm is removed. As a result, a gap 107 having a gate oxide film thickness is formed horizontally below the polycrystalline silicon film 104A.

Next, in a UHV-CVD apparatus, 1 × 1
After ultra-high vacuum with a pressure of 0 ^-8 Pa or less, a small amount of B ₂
While supplying only the H ₆ gas, the substrate is subjected to a heat treatment at a temperature of 700 ° C. or more, for example, 750 ° C. for about 5 minutes in an ultra-high vacuum of 1 × 10 ⁻⁷ Pa or less. Self-diffusion of silicon atoms through the grain boundaries in the polycrystalline silicon occurs, and the side wall portions opening the polycrystalline silicon are curved, making physical contact with the substrate, and as shown in FIG. Near the interface of the N-type epitaxial layer 101-1 where
In 19, it becomes a single crystal. In the vicinity of the interface, boron is doped to become P-type. In this reaction process, the degree of vacuum and temperature are important. At a pressure of 1 × 10 ⁻⁷ Pa or more, or at a substrate temperature of 700 ° C. or less, the above-mentioned reaction hardly occurs. Although the reason for this is not clear, the self-diffusion of silicon atoms through the grain boundaries of the polycrystalline silicon film is more likely to be rate-determined by increasing the supply of B ₂ H ₆ gas to the substrate surface under high temperature and reduced pressure. Also, the crystal grains of polycrystalline silicon become smaller as the temperature becomes higher, which also has an effect that the crystal grains tend to be mainly composed of the (100) plane of silicon. In the above-described reaction process, B ₂ H ₆ gas is supplied. This serves to promote the surface cleaning without adding impurities. In this reaction process, the impurity concentration in the polycrystalline silicon film 104A is an important parameter in addition to the degree of vacuum and the temperature. In particular, it is desirable that the concentration of boron contained in the polycrystalline silicon is low, but an undoped polycrystalline silicon film formed without intentionally doping impurities by a CVD method usually used in the semiconductor field may be used.

The thickness of the gap 107 and the distance in the horizontal direction are important because they affect the contact resistance. However, if the thickness of the gate insulating film 103 is 15 nm and the horizontal distance is 500 nm, the above-mentioned ultra-high vacuum may be used. It was possible to fill with silicon by heat treatment. Therefore, it can be used for forming a link base of a bipolar transistor in BiCMOS.

In FIG. 1B, the curvature at the opening of the polycrystalline silicon film 104A is exaggerated for easy understanding.

Next, in the same manner as in the conventional example, as shown in FIG. 1C, an intrinsic base region 112 and a collector lead region (not shown) are formed, and a spacer 109A is formed.
^{A +} -type polycrystalline silicon film 110 and a silicon oxide film 111 are formed and patterned to form an emitter electrode. Next, the polycrystalline silicon film 104A is patterned to
As shown in (d), the base electrode 113 and the gate electrode 1
14 are formed, spacers 115 are formed, and BF ₂ ⁺ is implanted. This is because the gate electrode 114 and the base electrode 113 are doped and a pair of source / drain regions 116 are formed. Next, heat treatment is performed at 900 ° C.
An emitter region 117, a graft / base region 118, and a source / drain region 116 are formed.

The silicon film 108 described in the first conventional example
Contact hole 10 when etching is performed.
In part 6a, the N-type epitaxial layer 101-1 of the semiconductor substrate is used.
Can be avoided. When the gate oxide film 103 is removed by wet etching, a sufficient selectivity can be obtained, so that the exposed surface of the N-type epitaxial layer 101-1 is hardly etched. or,
Since heat treatment under ultra-high vacuum may be performed instead of formation and etching of the silicon film 108, the number of steps is reduced.

Next, a second embodiment of the present invention will be described.

As shown in FIG. 2A, an element isolation oxide film 202 is formed on the surface ((100) surface) of a P-type silicon substrate 201 by a known selective oxidation (LOCOS) method.
It is formed to a thickness of 00 to 400 nm. And CMOS
The gate oxide film 203 of the transistor is 7 nm to 15 n
After growth of, for example, 7 nm, the polycrystalline silicon film 206 serving as a CMOS gate electrode is
It grows to a thickness of 50 to 300 nm. At this time, no impurity is added to the polycrystalline silicon film 206. Using a known light exposure technique, a resist mask 213 is applied so as to leave a portion of the polycrystalline silicon film 206 serving as a gate electrode.
The polycrystalline silicon film 206 is removed by a known dry etching technique. Thus, gate electrodes 206-1 and 206-2 are formed as shown in FIG.
However, the gate oxide film 203 is
Cl ₂ or HBr so as to serve as a stopper for etching
By using such a gas, the gate oxide film 203 of the CMOS is left over the region where the direct contact is formed. Next, as shown in FIG. 2C, a resist mask 214 is applied using a known light exposure technique in order to prevent the gate oxide film of the MOS transistor from being removed by wet etching. Thereafter, the gate oxide film 203 in the direct contact formation region is formed.
In the horizontal direction by a known wet etching technique.
About 200 to 200 nm is removed. As a result, a gap 215 having a gate oxide film thickness is formed horizontally below the polycrystalline silicon film 206-1.

Next, the resist mask 214 is removed and U
The substrate is subjected to a heat treatment for several minutes at a temperature of 700 ° C. or more, for example, 800 ° C. in a high vacuum at a pressure of 1 × 10 ⁻⁷ Pa or less in an HV-CVD apparatus or the like. Self-diffusion of silicon atoms through the grain boundaries in the polycrystalline silicon occurs, and the side wall portions opening the polycrystalline silicon are curved and physically contact the substrate as shown in FIG. Part 2
16 are formed. Single crystal is formed near the interface with the silicon substrate 201. In this reaction process, the degree of vacuum and temperature are important. If the degree of vacuum is 1 × 10 ⁻⁷ Pa or more, or if the substrate temperature is 700 ° C. or less, the above-mentioned reaction hardly occurs. Although the reason for this is not clear, the high temperature and low pressure make it easier for the self-diffusion of silicon atoms through the grain boundaries of the polycrystalline silicon film to be rate-determined, and the polycrystalline silicon crystal grains become smaller as the temperature increases, The fact that the (100) plane is mainly used also has an effect. In this reaction process, the impurity concentration in the polycrystalline silicon film 206 is an important parameter in addition to the degree of vacuum and the temperature. In particular, it is desirable that the concentration of boron contained in the polycrystalline silicon is low, but an undoped polycrystalline silicon film formed without intentionally doping impurities by a CVD method usually used in the semiconductor field may be used.

The thickness and the horizontal distance of the gap 215 are important because they affect the contact resistance. However, when the thickness of the gate insulating film 103 is 15 nm and the horizontal distance is up to 500 nm, the above-mentioned ultra-high vacuum can be used. It was possible to fill with silicon by heat treatment. Therefore, SRA of 4 Mbits or more
Can be used for M.

Next, as shown in FIG. 2E, a resist mask 217 is provided for doping the gate electrodes 206-1 and 206-2, and phosphorus ions are implanted. Next, the resist mask 217 is removed, ion implantation of arsenic is performed, and heat treatment is performed, so that the N-type diffusion layer 20 is formed.
9 and direct contact DC. The following steps are exactly the same as in the second conventional example.

In the second conventional example, the trench 208 is formed by etching the silicon substrate during the patterning of the polycrystalline silicon film 206 for forming the gate electrode. There is no. That is, the gate oxide film is used as an etching stopper during patterning for forming the gate electrodes 206-1 and 206-2, and the gap 215 is formed by wet etching with a good selectivity. Accordingly, the parasitic resistance between the direct contact and the source / drain does not increase, so that the operation speed of the SRAM is not impaired.

Although the link base and the direct contact of the SRAM have been described above as examples, the present invention is applicable to any electrode or wiring made of a polycrystalline silicon film which is in direct contact with a part of the exposed surface of the semiconductor substrate. Can.

[0030]

As described above, the surface of the semiconductor substrate is covered with a thin insulating film such as a gate oxide film, and a polycrystalline silicon film is deposited and patterned to expose the surface of the insulating film. After removing the insulating film under the polycrystalline silicon film edge by wet etching,
Since the polycrystalline silicon film and the semiconductor substrate can be brought into contact by heat treatment under ultra-high vacuum, the problem of etching the surface of the semiconductor substrate during the patterning can be avoided. Accordingly, it is possible to prevent variations in the shape of the contact portion between the semiconductor substrate and the electrode or the wiring made of the polycrystalline silicon film and the vicinity thereof, and it is possible to manufacture a semiconductor integrated circuit with high yield.

[Brief description of the drawings]

FIGS. 1A to 1D are cross-sectional views illustrating a first embodiment of the present invention in the order of steps, which are separately illustrated in FIGS.

FIGS. 2A to 2F are cross-sectional views in the order of steps for explaining a second embodiment of the present invention.

FIGS. 3A to 3C are views for explaining a first conventional example.
FIG. 6E is a sectional view in a process order, which is separately illustrated in FIG.

FIG. 4 is a plan view showing an example of an SRAM cell (FIG. 4)
(A)) and a circuit diagram (FIG. 4 (b)).

FIGS. 5A to 5C are views for explaining a second conventional example.
FIG. 6E is a sectional view in a process order, which is separately illustrated in FIG.

[Explanation of symbols]

Reference Signs List 101 silicon substrate 101-1 n-type epitaxial layer 101-2 n-well 102 field oxide film 103 gate oxide film 104, 104a polycrystalline silicon film 105 silicon oxide film 106 emitter contact hole 107 gap 108 silicon film 108a single crystal silicon film (link) Base) 109, 109A Spacer 110 N ⁺ -type polycrystalline silicon film 111 Silicon oxide film 112 Intrinsic base region 113 Base electrode 114 Gate electrode 115 Spacer 116 Source / drain region 117 Emitter region 118 Graft / base region 119 Near interface 201 Silicon substrate 202 Field oxide film 203 Gate oxide film 204 Resist mask 205 Silicon surface 206 Polycrystalline silicon film 206-1, 206-2 Gate electrode (polycrystalline Silicon film) 207 resist mask 208 the grooves 209 source and drain regions 210 high-resistance polycrystalline silicon film 210a N ⁺ -type polycrystalline silicon film 211 first layer aluminum interconnection (bit line) 212 second layer aluminum wiring (word line) 213 resist Mask 214 Resist mask 215 Gap 216 Direct contact part 217 Resist mask B ₁ , B ₂ Bit line R ₁ , R ₂ High resistance load element T _{1 to} T ₄ MOS transistor V _CC power supply line W Word line

Claims (4)

(57) [Claims] A step of forming an insulating film having a predetermined thickness on a surface of a semiconductor substrate and depositing a polycrystalline silicon film; and a step of patterning the polycrystalline silicon film and wet-etching the exposed insulating film to form the polycrystalline silicon film. Forming a gap of a predetermined size between the silicon film and the semiconductor substrate; 1 × 10 ⁻⁷
Heating the semiconductor substrate at a temperature of 700 ° C. or higher under an ultra-high vacuum of less than Pa to bring the polycrystalline silicon film into contact with a semiconductor substrate to eliminate the gap. 2. The method according to claim 1, wherein the polycrystalline silicon film is deposited without intentionally doping impurities. 3. The semiconductor substrate is heated by supplying a B ₂ H ₆ gas to bring the polycrystalline silicon film into contact with the semiconductor substrate. After doping the polycrystalline silicon film with a P-type impurity, the polycrystalline silicon film is heated again to heat the surface of the semiconductor substrate. 3. The method for manufacturing a semiconductor integrated circuit according to claim 1, wherein a P-type diffusion layer is selectively formed as a graft base region of the bipolar transistor. 4. An N-type impurity is introduced into the polycrystalline silicon film after the polycrystalline silicon film is brought into contact with a semiconductor substrate,
3. The method of manufacturing a semiconductor integrated circuit according to claim 1, wherein heating is performed again to selectively form an N-type diffusion layer on a surface portion of the semiconductor substrate as a direct contact connected to a source / drain region of a MOS transistor.