JPH0621462A - Thin-film transistor - Google Patents

Abstract

PURPOSE:To facilitate manufacture of an integrated circuit highly packed with thin-film transistors. CONSTITUTION:A thin-film transistor comprises a gate electrode 103 on an insulating film 102, a gate oxide 105 formed on the side wall of an opening in the gate electrode and gate insulator, an active polysilicon 106 opposed to the gate electrode along the gate electrode, and heavily dope regions 107 formed around the top and bottom of the opening in the active polysilicon. The transistor has a vertical structure, in which current flows in the active polysilicon between the heavily doped regions.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a thin film transistor using polysilicon.

[0002]

2. Description of the Related Art Thin film transistor (TFT) using polysilicon formed at a temperature of about 600 ° C. as an active layer
Has a feature that it can be easily formed even on an insulator whose base is not crystalline, and has good coverage for the stepped shape of the base. Therefore, it is possible to interpose an interlayer insulating film on the upper layer of a transistor formed on a silicon substrate. It is used by stacking.
In particular, since it can be manufactured by a heat treatment process at a lower temperature than the current manufacturing process of an LSI in which a transistor made on a silicon single crystal substrate is integrated, the thermal effect given to the transistor on the base substrate made at this previous process There is no influence, and there is a feature that a device having a three-dimensionally stacked structure can be easily configured.

Further, the thin film transistor is characterized in that its electric mobility is smaller than that of a single crystal, so that the internal resistance as a circuit element is large, and the function on the circuit is a load for switching operation. It has desirable properties as an element. For example, in a static type memory device composed of a memory cell using a flip-flop circuit, by replacing it with a high resistance element which is a simple passive element before that,
The effect of reducing the current consumption in the data holding state and improving the operation speed is shown.

9A and 9B are views showing the structure of the transistor. FIG. 9A is a plan view and FIG. 9B is a sectional view taken along line CC. As shown in the figure, a base wiring polysilicon 201 is formed on a base insulating layer 200 such as an oxide film on a silicon substrate, and a CVD oxide film 202 is deposited thereon as an interlayer insulating film. Further, after the gate polysilicon 203 is processed into a desired shape and a gate oxide film 205 is deposited thereon, the gate oxide film 205 and the CVD oxide film 202 are opened for connection with the underlying wiring polysilicon 201. Then, a TFT active layer polysilicon 206 is deposited, a region is set by using a lithographic technique, and carrier impurities are ion-implanted to form a polysilicon high concentration region 20.
Forming 7. Incidentally, 204 is a CVD oxide film, 210
Is wiring aluminum.

In order to form a circuit by integrating such transistors at a high density, it is necessary to devise a layout. In this example, the underlying wiring polysilicon 201 is provided to connect to one of the polysilicon high-concentration regions 207, and the other is connected to the wiring layer aluminum 210. In such an arrangement, since the underlying wiring polysilicon 201 can be arranged as a lower layer of the TFT active layer polysilicon 206, there is a high degree of freedom in wiring layout, and since it can be arranged by stacking with substantially the same size, the occupied area is reduced. It can also contribute to the improvement of the degree of integration without increasing the number.

[0006]

In such a transistor structure, at least the length of the gate electrode in the width direction is
The size of the transistor layout is limited and further miniaturization is not possible. Further, in such a thin film transistor having a lower gate structure, since the polysilicon high concentration region 207 needs to be formed in alignment with the gate polysilicon 203, not only the processing itself of the gate polysilicon 203 but also the polysilicon high concentration region 207 is performed. The lithography technique and the dry etching technique for forming the concentration region 207 have to be performed with high accuracy, and there is a problem that manufacturing becomes difficult. It is an object of the present invention to provide a thin film transistor that enables miniaturization of the transistor to achieve high integration and facilitates manufacturing.

[0007]

According to the present invention, there is provided a gate electrode formed on an insulating film, a gate insulating film formed on a side surface of an opening formed in the gate electrode and the insulating film, and the gate insulating film. The active layer polysilicon is formed along the film so as to face the gate electrode, and the high-concentration region is formed in the active-layer polysilicon around the bottom and the upper portion of the opening. The active layer polysilicon is used as a current path.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. 1A and 1B show a first embodiment of the present invention. FIG. 1A is a plan view and FIG. 1B is a sectional view taken along the line AA. Polysilicon base wiring 10 on the base insulating film 100 on the silicon substrate.
1 and the gate polysilicon 103 is provided on this via the CVD oxide film 102. Then, a gate oxide film 105 is provided on the side surface of the gate polysilicon 103, a TFT active layer polysilicon 106 is provided along the gate oxide film 105, and a polysilicon high concentration region 107 is formed on this. There is. Incidentally, 104 and 108 are CVD oxide films.

2 and 3 are sectional views showing the manufacturing method of FIG. 1 in the order of steps. First, as shown in FIG. 2A, a doped polysilicon having a thickness of 0.2 μm and a layer resistance of 100 Ω / □ is deposited on the underlying insulating layer 100, and is processed to form an underlying wiring polysilicon 101. . Further thickness on the entire surface
A 0.2 μm thick CVD oxide film 102 and a 0.3 μm thick undoped polysilicon layer are deposited, and a high concentration of phosphorus is doped by phosphorus diffusion at 875 ° C. A gate polysilicon 10 is formed by performing a shape processing on this polysilicon.
3 is formed, and then a 0.2 μm thick CVD oxide film 104 is deposited on the entire surface.

Next, as shown in FIG. 2B, the resist 1
With 10 as a mask, by dry etching technology,
This laminated film is subjected to opening processing to expose the surface of the underlying wiring polysilicon 101 on the bottom surface thereof. Further, as shown in FIG. 2C, after a gate oxide film having a thickness of 300 Å is deposited on the entire surface, the gate oxide film 105 is left only on the sidewalls by anisotropic etching on the entire surface, and again on the bottom of the opening shape. The underlying wiring polysilicon 101 is exposed. After that, a TFT active layer polysilicon 106 having a thickness of 500 Å is deposited on the entire surface.

Next, as shown in FIG. 2D, arsenic is ion-implanted into the TFT active layer polysilicon 106 at an accelerating voltage of 50 KeV with a dose amount of 10 16 to the power of 1 cm 2. Polysilicon high-concentration regions 107 to be the source / drain of the transistor are formed in the TFT active layer polysilicon 106. Then, FIG. 3 (a)
As described above, the TFT active layer polysilicon 105 is processed into a shape by the lithography technique using the resist 110 and the dry etching technique, and separated into individual transistors. After that, as shown in FIG. 3B, a CVD oxide film 108 having a film thickness of 0.5 μm is deposited, and an opening process is performed using a resist 110. Furthermore, as shown in FIG. 3C, the thickness is 0.6
A wiring aluminum 109 of μm is formed in a required pattern.

In the thin film transistor of this structure, the thin film transistor is formed along the side surface of the opening having a cylindrical shape, and the high concentration polysilicon region 107 is formed on the bottom surface or the upper portion of the opening of the thin film transistor. Moreover, in the high concentration region 107, connection between adjacent transistors is made. Therefore, even if the width direction of the gate is increased, it is not necessary to increase the dimension in the plane direction, so that the transistor can be miniaturized and high integration can be achieved. In addition, the polysilicon high concentration region 10
The formation of 7 can be performed in a self-aligned manner by utilizing the opening, and alignment with a photolithography technique or the like is unnecessary, and high precision formation is possible.

In the above-described embodiment, arsenic, which is an n-type impurity, is used as a carrier impurity for forming the polysilicon high-concentration region 107 of the thin film transistor, but phosphorus may be used or a p-type impurity such as boron may be used. it can. Also, for the TFT active layer polysilicon 106,
For the purpose of controlling the operating threshold value of the transistor, it is effective to perform additional ion implantation of about 10 12 per square centimeter.

FIG. 4 shows a second embodiment of the present invention (a).
Is a plan view and (b) is a cross-sectional view taken along the line BB. The same parts as those in FIG. 1 are designated by the same reference numerals. In this embodiment, one polysilicon high concentration region 107 of the thin film transistor is connected to the electrode of the capacitor element formed on the underlying silicon substrate 400 to form an integrated structure. That is, a groove is provided in the silicon substrate 400, a substrate high-concentration region 401 is formed on the inner surface of the groove, a capacitor insulating film 402 is formed on the inner wall of the groove, and a capacitor electrode polysilicon 403 is buried in the groove. Capacitance electrode polysilicon 40
3 is in direct contact with the high polysilicon concentration region 107.

FIG. 5 is a sectional view showing a process for manufacturing the structure shown in FIG. First, as shown in FIG.
Using resist 410, depth 3μm, diameter 0.6μm
The groove shape is processed. Next, as shown in FIG. 5B, a thermal oxide film having a thickness of 80 Å is formed on the entire surface of the capacitive insulating film 40.
2 is formed, then arsenic is ion-implanted at an incident angle of 20 degrees to form a substrate high-concentration region 401 on the entire surface including the groove-shaped side wall and bottom surface. Then, as shown in FIG. 5C, a capacitor electrode polysilicon 403 is deposited on the entire surface to a thickness of 1 μm, and doping is performed by phosphorus diffusion.
As shown in (d), the entire surface of the polysilicon is etched, and the surface is flattened and the portion other than the groove shape has a thickness of 0.3 μm.
The thickness is reduced to m, and then the resist 410 is used for shape processing.

Since the underlying electrode layer similar to that of the first embodiment is formed by the steps up to this point, a thin film transistor is laminated on the underlying layer in the same manner as in the first embodiment. , The thin film transistor of FIG. 4 is formed. With this transistor structure, since the bottom surface of the thin film transistor can be connected to the electrode of the capacitor, a memory element with extremely high degree of integration can be formed.

FIG. 6 shows a sectional view of the manufacturing process of the third embodiment of the present invention. First, as shown in FIG. 6A, FIG.
It is formed in the same manner as the manufacturing process of the first embodiment shown in FIG. Then, as shown in FIG. 6B, the uppermost oxide film 1
08 is etched back using a dry etching technique having a sufficient selection ratio with respect to polysilicon,
The high polysilicon concentration region 107 in the opening is exposed.
After that, pad polysilicon 601 is deposited on the entire surface by growth of doped polysilicon having a thickness of 0.2 μm and a layer resistance of 100 Ω / □, and shape processing is performed by using a dry etching technique.

Then, as shown in FIG.
After depositing a CVD oxide film 602 of 0.3 μm, an opening process is performed on the pad polysilicon 601 to form a wiring aluminum 109. As described above, in the third embodiment, the pad polysilicon 601 is provided to form the contact region above the opening. In the transistor having this structure, the contact region of the thin film transistor can be formed in multiple layers in a planar arrangement together with the bottom surface, and the planar occupied area can be further minimized. Further, since the contact region is flattened, it can be configured as a multi-layered laminated structure as shown in FIG. 7A, for example. Alternatively, as shown in FIG.
A structure in which the gates are shared and the contact regions are arranged close to each other is also possible.

FIG. 8 shows a vertical sectional view of the manufacturing process of the fourth embodiment of the present invention. As the filling of the opening, C is used in the third embodiment.
Although a VD oxide film is used, the pad polysilicon is partially buried in the opening here. That is,
Similar to the manufacturing process of the first embodiment shown in FIGS. 3 and 4, after forming the structure of FIG. 8A, the outermost CVD oxide film 108 is formed as shown in FIG. 8B. The entire surface is etched back using a dry etching technique having a sufficient selection ratio with respect to polysilicon to expose the high-concentration polysilicon region 107 in the opening and further dig into the inside. After that, a CVD oxide film 801 having a thickness of 400 Å is deposited on the entire surface and removed except the opening and its periphery, and the same pad polysilicon 601 as in the third embodiment is formed on the entire surface with a thickness of 0.2 μm. accumulate.

Then, as shown in FIG. 8C, the thickness is 0.3 μm.
m CVD oxide film 602 is deposited, opening processing is performed, and wiring aluminum 109 is formed on the pad polysilicon 601.
To form a contact with. Although the number of manufacturing steps is increased in this embodiment as compared with the third embodiment, the back gate effect can be obtained by setting the buried pad polysilicon to the drain potential, and the on-current increases about 5 times. For example, the driving capability of the thin film transistor can be improved.

[0021]

As described above, according to the present invention, since the thin film transistor is formed by utilizing the side surface of the opening,
Miniaturization is possible without being restricted by the gate width dimension, and high integration can be realized. In addition, the high-concentration regions as the source / drain can be formed in a self-aligned manner, and the manufacturing precision of the photolithography technique or the etching technique can be relaxed.

[Brief description of drawings]

FIG. 1 is a plan view and a cross-sectional view taken along line AA of a first embodiment of a thin film transistor of the present invention.

2A to 2D are cross-sectional views showing a method of manufacturing the transistor of FIG. 1 in process order.

FIG. 3 is a cross-sectional view showing a continuation of the step of FIG.

FIG. 4 is a plan view and a sectional view taken along line BB of the second embodiment of the present invention.

5A to 5D are cross-sectional views showing a method of manufacturing the transistor of FIG. 4 in order of steps.

FIG. 6 is a cross-sectional view showing the manufacturing method of the third embodiment of the present invention in the order of steps.

FIG. 7 is a cross-sectional view showing an application example of the third embodiment.

FIG. 8 is a cross-sectional view showing the manufacturing method of the fourth embodiment of the present invention in the order of steps.

FIG. 9 is a plan view and a cross-sectional view taken along line CC of a conventional thin film transistor.

[Explanation of symbols]

 101 Underlying Polysilicon 102 CVD Oxide Film 103 Gate Polysilicon 104 CVD Oxide Film 105 Gate Oxide Film 106 TFT Active Layer Polysilicon 107 Polysilicon High Concentration Region 108 CVD Oxide Film 109 Wiring Aluminum

Claims (1)

[Claims] 1. A gate electrode formed on an insulating film, a gate insulating film formed on a side surface of an opening formed in the gate electrode and the insulating film, and the gate electrode along the gate insulating film. An active layer polysilicon formed so as to face the active layer polysilicon, and high concentration regions formed in the active layer polysilicon around the bottom and the upper portion of the opening, and the active layer polysilicon between the high concentration regions. Is a current path.