JP2705146B2 - MOS type semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS semiconductor device, and more particularly, to a MOS semiconductor device in which a source or a drain has a capacitance.

[Prior art] Conventionally, in the source and drain regions of a MOS transistor,
In some cases, a plate electrode was connected to increase the capacitance at that point. For example, as shown in FIG. 2, the memory cells of the static RAM include memory transistors 15, 15,
It is composed of load resistors 17, 17, and transfer gates 16, 16, and information is stored in parasitic capacitances 20, 20 at the nodes. However, miniaturization of memory cells has progressed,
When the parasitic capacitance decreases, the information in the parasitic capacitance is destroyed by irradiation with α rays or the like, and the possibility of inversion of the information stored in the memory cell, that is, the possibility of occurrence of a so-called soft error increases. Therefore, as a countermeasure, a method of providing an electrode fixed to the ground potential via a thin insulating film on a transistor constituting a memory cell and adding a stack capacitance has been adopted.

[Problems to be Solved by the Invention] In the conventional method described above, a step is generally formed on the surface of the MOS type semiconductor device due to a gate electrode, an oxide film for element isolation, or the like. As a result, the insulating film forming the stack capacitance becomes thinner, and the capacitance insulating film is liable to be damaged here. Also, if the thickness of the capacitor insulating film is increased in order to secure a withstand voltage in this portion, the area of the capacitor portion must be increased in order to add a sufficient capacity, thereby hindering high integration. .

[Means for Solving the Problems] According to the MOS type semiconductor device of the present invention, the source and drain electrodes of a MOS transistor are formed by a semiconductor layer selectively epitaxially grown to the same height as the gate electrode, and
A step in the S transistor is eliminated, and a stack capacitor is provided thereon.

Example Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view showing one embodiment of the present invention. In the figure, reference numerals 8 and 9 denote N ⁻ diffusion layers and N ⁺ diffusion layers constituting source and drain regions formed in a P-type semiconductor substrate 1, and 2 denotes a field formed on the semiconductor substrate 1. oxide film, 4 and 5, on the semiconductor substrate 1, a polysilicon gate electrode and the WSi ₂ gate electrode formed via a gate oxide film 3, 6, polycrystalline silicon formed on the gate electrode 5, 7 is a side wall oxide film formed on the side surfaces of the gate electrodes 4 and 5 and the field oxide film 2, and 10 is a side wall oxide film 7
And a silicon epitaxial layer 11 formed on the source and drain regions so that the upper surfaces thereof substantially coincide with the upper surfaces of the field oxide film 2, the gate electrode 5 and the sidewall oxide film 7. Thermal oxide film formed on crystalline silicon 6 and silicon epitaxial layer 10;
Is a nitride film formed on the oxide films 2, 7, and 11, 13 is an oxide film formed on the nitride film 12, and 14 is formed on the oxide film 12 and is connected to one of the silicon epitaxial layers 10. This is a polycrystalline silicon layer.

As shown in FIG. 1, field oxide film 2, sidewall oxide film 7, silicon epitaxial layer 10 and
Since the upper surface of the WSi ₂ gate electrode 5 is formed so as to be substantially coplanar, the insulating film formed thereon can have a uniform thickness.

Here, the sum of the thicknesses of the thermal oxide film 11, the nitride film 12, and the oxide film 13 is set to be 50 nm or less and 10 nm or more. If the thickness is 50 nm or more, a large area is required to obtain a sufficient capacity.
If the thickness is less than nm, stable film formation is difficult and the withstand voltage is reduced.

Next, with reference to FIGS. 3A to 3E, a manufacturing method of the embodiment of FIG. 1 will be described. An oxide film 2 of about 600 nm is formed in an element isolation region of a P-type semiconductor substrate 1 and a gate oxide film 3 is formed on a substrate surface of an active region. Then, polycrystalline silicon, WSi ₂ , polycrystalline silicon 6, Oxide film 7 '
Is deposited, and the gate electrode and the wiring are patterned. Thereafter, phosphorus (P) is implanted at a dose of 10 ¹³ to 10 ¹⁴ cm ⁻² to form the N ⁻ diffusion layer 8 (FIG. 3A). Subsequently, an oxide film is deposited to a thickness of about 300 nm, and this is etched back to form an oxide film 7 on the gate electrode and on the side wall. Then, using this oxide film as a mask, a dose of 5 × 10 ¹⁵
Arsenic (As) of cm ⁻² is ion-implanted to form an N ⁺ diffusion layer 9 (FIG. 3B). Next, after the silicon epitaxial layer 10 is formed on the diffusion layer 9 to have the same height as the gate electrode by selective epitaxial growth, the oxide film 7 on the gate electrode is removed [FIG. 3 (c)].

Subsequently, a silicon oxide layer is formed by a thermal oxide film.
10. After forming an oxide film 11 of 10 nm or less on the polycrystalline silicon 6, a nitride film 12 of 20 nm or less is deposited thereon, and an oxide film 13 of 2 to 5 nm is further deposited thereon [FIG. (D)]. Thereafter, one diffusion layer 9 of the MOS transistor is formed.
A contact hole is formed on the top and polycrystalline silicon is
14 is deposited and then patterned [FIG. 3 (e)].

The above-mentioned contact hole is formed by plasma etching. However, during this step, the diffusion layer 9 is covered with the epitaxial layer 10, so that it is not exposed to an etching atmosphere. Therefore, according to the present invention, it is possible to prevent an increase in leakage current caused by damage to the source and drain diffusion layers.

In the above embodiments, the gate electrode was described as polycide, but the present invention is not limited to this.
Other materials such as polycrystalline silicon or silicide may be used. Also, polycrystalline silicon
14 can be appropriately replaced with another material, for example, a refractory metal, aluminum or the like.

[Effects of the Invention] As described above, the present invention eliminates a step between a gate electrode and a diffusion layer by selectively epitaxially growing a semiconductor material on a diffusion layer of a MOS transistor, and forms an insulating film of a stack capacitor there. Therefore, it is possible to prevent electric field concentration from occurring in a specific portion of the insulating film, and to reduce the thickness of the insulating film. Therefore, according to the present invention, it is possible to obtain a large-capacity stack capacitance in which the breakdown of the insulating film is suppressed. further,
According to the present invention, since the diffusion layer in the semiconductor substrate is covered with the semiconductor material grown by selective epitaxial growth, the diffusion layer is not damaged in a process such as plasma etching, and when a reverse voltage is applied to the diffusion layer. Leakage current can be suppressed.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of one embodiment of the present invention, FIG. 2 is a circuit diagram of a memory cell, and FIG. 3 is a cross-sectional view showing a manufacturing process of the device of the embodiment of the present invention. 1 ... P-type semiconductor substrate, 2 ... Field oxide film, 3 ...
... gate oxide film, 4 ... polycrystalline silicon gate electrode, 5
... WSi ₂ gate electrode, 6 ... polycrystalline silicon, 7 ... side wall oxide film, 8 ... N ^- diffusion layer, 9 ... N ⁺ diffusion layer, 10 ... silicon epitaxial layer, 11 ... thermal oxide film , 12 ... nitride film, 13 ... oxide film, 14 ... polycrystalline silicon.

Claims (1)

(57) [Claims] A semiconductor substrate of one conductivity type, a gate electrode formed on the semiconductor substrate via a gate insulating layer, and an insulating film formed on both side surfaces of the gate electrode so as to cover the gate electrode; MOS having source and drain regions of opposite conductivity type formed in the semiconductor substrate with the gate electrode interposed therebetween
In the semiconductor device, a semiconductor electrode having substantially the same height as the gate electrode is formed on each of the source and drain regions, and a thin capacitive insulating film is interposed on the semiconductor electrode and the gate electrode. And a conductor layer connected to any one of the semiconductor electrodes is formed.