JP2827377B2 - Semiconductor integrated circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly, to a stacked capacitor type memory cell of a MOS dynamic semiconductor memory device.

[Prior Art] As a memory cell of a conventional MOS type dynamic semiconductor memory device, a one-transistor one-capacitor type is mainstream, and high integration and large capacity have been achieved by reducing the size of each element. However, simply reducing the size limits the degree of integration and capacity, and reducing the size of the memory cell not only reduces the charge retention time but also increases the soft error rate, thus improving the structure of the memory cell. A stacked capacitor type memory cell in which the capacitance of the capacitor is increased is used.

FIG. 3 is a sectional view of a conventional stacked capacitor type memory cell. In FIG. 3, a stacked capacitor is provided at the intersection of a word line 3 made of a polysilicon film and a bit line 9 made of a polycide film. The capacitor of each memory cell is composed of a charge storage electrode 4, a counter electrode 6, and an insulating film 4 between these electrodes. The bit line 9 and the electrode 4 are connected to the impurity diffusion layer 2 which is a source or a drain of a MOS transistor having the word line 3 as a gate.

[Problems to be solved by the invention]

As described above, since the capacitor of the stacked capacitor type memory cell is formed on its own gate and on the field oxide film 2, the capacitance is larger than that of the ordinary one-transistor one-capacitor type memory cell. ing.

However, the demand for higher integration and larger capacity of semiconductor memory devices is still unquestionable, and even if stacked capacitor type memory cells are used as long as the conventional structure is used.
Reduction of the capacitor size cannot be avoided. As a result, problems such as a decrease in the charge retention time and an increase in the soft error occurrence rate become significant.

The present invention has been made in view of such a problem, and an object of the present invention is to provide a semiconductor integrated circuit that can effectively increase the capacitor size without increasing the two-dimensional size.

[Means for solving the problem]

In the semiconductor integrated circuit of the present invention, a groove is provided in an element formation region partitioned by a field green film formed on a surface of a semiconductor substrate, and a groove is provided on a side wall step portion of the groove and in the vicinity thereof via a green film. And a capacitor having an electrode made of a conductive film.

〔Example〕

Next, embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a sectional view of a semiconductor chip showing a semiconductor memory device having a stacked capacitor type memory cell according to an embodiment of the present invention.

First, a manufacturing method for obtaining this structure will be described below with reference to FIGS. 2 (a) to 2 (d).

First, as shown in FIG. 2A, a photoresist film 110 is formed in a region where a field oxide film is to be formed on a semiconductor substrate 101 made of P-type Si. A groove is formed by etching 1.5 μm. Next, as shown in FIG. 2 (b), after removing the photoresist film 110, a silicon nitride film 111 is formed on the entire surface of the semiconductor substrate 1, and the photoresist film 112 is patterned on the memory cell formation region. I do. By removing the silicon nitride film 111 by anisotropic etching in this state, the silicon nitride film, which is an oxide-resistant material, remains where no field oxide film is formed. Thereafter, as shown in FIG. 2C, a field oxide film 107 having a thickness of 0.5 μm is formed by oxidizing the substrate. Here, the field oxide film is formed without penetrating under the silicon nitride film (bottom of the groove) at all, and does not shrink the active region. Next, the silicon nitride film is removed. Thereafter, through a process similar to that of a normal stacked capacitor type memory cell, as shown in FIG. 2D, a word line 103 is formed after gate oxidation, and an interlayer insulating film 108 is sandwiched. Electrode for charge storage 1
Form 04. At this time, the charge storage electrode is formed from the inside of the groove to over the field oxide film 107, but the area of the charge storage electrode 4 is increased as compared with the conventional example because of the step.

Finally, as shown in FIG.
There is a groove in the element formation region defined by 7, and a memory cell can be realized in which a capacitor is provided from the side wall step of the groove to the field oxide film. Therefore, when the plane area of the semiconductor chip is the same, the capacitance of the capacitor can be increased, and the integration degree can be improved, the charge retention time can be increased, and the soft error occurrence rate can be suppressed.

The stacked capacitor type memory cell has been described above as an example. However, it is apparent that the present invention is not limited to the memory cell but can be generally applied to a semiconductor integrated circuit using a capacitor.

〔The invention's effect〕

As described above, according to the present invention, by providing the element formation region inside the groove, the capacitor can be formed by utilizing the step of the groove. Therefore, there is an effect that the degree of integration of the semiconductor integrated circuit can be improved.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a stacked capacitor type memory cell according to an embodiment of the present invention, and FIGS. 2 (a) to 2 (d) are cross-sectional views showing process steps for explaining a manufacturing method of the embodiment. ,
FIG. 3 is a sectional view showing a conventional stacked capacitor type memory cell. 1,101: Semiconductor substrate, 2,102: Impurity diffusion layer, 3,103
…… Word line, 4,104… Charge accumulation electrode, 5,105 …… Thin green film, 6,106… Counter electrode, 7,107… Field oxide film, 8,108… Interlayer green film, 9,109… Bit line, 110
...... Photoresist film, 111 ... nitride film, 112 ... photoresist film.

Claims (2)

(57) [Claims] 1. A conductive film, wherein a groove is provided in an element forming region defined by a field insulating film formed on the surface of a semiconductor substrate, and a sidewall is provided at the step portion of the groove and in the vicinity thereof via an insulating film. A semiconductor integrated circuit comprising: a capacitor having an electrode made of: 2. The semiconductor integrated circuit according to claim 1, wherein a stacked capacitor of the memory cell is provided in a region extending from a bottom surface of the groove to an adjacent field insulating film.