JPS6362370A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the area of a cell, by digging a deep groove, which does not reach a drain, in a drain hole region, and increasing the area of the side wall of a lower electrode. CONSTITUTION:A hole is provided for a drain contact region in an interlayer insulating film 7. A polycrystalline silicon layer 8 is grown. The unnecessary area of the polycrystalline silicon 8 other than the lower electrode of a capacitor is removed by anisotropic dry etching. Etching is also performed so that the polycrystalline silicon layer 8 in the drain hole part remains. As a dielectric material for the capacitor, the surface of the polycrystalline silicon 8 is oxidized, a thermal oxide film 10 is formed, a polycrystalline silicon layer 11 as the upper electrode of the capacitor and an interlayer insulating film 12 are formed, and a bit line 13 is formed so as to contact with a source diffused layer 5. Thus, the capacitance value of the capacitor is increased, the area of a cell can be reduced and miniaturization becomes easy.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device applied to manufacturing a memory cell of an MIS type dynamic RAM.

[Conventional technology]

Conventionally, the cell structure of Dynamic R/4M (hereinafter referred to as DRAM) has been a brainer type cell in which a two-dimensional cavity Ik is made of a silicon substrate and polycrystalline silicon using a thermal oxide film as a dielectric material, a groove is dug in the silicon substrate, A trench cell is created by doping the sidewalls and bottom of the trench with impurities to create a capacitor between the buried polysilicon and the trench sidewall, or by growing polycrystalline silicon directly onto the drain and thermally oxidizing it. There is a stacked capacitor type cell that forms a polycrystalline silicon layer and creates a capacitor between the polycrystalline silicon layers.

A conventional manufacturing method for a stacked capacitor type cell will be explained with reference to FIG.

A field oxide film 2 and a gate oxide film 3 are formed on the surface of a P-type silicon substrate 10, polycide gate poles 4 are arranged as gate electrodes, and an N-type impurity (for example, As) is formed.
After opening a drain contact region in the polycide gate electrode 4, a layer of polycrystalline silicon 8 doped with an impurity (for example, P) is grown (FIG. 2(a)). moreover,
The electrode area of the capacitor is formed by dry etching,
Polycrystalline silicon 8T- is used as the dielectric material of the capacitor.
A thermal oxide film 10 is formed by oxidation (see FIG. 2).
b) ). Furthermore, the upper part of the capacitor 1! A polycrystalline silicon layer 11 doped with an impurity (for example, P) is formed as a pole, an interlayer insulating film 12 is formed, and a bit line 13 is formed by contacting the source diffusion layer 5 (FIG. 2(C)).
).

[Problem that the invention seeks to solve]

DRA using the conventional semiconductor device manufacturing method described above
In the cell structure of M, since the polycrystalline silicon 8, which is the lower electrode of the capacitor, is thin, the capacitance of the sidewalls of the polycrystalline silicon 8 is small, increasing the total area as a capacitor and increasing the capacity: tt-
In order to increase the size, it is necessary to increase the area of the polycrystalline silicon 80, which has the disadvantage that miniaturization is difficult.

[Means for solving problems]

The method for manufacturing a semiconductor device of the present invention includes a step of completely introducing impurities of a second conductivity type onto a semiconductor substrate of a first conductivity type to form a source and a drain, and a step of forming a source and a drain in contact with the surface of the drain. a layer of crystalline semiconductor is grown flat on the opening region of the drain, a groove is formed in the first polycrystalline semiconductor over the region of the drain by anisotropic etching, and does not reach the drain; , a step of removing unnecessary first polycrystalline semiconductor, a step of thinly oxidizing the surface of the remaining first polycrystalline semiconductor to form an oxide film, and a step of forming a second polycrystalline semiconductor on this oxide film. The method includes steps of forming a crystalline semiconductor layer and forming a capacitive element.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a vertical cross-sectional view of a DRAM cell structure to which an embodiment of the present invention is applied. It is a drawing shown in the order of steps.

A drain contact region of the interlayer insulating film 7 is opened (FIG. 1(a)). The depth of the drain hole is about 5oooX, and the polycrystalline silicon 8ON is 3μm thick,
When grown by VD, the surface of polycrystalline silicon 80 becomes flat (FIG. 1(b)). Furthermore, apply Regismi f,
The resist on the inside of the drain opening in the lower electrode region of the capacitor and on unnecessary regions is removed by photolithography (FIG. 1(C)). Thereafter, unnecessary portions of the polycrystalline silicon 8 other than the capacitor lower part t& are removed by anisotropic dry etching, and etching is performed so as to leave the polycrystalline silicon 80 layer inside the drain opening.

Since the layer of polycrystalline silicon 8 in the drain opening region has a large thickness, a polycrystalline silicon layer 8 can be formed by one dry etching.

Furthermore, the surface of the polycrystalline silicon 80 is oxidized to form a thermal oxide film 10 as a dielectric material for the capacitor (FIG. 1(d)). Furthermore, the polycrystalline silicon layer 11 and interlayer insulating film 12'i type are left as the upper electrode of the capacitor, and a contact is made to the source diffusion j*5 to form the υ bit line 13 (
Figure 1(e)).

In FIG. 1(e), the size of the polycrystalline silicon 8 is 5 μm square, and the size of the groove inside the drain opening region is ′ft1.
Assuming that the thickness of the polycrystalline silicon 8 is 3 μm square and the thickness of the thermal oxide film 10 serving as a dielectric is 200 μm, the capacitance value of the capacitor is 172 fF. Conventional DRAM
In the capacitor forming method, if the size of the lower electrode is t-5 μm square and the thickness of the thermal oxide film is 200X, the capacitance value of the capacitor to which the present invention is applied is 93 fF compared to the conventional one. % increase. Therefore, the cell surface itR can be made smaller and miniaturization becomes easier.

Note that the capacitance value can be increased by using a two-layer structure of an oxide film and a nitride group having a high fat charge as the dielectric material of the capacitor.

Furthermore, by forming not only one groove but a plurality of grooves in the lower electrode of the capacitor within the limits of microfabrication technology, the capacitance can be further increased.

〔Effect of the invention〕

As explained above, in the present invention, polycrystalline silicon, which is the lower electrode of a capacitor, is grown thicker than the step in the drain hole region to make it flat, and then anisotropic dry etching is performed to form the inside of the train hole region. Since the depth of the groove that does not reach the drain can be increased, the side wall area of the lower electrode can be increased, which has the effect of reducing the DRAM cell area.
Furthermore, since the present invention has a stacked capacitor structure,
Another advantage is that the drain area is small, which is advantageous against soft errors that destroy cell information due to alpha rays emitted from package materials.

[Brief explanation of drawings]

FIGS. 1(a) to 1(e) are longitudinal sectional views showing the manufacturing process of a DRAM cell structure to which all embodiments of the present invention are applied;
Figures (a) to (e) are longitudinal cross-sectional views showing the manufacturing process of a DRAM cell structure by a conventional semiconductor device manufacturing method. 1... Pi silicon substrate, 2... Field oxide film, 3... Gate oxide film, 4...
...Polycide gate electrode, 5...Source diffusion layer, 6...Drain diffusion layer, 7...
Interlayer insulating film, 8...polycrystalline silicon 9...
...7 Oto V cyst, 10...Thermal oxide film, 1
1... Polycrystalline silicon layer, 12... Interlayer insulating film, 13... Bit line. Agent Patent Attorney Susumu Uchihara (,1,jj Stomach also ゝ 5- Shoulder 1 time 7: Kuzukanzetsu Gonomas Kasa 1 time

Claims (1)

[Claims] a step of introducing impurities of a second conductivity type onto a semiconductor substrate of a first conductivity type to form a source and a drain; grow flat on the region, and form a groove in the first polycrystalline semiconductor on the drain region by anisotropic etching so as not to reach the drain, and
a step of removing unnecessary first polycrystalline semiconductor; a step of thinly oxidizing the surface of the remaining first polycrystalline semiconductor to form an oxide film; and a step of forming a second polycrystalline semiconductor on this oxide film. 1. A method for manufacturing a semiconductor device, comprising the steps of forming a semiconductor layer and forming a capacitive element.