JPS62114263A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To highly integrate a semiconductor memory without decreasing its reliability by stepwisely forming a sidewall opposed to the capacitor electrode of an insular semiconductor region. CONSTITUTION:Grooves are dug by RIE on the element separating region of a P-type Si substrate 1, and a plurality of insular semiconductor regions of rectangular pattern having a stepwise sidewall 2 are formed. Since an MOS capacitor is formed by utilizing parts of three stepwise sidewalls and upper surface of the ends of the insular region, a large capacitor capacity can be performed with smaller occupying area than the conventional structure which utilizes only vertical wall. The separation between the capacitors of the adjacent memory cell is effectively achieved by an insulating film 32 buried in the deepest portion of the groove and a P<+> type layer 4 disposed under the groove, and a punch-through hardly occurs as compared with the deeper groove from the boundary of the substrate of the element separating region in the capacitor region. Accordingly, a highly integrated (d) RAM having high reliability can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor memory device in which a memory cell is constituted by - MOS transistors and one capacitor.

[Technical background of the invention and its problems]

- A dynamic semiconductor memory device in which a memory cell is composed of MOS transistors and one capacitor (
dRAM) has become increasingly highly integrated in recent years. dR
In AM, the area of the memory cell and the area of the capacitor are reduced as the integration becomes higher, and the information charge storage layer has become extremely small. As a result, problems have arisen, such as erroneous reading of information stored in memory cells or loss of information content due to charges generated in the semiconductor substrate due to alpha rays or the like.

As a method for solving such problems, several structures have been proposed that substantially increase the capacitor area without increasing the area occupied by the memory cell.

One is to dig a narrow groove in a capacitor formation region of a semiconductor substrate and use the 1lIIW of the groove to increase the capacitor area. Thereby, the capacitor capacity can be increased two to three times as much as when no trench is dug. However, with this structure, when the dRAM is further integrated, a problem arises in that charge leakage occurs between capacitors of adjacent memory cells due to bunch through or the like. A countermeasure against this problem is to increase the distance between adjacent memory cells, but this hinders higher integration and higher density of memory cells. It is also possible to make the capacitor trench shallower, but since the depletion layer tends to extend from the trench sidewalls, it is ineffective unless it is made sufficiently shallow. The present applicant has previously proposed a structure in which the area of the capacitor is increased using the groove. Its structure will be explained with reference to FIG. p-type Si
A groove 22 is formed in the element isolation region of the substrate 21.
A MOS capacitor is formed on the side wall of the island-shaped semiconductor region surrounded by 2, with a capacitor electrode 24 facing each other with a capacitor insulating film 23 interposed therebetween. More specifically, the capacitor electrode 24 is opposed to three side walls and a part of the top surface of the end portion of the island-shaped semiconductor region. An n-type layer 25 is formed on the surface of the island-shaped semiconductor region facing the capacitor electrode 24 in order to increase the capacitance.

A thick insulating film 26 for element isolation is buried in the bottom of the trench 22, and a p+ type @27 for preventing inversion is formed in the substrate below. Inside the island-shaped semiconductor region, a gate electrode 29 is formed via a gate insulator I1I28, and an n+ type layer 30.31 that becomes a source and a drain is formed.
A MOS transistor is configured.

With this structure, a large capacitor area can be realized by effectively utilizing the trench in the element isolation region fIi.

However, when dRAM is highly integrated with this structure, the trench is formed with the minimum width technically possible, but this places a limit on the depth of the trench, and the bottom of the trench is narrow and deep. It is also difficult to embed an insulating film for element isolation in the semiconductor device. Therefore, in order to obtain a capacitor capacitance above a certain value, the groove width must be increased to a certain extent.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned points, and an object of the present invention is to provide a semiconductor memory device that realizes a larger capacitor capacity with a smaller occupied area and achieves higher integration without reducing reliability. .

[Summary of the Invention] A semiconductor memory device according to the present invention is based on the structure shown in FIG. 5, and is characterized in that the sidewalls of the island-shaped semiconductor region facing the capacitor electrodes are stepped.

〔Effect of the invention〕

According to the present invention, by forming the sidewalls of the island-shaped semiconductor regions constituting the capacitor in a stepped manner, a large capacitor area can be realized without requiring a large occupied area. In addition, by providing a thick isolation insulating film at the deepest part of the element isolation groove that gradually becomes deeper and narrower in a stepped manner, capacitors of adjacent memory cells can be reliably isolated. Therefore, according to the present invention, a highly reliable and highly integrated dRAM can be obtained.

[Embodiments of the invention]

The present invention will be explained in detail below.

FIGS. 1(a)-(d) show one embodiment of the dRAM. (a) is a plan view, (b), (C) and (d)
are A-A' in (a), respectively.

They are B-8- and CC' sectional views. To explain this according to the manufacturing process, grooves are dug in the element isolation region of the p-type S+ substrate 1 by RIE, and a plurality of island-shaped semiconductor regions having a rectangular pattern having stepped sidewalls 2 are formed. A specific example of the step-shaped groove digging process will be described later. A p+ type layer 4 for preventing inversion is formed in the element isolation trench, and an element isolation insulating film 3 is buried therein. The p+ type layer 4 is formed in all the stepped grooves except for the capacitor a (FIG. 1(C)), and only in the deepest part of the capacitor region (FIG. 1(d)). be done. In addition, as the element isolation insulation I'll 3,
A thick insulating film 31 is buried in the part where the gate electrode of the MoS transistor runs so that the groove is completely flat (FIG. 1(C)), and the stepped sidewall 2 is exposed in the part where the capacitor will be formed. Insulating film 3 selectively applied only to the deepest part
2 is embedded (FIGS. 1(b) and (d)). This can be done by once completely burying the insulating film in the element isolation trench, and then partially etching the insulating film in the capacitor region so that the insulating film 32 of a predetermined thickness remains only in the deepest part.

Then, by using, for example, solid phase diffusion, the n-type 11
A capacitor insulating film 5 is formed on the surface thereof by thermal oxidation, and a capacitor electrode 7 is formed by depositing and patterning a first layer polycrystalline silicon film. After this, M
Form an oS transistor. That is, the gate insulator 118 is formed by thermal oxidation, and the second! A gate electrode 9 is formed by depositing and patterning a polycrystalline silicon film,
N1 type 110.11 which will become the source and drain are formed by ion implantation of AS. After this, it is omitted in the diagram, but
The entire surface is covered with a CVDII film according to the usual process, contact holes are made, and AR wiring is formed to complete the dRAM. The gate electrode 9 is commonly provided to memory cells in one direction and serves as a word line, and the drains of memory cells in a direction perpendicular to the word line are commonly connected by an A2 wiring, which serves as a bit line.

FIGS. 2(a) to 2(f) show an example of a process for forming an isolation trench having stepped sidewalls, with reference to the cross section of FIG. 1(b). First, as shown in <a>, a first photoresist mask 121 covering the element region is formed on the substrate 1, and the surface of the substrate is etched by RIE to form a shallow groove. In order to facilitate the next PEP process, this trench is filled with oxidized l11131 by CVD and planarized, as shown in FIG. 3(b). Then, as shown in (C), the first mask 12
A second photoresist mask 122 whose periphery is expanded more than x is formed, and RIE is performed again to form a groove deeper than the previously formed groove. This trench is again filled with an oxide film 132 by CVD and planarized, as shown in FIG.

As shown in (e), a third photoresist mask 123 whose periphery is further expanded than that of the second mask 122
, and perform R1 and E again to form a groove deeper than the second groove. The oxide film 131.1 already buried in this way
When 32 is removed, an element isolation trench having stepped sidewalls 2 is formed as shown in FIG. 3(f).

Note that the p+ type layer 4 for preventing inversion is formed using, for example, oblique ion implantation in areas other than the capacitor region and the transistor region in the steps shown in FIGS. 2(a), 2(c), and 2(f). Solid phase diffusion can also be used instead of ion implantation. After the element isolation trenches are formed as shown in FIG. 2(f), the trenches are filled with a CvD insulation layer with a flat dielectric constant, and the insulating film is selectively etched in the capacitor electrode formation region to form a predetermined thickness in the deepest part of the trenches. Make sure to leave an insulating film.

According to this embodiment, the MOS capacitor is formed using the three stepped side walls and part of the top surface of the end of the island semiconductor fRj4, so it is smaller than the conventional structure that uses only the vertical walls. A large capacitor capacity can be realized with a small occupied area. In addition, the isolation between the capacitors of adjacent memory cells is reliably achieved by the insulating film 32 buried in the deepest part of the trench and the p+ type M4 underneath. Bunch-through etc. are less likely to occur compared to the structure to be formed. Therefore, highly reliable and highly integrated dRAM,? l<obtained.

Figure 3 shows a dRAM according to another embodiment of the present invention as shown in Figure 1 (1).
).

In this embodiment, the gate electrode 9 of the MoS transistor is partially overlapped with the capacitor electrode 7, and the n+ type layer in the source region is omitted. The rest is the same as the previous embodiment. This embodiment also provides the same effects as the previous embodiment, and also has the effect that by overlapping the electrodes, the occupied area per bit becomes smaller, and the density of the dRAM can be further increased.

FIG. 4 shows a dRAM of still another embodiment, corresponding to the cross section of FIG. 1(b). In this embodiment, the substrate 1 has a laminated structure consisting of a highly doped p+ type S1 substrate 11 and a lightly doped p-type layer 12 of the same conductivity type. The element isolation trench is formed so that the deepest part thereof reaches the p1 type substrate 11.

In the case of this embodiment, the step of forming a p+ type layer for preventing inversion at the bottom of the groove is not necessary.

The present invention is not limited to the embodiments described above. For example, nR formed in the capacitor region:! Layer 5 can be omitted, although the capacitor capacity becomes slightly smaller. It is also possible to reverse the conductivity type of each part to that in the embodiment. Furthermore, in the embodiment, as an example of the process for forming element III grooves, an example was given in which deep grooves are sequentially formed from a shallow groove portion, but in contrast to this, first R is formed using a mask with a small window.
Perform IE, sequentially enlarge the mask window, and perform multiple RIs.
By performing step E, a stepped side wall can be formed in the same manner as in the example. In this case, the step of flattening the trench after each RIE step is not necessary. The pond water invention can be further modified and implemented in various ways without overcoming the spirit thereof.

[Brief explanation of drawings]

FIGS. 1(a) to (d) are diagrams showing a dRAM according to an embodiment of the present invention, FIGS. Figure 4 shows dR of another example.
FIG. 5 is a diagram showing the AM, and FIG. 5 is a diagram showing the conventional dRAM. 1...p-type 5i substrate, 2...stepped side wall, 31°3
2... Insulating film for element isolation, 4... P+ type layer for preventing inversion, 5... N type layer, 6... Capacitor insulating film, 7...
... Capacitor electrode, 8... Gate insulating film, 9...
Gate electrode, 10.11...n+ type layer. Applicant's agent Patent attorney Takehiko Suzue 1-4ζ+r Tour 1 Figure 1 Figure 3 Figure 4 Figure 5

Claims (3)

[Claims] (1) A trench is dug in an element isolation region of a substrate, and a memory cell consisting of one MOS transistor and one capacitor is integrated and formed in a plurality of island-shaped semiconductor regions surrounded by the trench, and the capacitor is A semiconductor memory device configured with a capacitor electrode facing the side wall of the island-shaped semiconductor region with an insulating film interposed therebetween, characterized in that the side wall of the island-shaped semiconductor region facing the capacitor electrode has a stepped shape. Semiconductor storage device. (2) The island-shaped semiconductor region is formed in a rectangular pattern, and the capacitor is configured with capacitor electrodes facing each other with an insulating film interposed between three side walls and a top surface of the capacitor at its longitudinal end. The semiconductor memory device according to item 1. (3) The substrate is constructed by stacking a low concentration semiconductor layer of the same conductivity type on a high concentration semiconductor substrate, and the deepest part of the groove formed with stepped sidewalls is deep enough to reach the high concentration semiconductor substrate. A semiconductor memory device according to claim 1, which is formed in a semiconductor memory device.