JPS63207173A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To increase the breakdown strength of element isolation without spreading the area of an element isolation region by forming a trench for element isolation so that the base of the trench is brought into contact with an inversion preventive layer. CONSTITUTION:Depth from the surface of a substrate 11 of two impurity buried layers is made to differ by using two epitaxial growth layers 15, 17. That is, an impurity is introduced selectively to the semiconductor substrate 11 to form an inversion preventive layer 14, a first semiconductor film is grown onto the substrate 11 in an epitaxial manner, and the impurity is introduced selectively to the semiconductor film to shape a collector buried layer 16 for a bipolar transistor. A second semiconductor film is grown onto the first semiconductor film in the epitaxial manner, and the first and second semiconductor films are etched in response to an element isolation region to shape a trench 21 reaching the first buried layer 14. Consequently, the trench 21 is formed so that the base of the trench 21 for element isolation is brought into contact with the inversion preventive layer 14. Accordingly, the breakdown strength of element isolation can be increased.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor device in which a bipolar transistor and a MOS transistor are formed on the same substrate, and particularly relates to a collector buried layer of a bipolar transistor and an element isolation layer. The present invention relates to a method of manufacturing a semiconductor device in which the process of forming a region inversion prevention layer is improved.

(Prior Art) In recent years, with advances in semiconductor technology, particularly advances in microfabrication technology, semiconductor storage devices such as MOS type memories have become highly integrated. In DRAMs in which memory cells are constructed from MOS transistors and MOS capacitors, the area of MOS capacitors that store information decreases as the degree of integration increases, and therefore the amount of charge stored in the MOS capacitors decreases. As a result, problems arise when the memory contents are read out incorrectly or when the memory contents are destroyed by radiation such as alpha rays.

- In order to solve this problem, a trench is dug in the capacitor formation region to substantially increase the surface area without increasing the occupied area, thereby increasing the capacitance of the MOSJFt passacitor, thereby increasing the amount of stored charge. Therefore, methods for miniaturizing memory cells have been proposed.

Similarly, a reduction in the area of the element isolation region causes leakage between elements, resulting in a reduction in isolation voltage between elements, which is also a major problem. For this reason, methods have been proposed to increase the isolation voltage without increasing the occupied area by digging a trench in the element isolation region and burying an insulating film or selectively thermally oxidizing only the bottom of the trench. There is.

Figure 2 shows a memory cell that has already been proposed (Japanese Patent Laid-Open No. 1983-
72161), (a> is a plan view, (
b) is a sectional view taken along arrow AA'. A groove 42 is formed in the element valve w1 region of the p-type S1 substrate 41.
A plurality of island-like regions separated by are formed in an array. A thick insulating film 44 for element isolation is buried halfway at the bottom of the trench 42 . Furthermore, in order to improve the withstand voltage of the element isolation region, a p+ type scattering layer 4 is provided at the bottom of the full 42
3 are formed. The memory capacitor is formed by forming a capacitor insulating film 46 on the sidewalls and top surface of this element isolation trench 42, and disposing a capacitor electrode 47 so as to fill this trench 42. An n-type diffusion layer 45 serving as a counter electrode is formed in a region of the substrate A facing the capacitor electrode 47. Then, a gate electrode 49 is formed on the island-shaped semiconductor region via a gate insulating film 48, and impurity ions are implanted using the four gate electrodes as a mask to form an n+ type scattered layer 5051 that becomes a source and drain. has been done.

The capacitor electrode 47 and the four gate electrodes are shown in FIG. 2(a).
As is clear from the figure, the gate electrodes 49 are continuously arranged in the same direction, and the gate electrodes 49 serve as word lines.

A CVD insulating film 52 is deposited on the surface of the substrate on which the MOS capacitors and MoS transistors are formed, and a contact hole is formed in this to commonly connect the drains of the plurality of MoS transistors in the direction perpendicular to the word line.
Q wiring 53 is formed in an array. Note that this Aρ wiring 5
3 is a bit line.

In such a memory cell structure, by configuring the element isolation region and the capacitor formation region in the same trench, it is possible to improve the isolation voltage without increasing the area occupied by each, and also to increase the capacitor capacity. This is a promising method for improving the reliability of highly integrated memories. Furthermore, recently, in order to realize high-speed operation in a memory cell having the above structure, attempts have been made to use bipolar transistors in peripheral circuits other than the cell portion.

However, this type of device has the following problems. In other words, in order to further increase the integration density of memory, it is necessary to increase the lateral area of the trench compared to the opening, and when the ratio of the depth to the trench width increases in this way, it is necessary to increase the side area of the trench only at the bottom. It is difficult to form a p1 type diffusion layer to prevent inversion. Also, make the entire cell part high 1
A method is also known in which the device isolation breakdown voltage is compensated for by forming the device on a similar substrate. However, in such a case, ion implantation must be performed at a high concentration and at a high oxygen rate, and thermal diffusion must be performed for a long time.

This affected the transistor characteristics on the surface, causing variations in the threshold value, and caused major problems in terms of reliability.

Furthermore, when making a bipolar transistor on the same substrate, the optimum thickness of the epitaxial growth layer after the formation of the buried collector layer, which will become the collector electrode of the transistor, does not match the optimum thickness of the epitaxial growth layer after the formation of the anti-inversion layer at the bottom of the groove. . That is, in the bipolar transistor section, the performance can be improved by making the epitaxial growth body thinner and the collector buried layer shallower, but the inversion prevention layer at the bottom of the groove must be made deeper from the substrate surface as the structure becomes smaller.

(Problems to be Solved by the Invention) Conventionally, when the element isolation groove becomes deep, it has been difficult to form an anti-inversion layer only at the bottom of the groove. Furthermore, in the Bi-fv10s structure, it is difficult to optimize both the depth positions of the collector buried layer and the anti-inversion layer.

The present invention has been made in consideration of the above circumstances, and its purpose is to be able to secure sufficient element force w1 breakdown voltage without expanding the element occupied area, and to
The depth positions of the collector buried layer and the anti-inversion layer in the MOS structure can be optimized together, and the B i -MO
An object of the present invention is to provide a method for manufacturing a semiconductor device that can improve the reliability of an S-structure RAM or the like.

[Structure of the Invention] (Means for Solving Problems) The gist of the present invention is to use two epitaxial growth layers to make the depths of the two impurity physical implantation layers different from the substrate surface.

That is, the present invention forms grooves for element isolation in a semiconductor substrate, and also forms bipolar transistors and MOS transistors in the substrate.
In a method of manufacturing a semiconductor device in which an element is formed, after forming an anti-inversion layer by selectively introducing impurities into a semiconductor substrate, a first semiconductor film is epitaxially grown on the substrate, and then this semiconductor film is A collector buried layer of the bipolar transistor is formed by selectively introducing impurities into the bipolar transistor, and then a second semiconductor film is epitaxially grown on the first semiconductor film, and then the first and second semiconductor films are formed into a device. In this method, trenches reaching the first buried layer are formed by etching according to the isolation regions.

(Function) According to the present invention, since the bottom surface of the element isolation trench is formed so as to be in contact with the anti-inversion layer, it is possible to improve the element isolation breakdown voltage. is formed so that the bottom surface of the groove is in contact with the above-mentioned anti-inversion layer, so not only leakage between capacitors but also α
Soft errors caused by wires can be suppressed, and memory reliability can be improved. Furthermore, since this anti-inversion layer is buried and formed using epitaxial growth technology, the transistor characteristics on the surface are more stable than in the conventional technology, which uses long-term thermal diffusion to form a highly concentrated layer. becomes. Furthermore, when a buried layer formed by epitaxial growth technology is used in an OMOS, the resistance of the substrate can be reduced, which is effective in preventing latch-up.

Furthermore, according to the method of the present invention, the depths of the anti-inversion layer of the element isolation trench and the buried layer of the collector of the bipolar transistor can be determined independently. It is possible to construct a memory without reducing the reliability and performance of bipolar transistors. Therefore, it is possible to realize a semiconductor device having a [3i-MOS structure] with high reliability and high degree of integration.

(Example) Hereinafter, details of the present invention will be explained with reference to illustrated embodiments.

FIG. 1 is a sectional view showing the manufacturing process of a DRAM cell having a 31-MOS structure according to an embodiment of the present invention. First, as shown in FIG. 1(a), an oxide film 121 is formed on the surface of the p-type 5iJfi board 11, and using a resist 131 left in a predetermined area as a mask, a dose of, for example, boron is 5X.
10 is doped by 3 cm' at an acceleration voltage of 150 KeV to form a p+ type buried layer (inversion prevention@) 14.

Next, after removing the resist 131 and the oxide film 121, a first p-type epitaxial growth layer 115 is formed on the male plate 11 to a thickness of 2.5 μm, as shown in FIG. 1(b). Thereafter, as shown in FIG. 1C, an oxide film 122 is formed on the epitaxial growth layer 15, and using the resist 132 left in a predetermined region as a mask, doping is performed with, for example, arsenic at a dose of 5 x 10"car' and an acceleration voltage of 40 KeV. Then, an n+ type buried layer (collector buried layer) 16 with a high i of 11 degrees is formed.

Next, after removing the resist 132 and the oxide film 122, a second p-type epitaxial growth layer 17 is formed on the epitaxial growth layer 15, as shown in FIG. 1(d'). Next, by doping predetermined regions with impurities, an n-well 18 and an n-well 19 are formed, and by oxidizing a part of the element valve m region, an element isolation insulator 1 is formed.
Form 1!20.

Next, as shown in FIG. 1(e), the collector region of the bipolar transistor is doped with an n-type impurity to form a deep n+ type diffusion at a high concentration! 22 is formed. Further, the substrate in the element isolation region where the element isolation insulating film 20 is not formed is etched by reactive ion etching (RIE) to form an element isolation groove 21. At this time, the groove 21
At least a part or all of the bottom surface thereof is in contact with the p++ buried B14.

Next, as shown in FIG. 1(f), an element isolation withstand voltage hut of a predetermined thickness is formed at the bottom of the element isolation groove 21. Embed $23. The element isolation insulating film 23 is, for example, a SiO2 film. Subsequently, impurities are introduced into the side walls of the trench 21 to form an n-type diffusion layer 24, and then a capacitor electrode 26 is formed on the side and top surfaces of the trench 21 with a capacitor insulating film 25 interposed therebetween. The capacitor insulation y425 is, for example, a thermal oxide film. The capacitor electrode 26 is, for example, a first electrode doped with phosphorus.
It is formed by depositing a polycrystalline silicon film over the entire surface to fill the groove 21 and patterning it into a predetermined shape.

Next, unnecessary capacitor insulating film 25 is removed by etching to once expose the substrate surface, and as shown in FIG. 1(q), interlayer insulation 1271 is formed on the surface of capacitor electrode 26.
Gate insulation II on the exposed part of the board! 272 is formed. In this embodiment, the gate insulating film 272 is a thermal oxide film, but
It is also possible to use the previously formed capacitor insulating film 25 as it is without removing it.

Thereafter, a predetermined region is doped with an n-type impurity to form a base low type diffusion layer 28. Furthermore, after removing the gate insulator 11!272 in a predetermined region by etching, a second film doped with arsenic, for example, is formed as a gate electrode material film over the entire surface.
A layered polycrystalline silicon film is deposited, and the emitter n is formed by thermal diffusion.
+ type diffusion! ! form 30. Furthermore, this is patterned into a predetermined shape to form the gate electrode 8i2L1 and the emitter electrode 292. After this, the unnecessary gate insulating film 27
2, the capacitor electrode 26 and the gate electrode 29!
By doping impurities using n as a mask, n
- The type diffusion layer 31 is formed of self-naline.

Next, a CVD-8i02 film is deposited on the entire surface, and the entire surface is etched by anisotropic etching, for example, RIE, so that the 3i02 film 32 is left selectively only on the sidewalls of the gate electrode 291 by utilizing the steps of the gate electrode 291. A source/drain is formed by doping impurities into a mask and forming an n+ type wide diffusion layer 33 in a self-aligned manner. Furthermore, a p+ type wide diffusion layer 34 is formed by doping impurities at a predetermined position.

In this embodiment, an n+ type wide diffusion layer 33 is formed by doping impurities using the CVO-S R○2 film 32 left on the side wall step portion of the second layer polycrystalline silicon as a mask. It is also possible to directly form an n+ type wide diffusion layer by doping a mask with a high concentration of impurity to form the source/drain.

Next, as shown in step 1 (q), an interlayer insulating film made of, for example, CVD-8i 02 pA35 is deposited over the entire surface, and predetermined positions are etched away to form contact holes. After that, l! Il! As a wire material, for example, Afi model 3
After depositing 6 on the entire surface, wiring is performed by patterning it into a predetermined shape.

Thus, according to the method of this embodiment, since the bottom surface of the element isolation groove 21 is formed so as to be in contact with the p++ buried layer (inversion prevention layer) 14, the element isolation breakdown voltage can be improved without increasing the area of the element isolation. can be measured. Moreover, since the bottom surface of the trench capacitor is formed so as to be in contact with the buried side 14, not only leakage between the capacitors but also soft errors due to α rays can be suppressed, and the reliability of the memory can be improved. Furthermore, since the buried layer 14 for preventing inversion and the collector buried layer 16 of the bipolar transistor can be formed in sequence, these buried layers 114 and 16 can be formed at optimal depth positions, and It becomes possible to simplify the process.

In addition, since the buried layer 14 for preventing inversion is formed using epitaxial growth technology, the characteristics of the MOSi transistor formed on the substrate surface are better compared to the case where the diffusion layer is formed by long-term thermal diffusion. becomes stable. Furthermore, when a buried layer formed by this epitaxial growth technique is used in an OMOS, it is very effective in preventing latch-up, making it possible to reduce the well separation width, and achieving higher integration.

So, FC cell DRA using B i -MOSfN structure
In M, it is possible to achieve high-speed operation, high reliability, and 8-integration, and it is possible to realize a semiconductor device with high reliability and high degree of integration.

Note that the present invention is not limited to the embodiments described above. In the embodiment, the high concentration n+ buried layer 16 as the collector buried layer is formed by arsenic doping, but it can also be formed by, for example, antimony diffusion.

Furthermore, in the embodiment, the capacitor electrode was formed using the first layer polycrystalline silicon film, and the gate electrode and the emitter electrode were formed using the second layer polycrystalline silicon film, but it is also possible to use a high melting point metal or its silicide as the material. can. Furthermore, although the gate electrode and the emitter electrode are formed from the second layer polycrystalline silicon film, it is also possible to form the emitter electrode from the third layer polycrystalline silicon film.

Further, the conductivity types of the anti-inversion layer, the collector buried layer, and the first and second epitaxial growth layers are not limited to those in the embodiments, and can be changed as appropriate according to specifications. For example, the first epitaxial growth layer and the anti-inversion layer may be of the same conductivity type as the substrate, and the second epitaxial growth layer and the collector buried layer may be of the opposite conductivity type to the substrate. Furthermore, it is also possible to make the anti-inversion layer and the collector buried layer of the same conductivity type as the substrate, and to make the first and second epitaxial growth layers of the opposite conductivity type to the substrate. In addition to the SiO2 film formed by thermal oxidation, Si'
It is also possible to use 02 film, Si3N+, etc. In addition, in the embodiment, a DRAM structure was explained in which the capacitor area is increased by using the sidewalls of the element isolation trench, but it is also possible to expand the capacitor area by digging a trench in the substrate surface of the capacitor region, in addition to the element isolation trench. is possible. In addition, various modifications can be made without departing from the gist of the present invention.

[Effect of R-light] As detailed above, according to the present invention, since the element isolation trench is formed so that its bottom surface is in contact with the anti-inversion layer,
Element isolation withstand voltage can be improved without increasing the area of the element isolation region. Moreover, since the depth positions of the anti-inversion layer and the collector buried layer can be set independently depending on the thicknesses of the two epitaxially grown layers, the depth of each buried layer can be optimized together. Therefore, 31-M
The reliability and degree of integration of a semiconductor device with an OS structure can be improved, and its usefulness is enormous.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing the manufacturing process of a DRAM cell having a Bi-MOS structure according to an embodiment of the present invention, and FIG. 2 is a plan view and a sectional view showing a conventional DRAfvLIM structure. 11...p-type Si substrate, 14...p+ type buried layer (
(inversion prevention layer), 15...first p-type epitaxial growth layer, 16...n+ type buried layer (collector buried layer)
, 17... second p-type epitaxial growth layer, 18.
... n-well, 19... n-well, 23... buried insulating film for element isolation, 26... capacitor electrode, 291
...Gate electrode. Applicant's agent Patent attorney Takehiko Suzue Figure 1 (2) Figure 1 (3)

Claims (4)

[Claims] (1) Forming grooves for element isolation in the semiconductor substrate, and
A method for manufacturing a semiconductor device in which a bipolar transistor and a MOS element are formed on the substrate includes a step of selectively introducing impurities into the semiconductor substrate to form an anti-inversion layer, and a step of forming a first semiconductor film on the substrate. a step of epitaxially growing a second semiconductor film; a step of selectively introducing impurities into the semiconductor film to form a buried collector layer of the bipolar transistor; a step of epitaxially growing a second semiconductor film on the first semiconductor film; A method of manufacturing a semiconductor device, comprising the step of etching the first and second semiconductor films according to element isolation regions to form a trench that reaches the first buried layer. (2) The anti-inversion layer and the first and second semiconductor films are of the same conductivity type as the substrate, and the collector pad is of the opposite conductivity type to the substrate. A method for manufacturing a semiconductor device according to section 1. (3) The method for manufacturing a semiconductor device according to claim 1, wherein an insulating film for element isolation is buried in the bottom of the trench. (4) A method of manufacturing a semiconductor device according to claim 1, characterized in that a capacitor electrode is formed on a part of the side wall portion of the trench with a capacitor insulating film interposed therebetween.