TW406354B - A semiconductor device and a manufacturing process therefor - Google Patents
A semiconductor device and a manufacturing process therefor Download PDFInfo
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- TW406354B TW406354B TW088106994A TW88106994A TW406354B TW 406354 B TW406354 B TW 406354B TW 088106994 A TW088106994 A TW 088106994A TW 88106994 A TW88106994 A TW 88106994A TW 406354 B TW406354 B TW 406354B
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- insulating film
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 62
- 238000004519 manufacturing process Methods 0.000 title abstract description 17
- 230000001681 protective effect Effects 0.000 claims abstract description 96
- 239000010410 layer Substances 0.000 claims abstract description 69
- 238000009792 diffusion process Methods 0.000 claims abstract description 61
- 239000002019 doping agent Substances 0.000 claims abstract description 55
- 239000011229 interlayer Substances 0.000 claims abstract description 52
- 238000005530 etching Methods 0.000 claims abstract description 41
- 239000000758 substrate Substances 0.000 claims abstract description 41
- 238000000034 method Methods 0.000 claims abstract description 14
- 238000002955 isolation Methods 0.000 claims description 63
- 238000009413 insulation Methods 0.000 claims description 36
- 239000000463 material Substances 0.000 claims description 12
- 239000003990 capacitor Substances 0.000 claims description 7
- 239000003795 chemical substances by application Substances 0.000 claims description 5
- 238000003860 storage Methods 0.000 claims description 5
- 239000012535 impurity Substances 0.000 claims description 4
- 239000011810 insulating material Substances 0.000 claims description 4
- 239000004020 conductor Substances 0.000 claims description 3
- 239000013078 crystal Substances 0.000 claims 2
- 208000003251 Pruritus Diseases 0.000 claims 1
- 238000009429 electrical wiring Methods 0.000 claims 1
- 230000007803 itching Effects 0.000 claims 1
- 239000010977 jade Substances 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 18
- 229910052710 silicon Inorganic materials 0.000 abstract description 18
- 239000010703 silicon Substances 0.000 abstract description 18
- 230000008569 process Effects 0.000 abstract description 7
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- 230000006866 deterioration Effects 0.000 abstract description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 21
- 229910052814 silicon oxide Inorganic materials 0.000 description 18
- 238000005516 engineering process Methods 0.000 description 11
- 229910052581 Si3N4 Inorganic materials 0.000 description 10
- 229920002120 photoresistant polymer Polymers 0.000 description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 7
- 230000004888 barrier function Effects 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 4
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- 230000009467 reduction Effects 0.000 description 3
- 239000004575 stone Substances 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 241000293849 Cordylanthus Species 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 229910052769 Ytterbium Inorganic materials 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 239000003963 antioxidant agent Substances 0.000 description 1
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- 235000006708 antioxidants Nutrition 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/485—Bit line contacts
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
- Electrodes Of Semiconductors (AREA)
- Element Separation (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
406354 五、發明說明（1) " 【發明背景】 1.發明領域 本發明有關於一種半導體裝置，其於半導體基材的主 要表面包含一渠溝（凹槽）分離絕緣膜，其元件區域之間的 電性連接係透過接觸孔達成。特別關於可符合度 ⑽咖⑽）之需求的半導縣置^集積度 2 ·習知技術 隨著半導體裝置的高度積體化，為使一半導體基材上 的元件之間相互分離並絕緣而使用元件間隔離絕緣&的技 術，。藉由在半導體基材的表面形成渠溝並於其中注入絕緣 ^料而形成渠溝隔離絕緣膜。渠溝隔離絕緣膜的優點在於 積度裝置，因為其不會像L0C0S技術形成的場絕緣膜 一般形成鳥喙狀。在此等渠溝隔離絕緣膜中，當開通一接 =孔以電性連接到一擴散層時，可能會發生定位不準確的 情況’可能導致渠溝隔離絕緣膜被蝕刻，造成相鄰擴散層 =間隔離效果變差。圖10(a)之剖面圖顯示一此種問題的 範例其中在半導體基材201的主表面上形成有一渠溝 202 ’在其上以熱氧化法形成一層矽氧化物膜203，其内則 以如CVD法形成一矽氧化膜2〇4，以成為一渠溝隔離絕緣膜 205 °被渠溝隔離絕緣膜205所界定之區域内具有一閘絕緣 ，206、f閑極207、及一摻雜劑擴散層208作為源極-汲極 區域所形#成之電晶體。由矽氧化物膜構成之層間絕緣 膜209覆蓋該M0S電晶體與渠溝隔離絕緣膜205，其中開有 接觸孔21 0以確保對摻雜劑擴散層208之電性連接。406354 V. Description of the invention (1) " [Background of the invention] 1. Field of the invention The present invention relates to a semiconductor device, which includes a trench (groove) separation insulating film on the main surface of a semiconductor substrate, The electrical connection is achieved through the contact hole. In particular, the semi-conductor that can meet the requirements of the degree of integration ^ Accumulation degree 2 · Known technology As semiconductor devices are highly integrated, in order to separate and insulate components on a semiconductor substrate, Use the technology of isolation insulation between components. A trench isolation insulating film is formed by forming a trench on a surface of a semiconductor substrate and injecting an insulating material therein. The advantage of trench insulation film is the integrated device, because it does not form a bird's beak like the field insulation film formed by L0C0S technology. In these trench isolation insulation films, when a connection = hole is opened to electrically connect to a diffusion layer, inaccurate positioning may occur. 'It may cause the trench isolation insulation film to be etched, resulting in adjacent diffusion layers. = The isolation effect becomes worse. A cross-sectional view of FIG. 10 (a) shows an example of such a problem. A trench 202 'is formed on the main surface of the semiconductor substrate 201, and a silicon oxide film 203 is formed thereon by thermal oxidation. For example, a silicon oxide film 204 is formed by the CVD method to form a trench isolation insulating film 205. The area defined by the trench isolation insulating film 205 has a gate insulation, 206, f free electrode 207, and a doping. The agent diffusion layer 208 functions as a transistor formed in the source-drain region. An interlayer insulating film 209 made of a silicon oxide film covers the MOS transistor and trench isolation insulating film 205, and a contact hole 21 is formed therein to ensure the electrical connection to the dopant diffusion layer 208.
第6頁 406354 五、發明說明（2) 當接觸孔21 0開if時，以一光阻作為遮罩對層間絕緣 膜進行選擇性蝕刻。因此，若光阻遮罩的定位不準埃， 在，層間絕緣膜2 0 9的钱刻期間，渠溝隔離絕緣膜2 〇 5會被 部分#刻。一般而言，在蝕刻接觸孔時，會將絕緣膜稍微 過度餘刻’因為接觸孔底部表面之任何絕緣膜的殘留物會 造成導電失誤，而增加導電電阻。如此可能導致渠溝隔離 絕緣膜205的蝕刻，最終在表面形成凹陷χ。因此，在接觸 孔210開通之後，當藉由在接觸孔21〇中埋入導電元件2ιι 以形成到達摻雜劑擴散層之電性連接結構時，導電元件 211可能部分伸入渠溝隔離絕緣膜2〇5之凹陷χ中，造成渠 溝隔離絕緣膜205上箭頭所指處之有效隔離距離的降低了 因而導致絕緣隔離之隔離效果的惡化。 為解決此問題，於日本專利案Jp] 1〇_1 2733中提出 術，在接觸孔210開通時可能被钱刻之渠溝隔離絕 f =205之上形成一較層間絕緣膜2〇9更具有蝕刻選擇性之 絕膜212，例如多晶矽膜，#圖1〇((〇所示。依據上 =。案’蝕刻阻絕膜212係以下列步 緣膜2。5、在全部表面長成-層多“夕膜=形 = 化Γ ·多晶梦膜進行非等向性㈣ 2〇5的者作為侧壁、沿渠溝隔離絕緣膜 穿置中gΛ 、絕膜212。在此技術所製成之半導體 ίΐ:的Κ ;:孔210開通的過程令發生光阻遮罩定 隔離絕緣二的部分如露圖出 刀露出蝕刻阻絕膜21 2能夠防止渠溝 隔離絕緣膜2 0 5被姓刻’能夠有效解決上述問題。 該公告案中所揭露之技術，藉由在渠溝隔離絕緣膜 205的部分表面形成蝕刻阻絕膜212，在對層間絕緣膜進行 微過度蝕刻時，能夠有效的防止渠溝隔離絕緣膜2〇5的表 面被蝕刻。然而，當大於蝕刻阻絕膜21 2的層間絕緣膜區 域受到餘刻，此技術則無法防止未被蝕刻阻絕膜2丨2覆蓋 的渠溝隔離絕緣膜2 0 5區域受到姓刻。特別是現今半導體 裝置高度積體的技術中，一裝置圖案的尺寸小於數百微米 的情況下。然而，不易減少開通一對應出如此尺寸縮小的 接觸孔所使用之遮罩圖案的大小。因此，必須持續增加光 阻遮罩定位的精確度。因此，若遮罩圖案之開放窗口區域 被定位在蝕刻阻絕膜21 2以外的區域並進行蝕刻，上述問 題可能非常重要。 此外’在層間絕緣膜209過度蝕刻的過程中，此技術 並不此防止半導體基材2〇1主要表面上之摻雜劑擴散層gig 的表面受到蝕刻。因此，當因為半導體裝置的高度積體造 成摻雜劑擴散層208較薄時’摻雜劑擴散層2〇8的有效厚度 可此減少’導致對摻雜劑擴散層2 〇 8之接觸電阻增加，或 接點漏電的增加。 除此之外，上述公告案之技術中包含長成多晶矽以形 成姓刻阻絕膜21 2，其於非等向性蝕刻之後殘留作為侧 ，。因此’相較於原有之半導體裝置製程，會增加上述多 晶矽成長與非等向性蝕刻的步驟，造成製程的複雜化。 【發明概述】Page 6 406354 V. Description of the invention (2) When the contact hole 21 is opened at if, the interlayer insulating film is selectively etched with a photoresist as a mask. Therefore, if the positioning of the photoresist mask is inaccurate, the trench isolation insulating film 2005 will be partially engraved during the engraving of the interlayer insulating film 209. In general, when the contact hole is etched, the insulating film will be slightly over-etched 'because any residue of the insulating film on the bottom surface of the contact hole will cause conduction errors and increase the conductive resistance. This may cause the trench isolation insulating film 205 to be etched and eventually form a depression χ on the surface. Therefore, after the contact hole 210 is opened, when the conductive element 2m is buried in the contact hole 21 to form an electrical connection structure reaching the dopant diffusion layer, the conductive element 211 may partially extend into the trench isolation insulating film. In the depression χ of 205, the effective isolation distance indicated by the arrow on the trench isolation insulating film 205 is reduced, and the isolation effect of the insulation isolation is deteriorated. In order to solve this problem, a technique is proposed in Japanese patent case Jp] 10_1 2733. When the contact hole 210 is opened, it may be isolated by a groove carved by money and f = 205 to form a more interlayer insulating film than 209. An insulating film 212 having an etch selectivity, such as a polycrystalline silicon film, is shown in FIG. 10 ((0. According to the above = case.) The etching resist film 212 is based on the following step film 2. 5. A layer is formed on the entire surface. Multi-layer film = shape = chemical Γ · Polycrystalline dream film with anisotropy ㈣ 205 as the side wall, along the trench isolation insulation film wearing gΛ, insulation film 212. Made by this technology The process of opening of the semiconductor ΐ: K;: hole 210 causes the photoresist mask to isolate the insulating and insulating parts. The exposed etching resist film 21 2 can be exposed as shown in the figure. It can prevent the trench isolation insulating film 2 0 5 from being engraved. Effectively solve the above problems. The technology disclosed in this bulletin can effectively prevent trench isolation by forming an etch stop film 212 on a part of the surface of the trench isolation insulating film 205 when the interlayer insulating film is slightly over-etched. The surface of the insulating film 205 is etched. However, when it is larger than the etching stopper film 21 2 The interlayer insulating film area is subject to the remaining moments. This technology cannot prevent the trench isolation insulating film 2 0 5 areas that are not covered by the etch stop film 2 丨 2 from being engraved. Especially in the current technology of highly integrated semiconductor devices, a device When the size of the pattern is less than several hundred micrometers. However, it is not easy to reduce the size of the mask pattern used to open a contact hole corresponding to such a reduction in size. Therefore, the accuracy of the positioning of the photoresist mask must be continuously increased. Therefore, If the open window area of the mask pattern is positioned and etched outside the etching stopper film 21 2, the above problems may be very important. In addition, during the over-etching of the interlayer insulating film 209, this technology does not prevent the semiconductor-based The surface of the dopant diffusion layer gig on the main surface of the material 201 is etched. Therefore, when the dopant diffusion layer 208 is thin due to the high volume of the semiconductor device, the dopant diffusion layer 208 is effective. This decrease in thickness can result in an increase in contact resistance to the dopant diffusion layer 208, or an increase in contact leakage. In addition, the above-mentioned announcement The technology includes growing polycrystalline silicon to form a etched resist film 21 2 which remains as a side after anisotropic etching. Therefore, compared to the original semiconductor device manufacturing process, the above polycrystalline silicon growth and anisotropy will be increased. The etching step complicates the manufacturing process. [Summary of the Invention]
第8頁 五、發明說明(4) 306354 —— :土因此本發明目的之一在提出一種半導體裝置及其製 =方法，即使高度積體化，亦能夠防止渠溝隔離絕緣膜之 隔離特性的劣化、防止摻雜劑擴散層之接觸電阻或接點漏 電的增加、且不會使製程更為複雜。 本發明主要實施例為一半導體裝置，包含：一渠溝隔 離絕緣膜，在半導體基材表面上之渠溝内埋入一絕緣材料 所構成；一摻雜劑擴散層，形成於該半導鱧基材上且由該 渠溝隔離絕緣膜界定其範圍；一層間絕緣膜，形成於該半 導體基材表面；一接觸孔，開通於該層間絕緣膜並提供通 路至該摻雜劑擴散層；及一配線，包含配設於該接觸孔内 之導電物質，其特徵為在不包含該接觸孔開通區域之該半 導體基材以及該層間絕緣膜之間，形成一層較該層間絕緣 及該渠溝隔離絕緣膜更具蝕刻選擇性之防護膜。更明確而 言’本發明最佳實施例之半導體裝置其特徵在於在一半導 體基材上形成一閘電極及一包含摻雜劑擴散層作為源極_ 汲極區域之M0S電晶體；於閘電極上形成一第一防護膜； 於閘電極侧邊形成一第二防護膜；於全部半導體基材的表 面形成一第三防護膜並覆蓋該第一及第二防護膜；在第三 防護膜上形成一較第一至第三防護膜更具蝕刻選擇性之層 間絕緣膜；及一接觸孔通過此層間絕緣膜及第三防護膜以 提供通路至此摻雜劑擴散層。 此接觸孔在層間絕緣膜的上層區域，在X或γ平面方 向’相較於半導體基材被第一至第三防護膜與渠溝隔離絕 緣膜所界定的區域’較佳具有較大的開口尺寸，本發明可Page 8 V. Description of the invention (4) 306354 ——: One of the objects of the present invention is to propose a semiconductor device and a manufacturing method thereof. Even if it is highly integrated, it can prevent the isolation characteristics of the trench isolation insulation film. Deterioration, preventing increase in contact resistance or contact leakage of the dopant diffusion layer without complicating the process. The main embodiment of the present invention is a semiconductor device including: a trench isolation insulating film, which is formed by embedding an insulating material in a trench on the surface of a semiconductor substrate; a dopant diffusion layer formed on the semiconductor semiconductor; The substrate is delimited by the trench isolation insulating film; an interlayer insulating film is formed on the surface of the semiconductor substrate; a contact hole is opened in the interlayer insulating film and provides a path to the dopant diffusion layer; and A wiring including a conductive substance disposed in the contact hole, which is characterized in that a layer is formed that is more isolated from the interlayer insulation and the trench between the semiconductor substrate and the interlayer insulation film than the contact hole opening area. The insulating film has a more selective etching protection film. More specifically, the semiconductor device of the preferred embodiment of the present invention is characterized in that a gate electrode and a MOS transistor including a dopant diffusion layer as a source_drain region are formed on a semiconductor substrate; Forming a first protective film on the side; forming a second protective film on the side of the gate electrode; forming a third protective film on the surface of all semiconductor substrates and covering the first and second protective films; on the third protective film Forming an interlayer insulating film with more etch selectivity than the first to third protective films; and a contact hole passing through the interlayer insulating film and the third protective film to provide a path to the dopant diffusion layer. The contact hole in the upper layer region of the interlayer insulating film preferably has a larger opening in the X or γ plane direction than the region defined by the first to third protective films and the trench isolation insulating film of the semiconductor substrate. Size, the invention can
五、發明說明（5) 應用於DRAM ,其MOS電晶體構成DRAM之記憶單元，且接 孔構成至少一個用來連接一位元線至一構成此M〇s電晶體 之源極-汲極區域的摻雜劑擴散層之接觸孔以及一用來 ^儲存電容電荷之電極配線到另一摻雜劑擴散層的接觸 本發明亦提出一種製造半導體裝置的方法，包含· =導體基材的主要表面形成—渠溝；將絕緣材料埋入渠 /以形成渠溝隔離絕緣膜；I I導體基材主要表面上开; 2溝：離絕緣膜所阻絕’ &含至少-摻雜劑擴散声V. Description of the invention (5) Applied to DRAM, the MOS transistor constitutes the memory unit of the DRAM, and the connection hole forms at least one for connecting a bit line to a source-drain region constituting the MOS transistor. The contact hole of the dopant diffusion layer and the contact of an electrode wiring for storing a capacitor charge to another dopant diffusion layer The present invention also proposes a method for manufacturing a semiconductor device, including a main surface of a conductive substrate Forming-trenches; burying insulating material in the trenches to form trench isolation insulation films; II conductor substrates open on the main surface; 2 trenches: blocked from the insulation film '& containing at least-dopant diffusion sound
Li::: 半導體基材的全部表面形成-防護膜曰 i絡=形成—層較防護膜更具有㈣選擇性的層門 、，邑緣膜，及依序對層間絕緣膜與防護膜進行蝕刻以二 π:達摻雜劑擴散層。形成半導體元件的步二: i:及ίί!體ί材主要表面上形成閘極氧化膜、-閉電 上形成-摻雜劑擴散層作為源極-汲極區導，材要表面 夾於其中；及於開電極側邊形成—第'[二其將閉電極 =卩+導體基材表面之防護膜的步驟包含形成一可豫 蓋該第一及第二防護膜之第三防護膜。 了覆 接觸孔的開通步驟包含：以較第= 速率對層間絕緣膜進行蝕刻、以較j 之蝕刻 =迷率對第三防護膜進行.刻較 :用:光罩進行’其在X或γ平面方向，相較以 上破第-Μ三防護膜與渠溝隔離絕緣膜所界 第10頁 五 '發明說明（6) 域，具有較大的開口窗。 依據本發明、，在層間絕緣膜上開通接觸孔的蝕刻步驟 因A用來開通接觸孔之光阻遮罩的定位出現不準確’ 隔離絕緣膜被一防護膜所覆蓋，亦即被第三防護 ’亦能夠防止因為渠溝隔離絕緣膜受到钱刻導致 隔離距離減少所造成的絕緣隔離之隔離特性的劣化。 -咏吃摻雜劑擴散層的表面被—防護膜所覆蓋，亦即被第 ::護膜所覆蓋’在層間絕緣膜被姓 程度較輕微，，能夠有效防止== 層之接觸電阻的增加以及接點漏電。 在鄭^ : ί極受到從第一至第三防護膜的覆i，即使當 Ϊ = 附近區域之接觸孔在開通時，用來開通接觸 =開口可以限制在由第一至第三防護膜所以區：觸 尺二的體裝置高集積度而造成接觸孔之開口 j度的定位，接觸孔可以藉由自我定位獲得丄=精 【圖示之簡單說明】 平面遞本發明應用於半導體裝置之_型的實施例之 =_圖1中線段Α-Α及Β-Β所得之放大剖面圖。 依據圖2$^糸之剖面結構 圖圖1及圖2所示半導體裝置製程的第一步驟， 第11頁 406354 五、發明說 圖圖1及圖2所示半導體裝置製程的第二步驟 依據圖2〇{^#之剖面結構。 圖圖1及圖2所示半導體裝置製程的第三步驟 依據圖之剖面結構。 圖6胃芦圖1及圖2所示半導體裝置製程的第四步驟， 依據圖2丨:之剖面結構。 圖圖1及圖2所示半導體裝置製程的第五步驟， 依據圖2 之剖面結構。 圖8^^圖1及圖2所示半導體裝置製程的第六步驟， l.v.〆 依據圖2之剖面結構。 圖9^1夺本發明應用於DRAM的實施例之平面布局及沿 C - C線择刮面圖。 面圖顯示習知技術的問題以及以往之改善 提案。 【符號之說明】 1 0 1矽基材 102渠溝 1 0 3矽熱氧化膜 1 0 4矽氧化物膜 1 0 5渠溝隔離絕緣膜 1 0 6閘氧化物膜 1 0 7 閘電極 1 0 8 η型摻雜劑擴散層 1 0 9第一防護膜Li ::: The entire surface of the semiconductor substrate is formed-the protective film is formed = the layer is more selective than the protective film, the gate, the edge film, and the interlayer insulation film and the protective film are sequentially etched Dopant diffusion layer with two π: Da. Step 2: forming a semiconductor device: i: and ί! The main surface of the material is formed with a gate oxide film, and a dopant diffusion layer is formed on the power supply as a source-drain region guide, and the surface of the material is sandwiched therein. And forming a protective film on the side of the open electrode—the second step of closing the electrode = 卩 + the surface of the conductive substrate includes forming a third protective film that covers the first and second protective films. The opening step of covering the contact hole includes: etching the interlayer insulating film at a relatively high rate, and etching the third protective film with a relatively high etching rate. The comparison is performed with a photomask, which is performed at X or γ. In the plane direction, compared with the above-mentioned three-M third protective film and the trench isolation insulation film, page 10, the description of the invention (6), has a larger opening window. According to the present invention, the etching step of opening the contact hole on the interlayer insulating film is inaccurate due to the positioning of the photoresist mask used by A to open the contact hole, 'The insulating insulating film is covered by a protective film, that is, protected by the third protection'. It can prevent the deterioration of the isolation characteristics of the insulation isolation caused by the reduction of the isolation distance due to the trench isolation insulation film being subjected to money engraving. -The surface of the dopant diffusion layer is covered by a protective film, that is, covered by the ":: protective film", the degree of insulation between the interlayer insulating films is relatively slight, which can effectively prevent the increase of the contact resistance of the layer == And contact leakage. In Zheng ^: The pole is covered by the first to third protective films, even when Ϊ = the contact hole in the vicinity is opened, it is used to open the contact = the opening can be limited to the first to third protective films. Zone: The high degree of integration of the body device of the touch ruler leads to the positioning of the opening of the contact hole by j degrees. The contact hole can be obtained by self-positioning. 丄 = Fine [Simplified description of the icon] The present invention is applied to a semiconductor device. The embodiment of the type = _ enlarged sectional view obtained by the line segments A-A and B-B in FIG. 1. According to the cross-sectional structure diagram of FIG. 2 ^ 糸, the first step of the semiconductor device manufacturing process shown in FIG. 1 and FIG. 2 is on page 11. 406354 V. The invention is based on the second step of the semiconductor device manufacturing process shown in FIG. 1 and FIG. 2〇 {^ # 的 profilestructure. The third step of the semiconductor device manufacturing process shown in FIGS. 1 and 2 is a cross-sectional structure according to the figure. FIG. 6 shows the fourth step of the semiconductor device manufacturing process shown in FIGS. 1 and 2 according to the cross-sectional structure of FIG. The fifth step of the semiconductor device manufacturing process shown in FIGS. 1 and 2 is based on the cross-sectional structure of FIG. 2. FIG. 8 ^^ The sixth step of the semiconductor device manufacturing process shown in FIG. 1 and FIG. 2, l.v. l according to the cross-sectional structure of FIG. 2. Fig. 9 ^ 1 shows a plan layout of the embodiment of the present invention applied to DRAM and a plan view along C-C. The diagrams show problems with conventional technologies and past proposals for improvement. [Description of Symbols] 1 0 1 Silicon substrate 102 trench 1 0 3 Silicon thermal oxide film 1 0 4 Silicon oxide film 1 0 5 Channel isolation insulation film 1 0 6 Gate oxide film 1 0 7 Gate electrode 1 0 8 n-type dopant diffusion layer 1 0 9 First protective film
第12頁 406354 五、發明說明（8) 11 0第二防護膜 111第三防護膜 1 1 2層間絕緣膜 I 1 3接觸孔 II 4阻絕金屬膜 11 5 配線膜 11 6 第一配線 11 7 第二層間絕緣膜 11 8接觸孔 11 9阻絕金屬膜 1 2 0 配線材料 1 21 儲存電極 1 2 2 電容絕緣膜 123計數器電極 124 電容 1 2 5第三層間絕緣膜 1 31矽氧化物膜 1 3 2矽氮化物膜 201半導體基材 202渠溝 2 0 3矽氧化物膜 2 0 4矽氧化膜 2 0 5渠溝隔離絕緣膜 206 閘絕緣膜Page 12 406354 V. Description of the invention (8) 11 0 Second protective film 111 Third protective film 1 1 2 Interlayer insulating film I 1 3 Contact hole II 4 Barrier metal film 11 5 Wiring film 11 6 First wiring 11 7 No. Two interlayer insulating film 11 8 contact hole 11 9 barrier metal film 1 2 0 wiring material 1 21 storage electrode 1 2 2 capacitor insulating film 123 counter electrode 124 capacitor 1 2 5 third interlayer insulating film 1 31 silicon oxide film 1 3 2 Silicon nitride film 201 semiconductor substrate 202 trench 2 0 3 silicon oxide film 2 0 4 silicon oxide film 2 5 5 trench isolation insulating film 206 gate insulating film
第13頁 細 354 五、發明說明（9) 2(L7 閘極 208摻雜劑擴散層 2 0 9層間絕緣膜 2 1 0接觸孔 211導電元件 21 2蝕刻阻絕膜 【發明的詳細說明】 接下來參照附圖說明本發明之較佳實施例。圖1為將 本發明應用於半導體裝置之M0S型的實施例之平面布局 圖。圖2(a)與（b)為沿圖1中線段A-A及B-B所得之剖面圊。 深度100到300nra的渠溝102形成於一p型矽基材上。厚 度20到30nm的矽熱氧化膜i〇3(Si〇2)形成於渠溝1〇2之内表 面上，而一 CVD矽氧化物膜104(Si〇2)埋入於渠溝中以形 一渠溝隔離絕緣膜1 〇 5。 矽氧化物（Si〇2)所構成之閘氧化物膜1〇6及一 夕晶 矽所構成之閘電極1 07形成於矽基材丨〇 i〜一 X必叫丄。_ η型摻雜劑擴散層108，由渠溝隔離絕緣膜105所界定，形 成於矽基材的主要表面上，做為源極_汲極區域。此 二物膜1〇6及間電極！07構成一 _電晶體。一石夕氧化物 (saD所構成之第一防護膜1〇9沉積在閘電極1〇7上，一矽 p乂匕1〇2)所構成之第二防護膜110形成於閘電極107與 物膜106的側邊’做為側壁之用。一由石夕氣化物 (ShN4)所構成，厚度2〇至4〇11(11之第三防護膜ui形成於矽 五、發明說明（10) 基材101全部的表面上，包括閘電極107及渠溝隔離絕緣膜 1 05上。一BPSG材質，厚度1. 之層間絕緣膜丨12形成在 第三防護膜1 U上，且在層間絕緣膜11 2與第三防護膜丨】i 中間開通一接觸孔丨丨3，可到達閘電極丨〇7之間的η型摻雜 劑擴散層1 0 8。第一配線11 6形成於接觸孔〗丨3内，用來電 性連接η型摻雜劑擴散層108，其係由阻絕金屬膜114(例如 T i Ν，氮化嫣）及沉積在阻絕金屬膜11 4上之配線膜11 5 (例 如W，鎢）所構成。 、 接下來參照圖3〜8說明MOS型半導體裝置之製程。圖中 (a)與（b )分別為沿圖1中線段a — a與B - B所得之剖面圖。首 先，如圖3所示，與習知方法相同，一渠溝隔離絕緣膜1〇5 形成於一p型矽基材1〇1主要表面上之特定區域。舉例而 呂’在p型矽基材1〇1的主要表面上沉積一矽氧化物膜 及一石夕氮化物膜1 3 2做為抗氧化物琪，然後進行選擇性钱 刻以留下一元件形成區域。使用矽氮化物膜丨3 2做為遮 罩，對矽基材101進行蝕刻至形成深度10〇到3〇〇ηιη的渠溝 102。然後’將渠溝1〇2内表面加熱氧化以形成一矽熱氧化 膜103 ’厚度為20至30nm。之後，以CVD法將較渠溝1〇2深 度更厚之矽氧化物膜104埋入。埋入之矽氧化物膜丨以例 如CMP法（chemical mechanical polishing，化學機械研 磨）鍅刻，將矽氮化物膜1 32蝕去，以形成渠溝隔離絕緣膜 105。 接下來，如圖4所示，位於受到渠溝隔離絕緣膜丨所 界定之元件形成區域内之矽氧化物膜1 31被蝕去，然後再Page 13 354 V. Description of the invention (9) 2 (L7 Gate 208 dopant diffusion layer 2 0 9 Interlayer insulating film 2 1 0 Contact hole 211 Conductive element 21 2 Etching barrier film [Detailed description of the invention] Next A preferred embodiment of the present invention will be described with reference to the accompanying drawings. FIG. 1 is a plan layout diagram of an embodiment in which the present invention is applied to a MOS type semiconductor device. FIGS. 2 (a) and (b) are along the line segments AA and 2 in FIG. The cross section obtained from BB. The trench 102 having a depth of 100 to 300 nra is formed on a p-type silicon substrate. A silicon thermal oxide film i03 (Si〇2) with a thickness of 20 to 30 nm is formed within the trench 102. On the surface, a CVD silicon oxide film 104 (Si〇2) is buried in the trench to form a trench isolation insulating film 105. A gate oxide film 1 made of silicon oxide (Si〇2) 〇6 and the gate electrode made of crystalline silicon 107 is formed on the silicon substrate. 〇i ~ 一 X must be called 丄. _ N-type dopant diffusion layer 108 is defined by the trench isolation insulating film 105 and formed. On the main surface of the silicon substrate, as the source_drain region. The two material films 106 and the inter-electrode! 07 constitute a transistor. A stone evening oxide (saD) A first protective film 109 is deposited on the gate electrode 107, and a second protective film 110 composed of a silicon p10 10) is formed on the side of the gate electrode 107 and the object film 106 as a side wall. First, a third protective film ui composed of Shixi gas (ShN4) with a thickness of 20 to 4101 (11) is formed on silicon V. Description of the invention (10) The entire surface of the substrate 101, including the gate electrode 107 and trench isolation insulation film 105. A BPSG material, thickness 1. Interlayer insulation film 丨 12 is formed on the third protective film 1 U, and between the interlayer insulation film 11 2 and the third protective film 丨] i A contact hole 丨 3 is opened to reach the n-type dopant diffusion layer 1 0 between the gate electrode 〇 07. The first wiring 116 is formed in the contact hole 3 and is used to electrically connect the η-type dopant. The impurity diffusion layer 108 is composed of a barrier metal film 114 (for example, TiN, nitride) and a wiring film 11 5 (for example, W, tungsten) deposited on the barrier metal film 114. Figures 3 to 8 illustrate the manufacturing process of MOS-type semiconductor devices. (A) and (b) in the figure are cross-sectional views taken along the line segments a-a and B-B in Figure 1. First, as shown in Figure 3 As shown in the conventional method, a trench isolation insulating film 105 is formed in a specific area on the main surface of a p-type silicon substrate 101. For example, Lu's main method of p-type silicon substrate 101 A silicon oxide film and a silicon nitride film 1 3 2 are deposited on the surface as an anti-oxidant, and then a selective engraving is performed to leave an element formation area. A silicon nitride film 3 2 is used as a mask The silicon substrate 101 is etched to form a trench 102 having a depth of 100 to 300 nm. Then, the inner surface of the trench 102 is thermally oxidized to form a silicon thermal oxide film 103 'with a thickness of 20 to 30 nm. Thereafter, a silicon oxide film 104 having a thickness deeper than that of the trench 102 is buried by CVD. The buried silicon oxide film is etched by, for example, CMP (chemical mechanical polishing), and the silicon nitride film 132 is etched away to form a trench isolation insulating film 105. Next, as shown in FIG. 4, the silicon oxide film 1 31 in the element formation area defined by the trench isolation insulating film 丨 is etched away, and then
第15頁 五、發明說明（Π) 度進行加熱氧化，以在矽基材101的主要表面上形成厚度 、’勺20nm之閘氧化物膜。之後，在全部表面上形成一厚 度約80至120ΠΠ1之多晶矽膜107，並在其上形成一厚度約5〇 nm做為第一防護膜之矽氧化物膜1〇9。然後，使用光阻（圖 中未顯示）做為遮罩，以特定圖案對矽氧化物膜1〇9與多晶 矽膜1 07進行選擇性蝕刻，以在閘電極上同時形成多晶矽 膜107/、第防5蔓膜在選擇性姓刻中，多晶石夕膜IQ? 的蝕刻速度較閘氧化物膜1 06的蝕刻速度更快。因此，蝕 刻可以在適當的點停住以留下部分的閘氧化物膜丨〇6。因 而不需要在此一步驟中對渠溝隔離絕緣膜丨〇5進行蝕刻。 ，下來，殘餘之閘氧化物膜1〇6以例如緩衝的（buffered) 氫氟酸移除，且藉由使用閘電極丨〇 7與渠溝隔離絕緣膜丨〇5 做為遮罩的自我定位方法，將n型摻雜劑（例如砷）離子值 佈（ion-implanted)到矽基材101的主要表面上， 型掺雜劑擴散層108做為源極-汲極區域。 接下來，如圖5所示，在所有表面上形成厚度約8〇nm 之矽氧化物膜之後，以RIE法對矽氧化物膜進行非等向性 蝕刻，留下第一防護膜i 09、閘電極1〇7、及閘氧化物膜 106一的侧邊上做為側壁，其為第二防護膜n〇。然後如圖6 f Γ楚在所有表面上形成厚度約20至4〇nm之矽氮化物膜， 做為第三防護膜111，其上形成一 BPSG材質的 之層間絕緣膜112。 又5i· ummPage 15 V. Description of the invention (Π) The thermal oxidation is performed to form a gate oxide film with a thickness of 20 'on the main surface of the silicon substrate 101. Thereafter, a polycrystalline silicon film 107 having a thickness of about 80 to 120 Π1 is formed on the entire surface, and a silicon oxide film 109 having a thickness of about 50 nm as the first protective film is formed thereon. Then, a photoresist (not shown) is used as a mask to selectively etch the silicon oxide film 109 and the polycrystalline silicon film 107 in a specific pattern, so as to simultaneously form the polycrystalline silicon film 107 on the gate electrode. In selective engraving, the etching speed of polycrystalline stone film IQ? Is faster than that of gate oxide film 106. Therefore, the etching can be stopped at an appropriate point to leave a part of the gate oxide film. Therefore, it is not necessary to etch the trench isolation insulating film 5 in this step. Next, the remaining gate oxide film 106 is removed with, for example, buffered hydrofluoric acid, and the gate electrode is insulated from the trench by using the gate electrode. 〇〇7 as a mask for self-positioning. In the method, an n-type dopant (such as arsenic) is ion-implanted onto the main surface of the silicon substrate 101, and the type-dopant diffusion layer 108 is used as a source-drain region. Next, as shown in FIG. 5, after a silicon oxide film having a thickness of about 80 nm is formed on all surfaces, the silicon oxide film is anisotropically etched by the RIE method, leaving a first protective film i 09, The side of the gate electrode 107 and the gate oxide film 106 is used as a side wall, which is a second protective film no. Then, as shown in FIG. 6 f, a silicon nitride film having a thickness of about 20 to 40 nm is formed on all surfaces as a third protective film 111, and an interlayer insulating film 112 made of BPSG is formed thereon. 5i · umm
、發明說明（12) ^ f層間絕緣臈1 1 2表面形成一在接觸孔的開口區域具 有「/窗口之光阻膜（圖中未顯示），並使用此光阻膜做為遮 罩進行電漿蝕刻步驟’使用C4F8/Ar/02的混合，並在使層 間，緣膜112與第三防護膜1Π (即BpsG膜與矽氮化物）蝕刻 速率為50 : 1的條件下進行。因此，在層間絕緣膜11 2蝕刻 的，間’第三防護膜1 1 1具有蝕刻停止的作用，以將第三 防護膜111之膜損失降低到約50% ;因此，即使當層間絕緣 膜112的過度蝕刻量設定為50%，在第三防護膜111的蝕刻 可以限定為在表面侧之丨/2。因此，渠溝隔離絕緣膜 1〇5(石夕氧化物膜1〇3及1〇4)與η型摻雜劑擴散層1〇8絕對不 會被蝕刻。且第一與第二防護膜〗〇 9，丨丨〇亦不會受到蝕 刻。 接下來，如圖8所示’殘留在接觸孔113底部之第三防 護膜111 ’使用CHFa/O2氣體以電漿蝕刻技術將其去除。在 此步驟中，將條件設定成第三防護膜丨〗丨與渠溝隔離絕緣 膜1 0 5之間的蝕刻速率比約為2 : 1，亦即矽氮化物膜及矽 氧化物膜的比例。殘留在接觸孔丨丨3底部之第三防護膜i j i 的床度約為10至20nm。因此，即使當第三防護膜I"的過 度#刻量k疋為50% ’渠溝隔離絕緣膜1〇5表面之膜損失可 限定在約10至15nm。對η型摻雜劑擴散層1〇8的表面而言， 因為矽的蝕刻速率小於矽氮化物膜，即使第三防護族丨j 1 被過度蝕刻’ η型摻雜劑擴散層1 〇8表面的蝕刻得以減少； 因此η型摻雜劑擴散層1 〇8的厚度僅會微量變小。因此，即 使當第三防護膜111在接觸孔11 3中受到蝕刻，第一與第二、 Explanation of the invention (12) ^ f Interlayer insulation 表面 1 1 2 The surface is formed with a photoresist film (not shown) in the opening area of the contact hole, and the photoresist film is used as a mask for electrical The slurry etching step is performed using a mixture of C4F8 / Ar / 02, and the etching rate is 50: 1 between the interlayer, the edge film 112 and the third protective film 1Π (ie, the BpsG film and the silicon nitride). Therefore, at The interlayer insulating film 11 2 is etched, and the inter-third protective film 1 1 1 has an effect of etch stop to reduce the film loss of the third protective film 111 to about 50%; therefore, even when the interlayer insulating film 112 is over-etched, The amount is set to 50%, and the etching of the third protective film 111 can be limited to / 2 on the surface side. Therefore, the trench isolation insulating film 105 (stone oxide films 103 and 104) and The n-type dopant diffusion layer 108 will never be etched, and the first and second protective films will not be etched. Next, as shown in FIG. 8, it remains in the contact hole. The third protective film at the bottom of 113 111 'removes it with plasma etching technology using CHFa / O2 gas. In this step, the The condition is set to a third protective film 丨〗 丨 The etching rate ratio between the trench isolation insulating film 105 is about 2: 1, which is the ratio of the silicon nitride film and the silicon oxide film. Residue in the contact hole 丨丨 The bed of the third protective film iji at the bottom is about 10 to 20 nm. Therefore, even when the third protective film I " excessive #knot is 50%, the film on the surface of the trench isolation insulating film 105 The loss may be limited to about 10 to 15 nm. For the surface of the n-type dopant diffusion layer 108, because the etching rate of silicon is less than that of a silicon nitride film, even if the third protective group j 1 is over-etched 'n-type Etching of the surface of the dopant diffusion layer 108 is reduced; therefore, the thickness of the n-type dopant diffusion layer 108 is only slightly reduced. Therefore, even when the third protective film 111 is etched in the contact hole 113 , First and second
蔓膜109, 110並不會受到蝕刻’因此閘電極⑺7並不會露 认本ft i如圖2所示’在層間絕緣膜112包含接觸孔U3 、甘〃况積由氮化鈦所構成之阻絕金屬膜114，然後 ΐ '儿積鎢所構成之配線膜11 5 6然後依據一特定圖 二a 〇以在接觸孔1 1 3中形成一電性連接到η型摻雜劑擴 散層108之第一配線116 :然後形成圖1及圖2所示之議型' 如^刖文所述，在本發明的步驟中，於形成層間絕緣膜 11 2之前/由較層間絕緣膜11 2更具蝕刻選擇性之材質所構 成的第三防護膜形成於矽基材101的表面，特別是渠溝隔 離絕緣膜105與穆雜劑擴散層108上。因此，即使在層間絕 緣膜1^ 2中接觸孔11 3開通的蝕刻過程中所使用之光阻遮罩 出現定位不準確的情形，渠溝隔離絕緣膜1〇5並不會被蝕 刻。在接下來將第三防護膜lu除去的過程中，即使渠溝 隔離絕緣膜1 〇 5受到輕微的蝕刻，所蝕去的量能夠有效的 限制，以/方止在渠溝隔離絕緣膜1〇5的表面上出現如圖 1 0(0所示的凹陷。因此，即使當第一配線丨丨6在第一配線 116形成之形成步驟中埋入於接觸孔113内，渠溝隔離絕緣 膜105的有效隔離距離可能不會因為第一配線116而減少， 上述情況可能造成絕緣隔離之隔離特性的劣化。 在蝕刻層間絕緣膜11 2以同時開通接觸孔丨丨3的步驟 中’η型摻雜劑擴散層108的表面被第三防護膜1U覆蓋， 因此摻雜劑擴散層1 08不會受到蝕刻。此外，當對第三防The diffuser films 109, 110 will not be etched. Therefore, the gate electrode ⑺7 will not be exposed as shown in FIG. 2 '. The interlayer insulating film 112 includes a contact hole U3, and the GaN film is composed of titanium nitride. The metal film 114 is blocked, and then the wiring film 11 5 6 made of tungsten is then formed according to a specific figure II a 0 to form an electrical connection to the n-type dopant diffusion layer 108 in the contact hole 1 1 3. First wiring 116: Then, the shape shown in FIG. 1 and FIG. 2 is formed. As described in the text, in the step of the present invention, before the interlayer insulating film 11 2 is formed, A third protective film made of an etch-selective material is formed on the surface of the silicon substrate 101, in particular, the trench isolation insulating film 105 and the impurity diffusion layer 108. Therefore, even if the photoresist mask used in the etching process of opening the contact hole 11 3 in the interlayer insulating film 1 ^ 2 is inaccurately positioned, the trench isolation insulating film 105 will not be etched. In the following process of removing the third protective film lu, even if the trench isolation insulating film 105 is slightly etched, the amount of the erosion can be effectively limited to stop the trench isolation insulating film 1 A depression as shown in FIG. 10 appears on the surface of 5. Therefore, even when the first wiring 丨 6 is buried in the contact hole 113 during the formation step of the first wiring 116, the trench isolation insulating film 105 The effective isolation distance may not be reduced by the first wiring 116, and the above situation may cause deterioration of the isolation characteristics of the insulation isolation. In the step of etching the interlayer insulating film 112 to open the contact holes simultaneously, the n-type doping The surface of the agent diffusion layer 108 is covered by the third protective film 1U, so the dopant diffusion layer 108 will not be etched. In addition, when the third
第18頁 -------仙⑽ 5 d_____ 五、發明說明（14) — 護膜111進行蝕刻時，因為矽氮化物（亦及第三防護臈）與 矽之間存在蝕刻選擇性，使得n型摻雜劑擴散層i08的表面 僅會受到輕微的蝕刻。因此，即使因為高積體化M0S型半 導體裝置造成η型摻雜劑擴散層108的厚度變薄，其擴散深 度不會明顯降低，能夠防止η型摻雜劑擴散層丨〇8與第一配 線11 6之間接觸電阻的增加，亦可防止η型掺雜劑 108的接點漏電〇 ^ 依據此MOS型半導體裝置的製造過程，不需要如圖 10(c)之習知技藝所示在渠溝隔離絕緣膜1〇5的表面上選擇 性的形成一蝕刻阻絕膜。除此之外，並不需要如習知技藝 一般成長多晶矽膜以形成蝕刻阻絕膜及非等向 以形成側壁的步驟。在本發明的步驟中，#開==膜 時，需要形成第二防護膜111及對第三防護膜ln進行蝕刻 的步驟，但可以在形成層間絕緣膜i 12期間連續形成第三 防護膜111，且對第二防護膜111的姓刻可 膜U 3進行㈣時連續進行。因&，本發明的在二層可門以邑達緣 到較習知技藝（其中沉積與蝕刻步驟需分 製程及更短的處理時間。 ^ 另外，如上述實施例所述，在η型摻雜劑擴散層丨〇8鄰 近開電極107的區域開通接觸孔113時，第一防護膜1〇9形 成在閘電極107上表面，而第二防護膜11〇形成在閘電極 107的側邊，使得即使開通接觸孔113時，遮罩用光阻膜的 開口窗大於η型推雜劑擴散層108的區域，層間絕緣膜11£ 與第一及第二防護膜109, 110之間適當的蝕刻比例可以防Page 18 -------- Xianxun 5 d_____ V. Description of the invention (14) — When the protective film 111 is etched, there is an etching selectivity between the silicon nitride (and the third protective ytterbium) and silicon. As a result, the surface of the n-type dopant diffusion layer i08 is only slightly etched. Therefore, even if the thickness of the n-type dopant diffusion layer 108 becomes thin due to the over-molded MOS-type semiconductor device, the diffusion depth will not be significantly reduced, and the n-type dopant diffusion layer and the first wiring can be prevented. The increase in contact resistance between 11 and 6 can also prevent the contact leakage of the n-type dopant 108. According to the manufacturing process of this MOS-type semiconductor device, it is not necessary to display the channel as shown in the conventional art of FIG. 10 (c). An etching stopper film is selectively formed on the surface of the trench isolation insulating film 105. In addition, the steps of growing a polycrystalline silicon film to form an etch stop film and anisotropic forming a sidewall as in the conventional art are not required. In the step of the present invention, when # open == film, the steps of forming the second protective film 111 and etching the third protective film ln are required, but the third protective film 111 may be continuously formed during the formation of the interlayer insulating film i 12 In addition, the instant engravable film U 3 of the second protective film 111 is continuously performed. Because of & the present invention achieves a relatively high level of skill in the second floor of Comen (where the deposition and etching steps require separate processes and shorter processing times. In addition, as described in the above embodiment, in the n-type When the contact hole 113 is opened in a region adjacent to the open electrode 107 in the dopant diffusion layer, a first protective film 10 is formed on the upper surface of the gate electrode 107, and a second protective film 11 is formed on the side of the gate electrode 107. So that even when the contact hole 113 is opened, the opening window of the masking photoresist film is larger than the area of the n-type dopant diffusion layer 108, and the interlayer insulation film 11 £ and the first and second protective films 109, 110 are appropriately Etching ratio can prevent
五、發明說明（15) 406354 士閑電極m在層間絕緣膜112的蝕刻過程中 第一及第二防護膜⑺^❹會受到部分蝕刻。因此丨^ 到之接觸孔113被限定在閘電極107之陣列方向（^ =向）由第二防護膜11G所夾的區域，以及獻方向垂直（即 =1之Y方向）由渠溝隔離絕緣膜1〇5上之第三防護膜丨1 壤f的區域；結果此區域由自我定位所界定。目此 因為高積體化M0S型半導體裝置造成接觸孔尺寸變小/而 =寸的縮小需要開口窗更高精確度的定位，藉由上述自我 定位，接觸孔11 3的開通自我定位得以達到足夠的精確 度0 在上述實施例中，當第三防護膜^1較薄時，第一及 第=防護膜109, 110可為矽氮化物膜。在圖7的步驟中，對 第二防護膜111進行蝕刻時，可以使得第三防護膜丨丨丨更易 受到蝕刻而在受到蝕刻的角落，即第三防護膜丨1上與第一 及第二防護膜109, U0的接觸點，具有較快的蝕刻速率。 因，，即使較下層，即第一及第二防護膜1〇9, 11〇露出， 亦能夠防止此等防護膜受到蝕刻。因此，能夠製造出更薄 的第二防護膜111，使得相鄰閘電極之間的距離縮短，而 利於較高的集積度。 圖9(a)與（b)分別為將本發明應用於DRAM所得之平面 布局及沿線段C-C所得之剖面圖。與上述實施例中相同的 元件，則採用相同的參照數號。在此實施例中，接觸孔 113開通到n型摻雜劑擴散層1〇8d做為鄰近M〇s電晶體之區 域的沒極區域，各M〇s電晶體構成一記憶單元，且一位元V. Description of the Invention (15) 406354 During the etching of the interlayer insulating film 112, the first and second protective films ⑺ ^ will be partially etched. Therefore, the contact hole 113 is limited to the area sandwiched by the second protective film 11G in the array direction (^ = direction) of the gate electrode 107, and the vertical direction (that is, the Y direction of = 1) is insulated by the trench. The third protective film on the film 105 is an area of soil f; as a result, this area is defined by self-positioning. At present, because the high-integration M0S type semiconductor device causes the contact hole size to be reduced, and the reduction of the inch size requires more accurate positioning of the opening window. With the above self-positioning, the opening and self-positioning of the contact hole 113 can be sufficient. In the above embodiment, when the third protective film ^ 1 is thin, the first and third protective films 109, 110 may be silicon nitride films. In the step of FIG. 7, when the second protective film 111 is etched, the third protective film 丨 丨 丨 can be more susceptible to being etched and is etched in the corner, that is, the third protective film 丨 1 and the first and second The contact point of the protective film 109, U0 has a faster etching rate. Therefore, even if the lower layers, that is, the first and second protective films 10, 110 are exposed, these protective films can be prevented from being etched. Therefore, a thinner second protective film 111 can be manufactured, so that the distance between adjacent gate electrodes is shortened, which is conducive to a higher degree of integration. Figures 9 (a) and (b) are respectively a plan layout obtained by applying the present invention to a DRAM and a cross-sectional view taken along the line segment C-C. The same components as those in the above-mentioned embodiment are given the same reference numerals. In this embodiment, the contact hole 113 is opened to the n-type dopant diffusion layer 108d as the non-polar region of the region adjacent to the Mos transistor. Each Mos transistor constitutes a memory cell, and one bit yuan
第20頁 五、發明說明（16) iMa54Page 20 V. Description of Invention (16) iMa54
線形成做為第一配線116。在形成一覆蓋位元線116的第_ 層間絕緣膜11 7後，以相似的方法開通一接觸孔丨丨8，通— 第二層間絕緣膜11 7與層間絕緣膜1 1 2到達一η型掺雜劑擴^ 散層1 0 8 s做為源極區域。開通接觸孔11 3與11 8時，使用較 第三防護膜111更具蝕刻選擇性者可能使渠溝隔離絕緣膜 105與η型摻雜劑擴散層l〇8d，108s如同上述實施例一般受 到限制。此外’阻絕金屬膜119與一配線材料12〇(例 被埋入接觸孔118以形成一儲存電極121。儲存電極121 : 電容絕緣膜122、及一形成於儲存電極121上表面之計數器 電極123構成一電容124 ’用來儲存記憶資訊電荷，其受到 第三層間絕緣膜125的覆蓋。 如前文所述，本發明可應用於一DRAM，在開通接觸孔 113以電性連接到n型摻雜劑擴散層1〇8d與位元線丨16做為 一記憶單元，以及開通接觸孔11 8以電性連接到另一n型摻 雜劑擴散層108s與電容124時，使用從第一到第三防護膜 1 〇 9，11 〇，及111進行蝕刻，以防止渠溝隔離絕緣膜丨〇 5與^ 型摻雜劑擴散層1 〇 8 d，1 0 8 s被餘刻；防止渠溝隔離絕緣膜 105隔離特性的劣化；及防止η型掺雜劑擴散層1〇8d，1〇8s 中接觸電阻及接點漏電的增加。除此之外，即使用來開通 接觸孔的遮罩之開口窗比接觸孔的開口更大，利用防護膜 1〇9’ 11〇，及π!而得之自我定位能夠達成具有微小開口尺 寸之接觸孔的開通，因而促成高度積體化之DRAM的製造。 在本發明中’上述第一、第二、第三防護膜可以使用 相較於層間絕緣膜與渠溝隔離絕緣膜具有適當蝕刻選擇性A line is formed as the first wiring 116. After forming the first interlayer insulating film 1 17 covering the bit line 116, a contact hole is opened in a similar manner. The second interlayer insulating film 11 7 and the interlayer insulating film 1 1 2 reach an n-type. The dopant diffusion layer 108s is used as the source region. When the contact holes 11 3 and 11 8 are opened, the use of those with more etch selectivity than the third protective film 111 may cause the trench isolation insulating film 105 and the n-type dopant diffusion layer 108d, 108s to be generally affected as in the above embodiment. limit. In addition, the barrier metal film 119 and a wiring material 120 (for example, are buried in the contact hole 118 to form a storage electrode 121. The storage electrode 121 includes a capacitor insulating film 122 and a counter electrode 123 formed on the upper surface of the storage electrode 121. A capacitor 124 'is used to store the memory information charge, which is covered by the third interlayer insulating film 125. As described above, the present invention can be applied to a DRAM, and the contact hole 113 is opened to be electrically connected to the n-type dopant. When the diffusion layer 108d and the bit line 16 are used as a memory cell, and the contact hole 118 is electrically connected to another n-type dopant diffusion layer 108s and the capacitor 124, the first to the third are used. The protective films 10, 9, 10, and 111 are etched to prevent the trench isolation insulation film. The 05 and ^ -type dopant diffusion layers 1 08 d, 108 s are left uncut; the trench isolation insulation is prevented. The deterioration of the isolation characteristics of the film 105; and the prevention of an increase in contact resistance and contact leakage in the n-type dopant diffusion layers 108d and 108s. In addition, even the opening window of the mask used to open the contact hole Larger than the opening of the contact hole, using a protective film 109 '11〇 And π! 'S self-positioning can achieve the opening of contact holes with a small opening size, thereby promoting the manufacture of highly integrated DRAM. In the present invention, the above-mentioned first, second, and third protective films can be used with Appropriate etching selectivity compared to interlayer insulation film and trench isolation insulation film
第21頁 4〇β354 五、發明說明（17) 之任何材質，而並非限制於實施例中所提者。在前 例中，本發明被應用於一具有η通道M〇s電晶體之半 置中，當然本發明亦可應用於具有口通道M〇s 性電晶體之半導體裝置中。 稷次雙極 述，依據本發明，—防護膜形成並覆蓋位於 千導體基材主要表面上的一渠溝隔離絕緣膜及一半導 =，相較於防護膜具有蝕刻選擇性之層間絕緣膜形成於 。臈上；對層間絕緣膜進行蝕刻以開通接觸孔係在層間 緣膜較防護膜有更高蝕刻速率的條件下進行，如此能夠 =最少在層間絕緣臈蝕刻期間以防護膜覆蓋渠溝隔離絕 眩的表面以防止其表面受到#刻；防止渠溝隔離絕緣膜 =離特性的劣化；相似的防止摻雜劑擴散層表面受到蝕 =，並防止摻雜劑擴散層之接觸電阻及接點漏電的增加。 外，即使用來開通接觸孔的遮罩之開口窗比摻雜劑擴散 s的表面區域更大，防護膜可以防止必要區域受到侵蝕； :f我定位能夠使接觸孔的開通受到精密的控制，因而. 成兩度積體化之半導體裝置的製造。 第22頁Page 21 4〇β354 5. The material of the invention description (17) is not limited to those mentioned in the examples. In the previous example, the present invention is applied to a half device having an n-channel Mos transistor. Of course, the present invention can also be applied to a semiconductor device having a port channel Mos transistor. According to the present invention, according to the present invention, a protective film is formed and covers a trench isolation insulating film and a semiconducting film on the main surface of a thousand-conductor substrate. Compared with the protective film, an interlayer insulating film is formed with an etching selectivity. to.臈; Etching the interlayer insulation film to open the contact hole is performed under the condition that the interlayer edge film has a higher etch rate than the protective film, so that it can = at least cover the trenches with a protective film to isolate the glare during the interlayer insulation 臈 etching To prevent the surface from being engraved; to prevent the trench isolation insulation film from deteriorating the characteristics; similarly to prevent the surface of the dopant diffusion layer from being corroded, and to prevent the contact resistance of the dopant diffusion layer and the contact leakage increase. In addition, even if the opening window of the mask used to open the contact hole is larger than the surface area of the dopant diffusion s, the protective film can prevent the necessary area from being eroded;: f positioning can make the opening of the contact hole under precise control, Thus, the manufacture of semiconductor devices that have been integrated twice. Page 22
Claims (1)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10122240A JPH11317448A (en) | 1998-05-01 | 1998-05-01 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW406354B true TW406354B (en) | 2000-09-21 |
Family
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW088106994A TW406354B (en) | 1998-05-01 | 1999-04-29 | A semiconductor device and a manufacturing process therefor |
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| Country | Link |
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| JP (1) | JPH11317448A (en) |
| KR (1) | KR19990087996A (en) |
| DE (1) | DE19919962A1 (en) |
| TW (1) | TW406354B (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002198500A (en) * | 2000-12-27 | 2002-07-12 | Mitsubishi Electric Corp | Semiconductor integrated circuit device and manufacturing method therefor |
| KR100880332B1 (en) | 2007-09-06 | 2009-01-28 | 주식회사 하이닉스반도체 | Method of manufacturing contact plug of semiconductor device |
| TW201007885A (en) * | 2008-07-18 | 2010-02-16 | Nec Electronics Corp | Manufacturing method of semiconductor device, and semiconductor device |
-
1998
- 1998-05-01 JP JP10122240A patent/JPH11317448A/en active Pending
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1999
- 1999-04-29 TW TW088106994A patent/TW406354B/en not_active IP Right Cessation
- 1999-04-30 DE DE19919962A patent/DE19919962A1/en not_active Ceased
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| KR19990087996A (en) | 1999-12-27 |
| JPH11317448A (en) | 1999-11-16 |
| DE19919962A1 (en) | 1999-11-11 |
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