KR19990087996A - A semiconductor device and a manufacturing process therefor - Google Patents

Abstract

The present invention can prevent the deterioration of the separation characteristics in the trench isolation insulating film, prevent the increase of contact resistance and the leakage of the junction in the impurity diffusion layer, and the semiconductor device which is highly integrated and does not have a complicated manufacturing process, and a manufacturing process thereof. to provide. The process includes forming a trench isolation insulating film formed on the main surface of the silicon substrate and first to third protective films covering the MOS transistor, forming an interlayer insulating film having etching selectivity on the protective film, and an etching rate for the protective film. And etching the interlayer insulating film at a higher etching rate to open the contact holes.

During the etching process, the trench isolation insulating film covered with the protective film is not etched, so that the separation characteristics do not deteriorate.

The protective film prevents the surface of the trench isolation insulating film from being etched, prevents increase in contact resistance and junction leakage, as well as self-alignment even when the opening window of the mask for opening the contact hole is larger than the surface area of the impurity diffusion layer. This allows the opening size of the contact hole to be appropriately opened.

Description

A SEMICONDUCTOR DEVICE AND A MANUFACTURING PROCESS THEREFOR

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a trench isolation insulating film on a main surface of a semiconductor substrate, and electrically connected to an element region formed on the main surface of the semiconductor substrate through contact holes. In particular, the present invention relates to semiconductor devices and their fabrication processes that meet the demand for high integration.

As a semiconductor device has been highly integrated, an inter-element isolation insulating film for isolation and isolation between elements formed on a semiconductor substrate, the trench isolation insulating film being formed by forming a trench on the surface of the semiconductor substrate and then filling an insulating material in the trench. Technology has been used. Trench isolation insulating films are advantageous for highly integrated devices because they do not cause bird's beaks that occur in field insulating films formed by LOCOS technology. In such a trench isolation insulating film, misalignment may occur when opening a contact hole for electrical connection to the diffusion layer, which causes etching of the trench isolation insulating film, and deteriorates the separation characteristic with the adjacent diffusion layer. Come. FIG. 10A illustrates a trench 202 formed on the main surface of the semiconductor substrate 201, and a silicon oxide film 203 formed on the trench by thermal oxidation, for example, in a CVD technique. As a result, a silicon oxide film 204 is formed to form a trench isolation insulating film 205. In the region partitioned by the trench isolation insulating film 205, the gate insulating film 206, the gate electrode 207, and the impurity diffusion layer 208 as a source-drain region are formed to form a MOS transistor. An interlayer insulating film 209 formed of a silicon oxide film covering the MOS transistor and the trench isolation insulating film is formed, and the contact hole 210 is opened in the interlayer insulating film to ensure electrical connection to the impurity diffusion layer 208.

At the opening of the contact hole 210, the interlayer insulating film is selectively etched by selectively etching using a photoresist (not shown) as a mask. Therefore, if there is a misalignment in the photoresist mask, the trench isolation insulating film 205 is partially etched when the interlayer insulating film 209 is etched. In general, during etching of the contact hole, if any residual etching residue of the insulating film remains on the base surface of the contact hole, the contact failure and contact resistance are increased, so that the insulating film is slightly overetched when the contact hole is opened. This etches the trench isolation insulating film 205 and eventually forms a concave surface X on the surface. Therefore, when the conductive member 211 is embedded in the contact hole 210 after the opening of the contact hole 210 to form an electrical connection structure to the impurity diffusion layer, a part of the conductive member 211 is formed in the trench isolation insulating film 205. Inflow into the etched concave surface X causes a reduction in the effective separation distance indicated by the arrows in the drawing in the trench isolation insulating film 205, thus leading to deterioration of the separation characteristics for insulation separation.

To solve this problem, for example, JP-A 10-12733 shows an etching stopper film 212 such as a polysilicon film having etching selectivity compared to the interlayer insulating film 209, as shown in Fig. 10C. As described above, a technique of selectively forming the trench isolation insulating film 205 which is etched at the opening of the contact hole 210 is disclosed. According to the above publication, a trench isolation insulating film 205 is formed, a polysilicon film is grown on all surfaces, leaving an oxide film used to form the trench, and the polysilicon film is anisotropically etched to remain as sidewalls on the side of the oxide film. By doing so, a soft etching stopper film 212 is formed at the edge of the trench isolation insulating film 205. In the semiconductor device according to the above technique, misalignment occurs in the photoresist mask when the contact hole 210 is opened, and a portion of the trench isolation insulating film 205 is formed in the contact hole 210 as shown in FIG. Even when exposed, the etching stopper film 212 prevents the trench isolation insulating film 205 from being etched, and thus is effective in solving the above problem.

The technique disclosed in the publication is effective to prevent the trench isolation insulating film 205 from being etched during overetching of the interlayer insulating film 209 by using the etching stopper film 212 formed on a part of the surface of the trench isolation insulating film 205. Do. However, when etching the interlayer insulating film wider than the etching stopper film 212, this technique is not effective enough to prevent the trench isolation insulating film 205 from being etched in the region where the etching stopper film is not covered. In particular, in recent years, as semiconductor devices have been highly integrated, the size of device patterns has become several hundred nanometers or less. However, it is difficult to reduce the size of the mask pattern for opening of the contact hole in response to such a size reduction. As a result, there has been an increasing demand for the alignment of photoresist masks with great accuracy. Therefore, if the area for the opening window of the mask pattern is aligned on the area outside the etching stopper film 212 and etching is performed, the problem is imminent.

In addition, the above technique cannot prevent the surface of the impurity diffusion layer 208 on the main surface of the semiconductor substrate 201 from being etched during the over etching of the interlayer insulating film 209. Therefore, when the impurity diffusion layer 208 is thin due to the highly integrated semiconductor device, the effective depth of the impurity diffusion layer 208 is reduced to increase the contact resistance to the impurity diffusion layer 208 or to increase the junction leakage.

In addition, the technique of this publication includes grown polysilicon for forming an etch stopper film 212 left as a sidewall after anisotropic etching. Therefore, since the polysilicon growth process and the anisotropic etching process must be added to the existing manufacturing process of the semiconductor device, the manufacturing process becomes more complicated.

DISCLOSURE OF THE INVENTION An object of the present invention is to provide a semiconductor device capable of preventing deterioration of separation characteristics of a trench isolation insulating film, preventing increase in contact resistance and junction leakage in an impurity layer, and having high integration without complicating the manufacturing process thereof. The manufacturing process is provided.

A main aspect of the present invention is a trench isolation insulating film composed of an insulating material embedded in a trench formed on a semiconductor substrate, an impurity diffusion layer formed on a semiconductor substrate partitioned by a trench isolation insulating film, an interlayer insulating film formed on a surface of a semiconductor substrate, an interlayer A semiconductor device comprising a contact hole opening in an insulating film and providing an opening to an impurity diffusion layer, and a wiring made of a conductive material disposed in the contact hole, the semiconductor device being between a semiconductor substrate and an interlayer insulating film except for a region in which the contact hole is opened. A protective film having etching selectivity is formed in comparison with an insulating film including an interlayer insulating film and a trench isolation insulating film.

In particular, the most preferred embodiment of the present invention is a MOS transistor including an impurity diffusion layer as a gate electrode and a source drain region is formed on the semiconductor substrate, the first protective film is formed on the gate electrode, the second protective film is formed of the gate electrode It is formed on the side, the third passivation film is formed over the entire surface of the semiconductor substrate covering the first and second passivation film, an interlayer insulating film having an etching selectivity over the first to the third passivation film is formed on the third passivation film And a contact hole for providing an opening to the impurity diffusion layer is opened in the interlayer insulating film and the third protective film.

The contact hole preferably has an opening size larger in at least one of the plane directions X and Y in the upper region of the interlayer insulating film than in the planar region of the semiconductor substrate partitioned by the first to third protective films and the trench isolation insulating film.

The present invention can be applied to a DRAM, wherein the MOS transistor constitutes a memory cell of the DRAM, and the contact hole includes a contact hole for connecting the bit line to one of the impurity diffusion layers constituting the source drain region of the MOS transistor, And at least one of the contact holes for connecting the electrode wiring for storing charge to the other impurity diffusion layer.

The present invention also provides a process for forming a trench on a main surface of a semiconductor substrate; Embedding an insulating material in the trench to form a trench isolation insulating film; Forming a semiconductor element composed of at least one impurity diffusion layer on a main surface of the semiconductor substrate partitioned by a trench isolation insulating film; Forming a protective film over the entire surface of the semiconductor substrate; Forming an interlayer insulating film having etching selectivity over the protective film on the protective film; And sequentially etching the interlayer insulating film and the protective film to open the contact holes reaching the impurity diffusion layer.

The step of forming a semiconductor element includes a step of forming a stacked structure of a gate oxide film, a gate electrode, and a first passivation film on a main surface of a semiconductor substrate; Forming an impurity diffusion layer as a source drain region on a main surface of the semiconductor substrate sandwiching the gate electrode; And forming a second passivation film on the side surface of the gate electrode, wherein forming the passivation film covering the entire surface of the semiconductor substrate comprises forming a third passivation film covering both the first and second passivation films. It is preferable.

The opening process of the contact hole includes the steps of etching the interlayer insulating film at an etching rate higher than the etching rate for the third protective film, and after etching, etching the third protective film at an etching rate higher than the etching rate for the trench isolation insulating film. It is composed.

The opening process of the contact hole is preferably performed using a mask having an opening window larger in at least one of the plane X and Y directions than the planar region of the semiconductor substrate partitioned by the first to third protective films and the trench insulating film.

According to the present invention, even when misalignment of the photoresist mask used to open the contact hole occurs in the etching process for opening the contact hole in the interlayer insulating film, effective separation of the trench isolation insulating film caused by etching of the trench isolation insulating film Due to the reduction of the distance, deterioration of the separation characteristic at the time of insulation separation can be prevented. This is because the trench isolation insulating film is covered with a protective film, that is, a third protective film. Moreover, since the surface of the impurity diffusion layer is covered with a protective film, that is, a third protective film, the surface of the impurity diffusion layer is hardly etched during the etching of the interlayer insulating film. Therefore, an increase in contact resistance and junction leakage of the impurity diffusion layer can be effectively prevented.

Since the gate electrode is covered by the first to third protective films, when opening the contact hole in the area adjacent to the gate electrode, the contact for opening the contact hole, even if the mask for opening the contact hole has a larger opening size than the area of the impurity diffusion layer, The opening of the hole can be suppressed into the area partitioned by the first to third protective films. Therefore, even when the opening size of the contact hole is reduced due to the highly integrated semiconductor device, and even when the difficulty of such size reduction requires high precision alignment of the opening window, the contact hole can be appropriately opened by self alignment.

1 is a planar layout diagram of an embodiment in which the present invention is applied to a MOS type semiconductor device.

2 is an enlarged view of a cross section taken along line A-A and line B-B of FIG.

FIG. 3 shows a first process of the semiconductor device manufacturing process shown in FIGS. 1 and 2 in the cross-sectional structure of FIG.

FIG. 4 shows a second process of the semiconductor device manufacturing process shown in FIGS. 1 and 2 in the cross-sectional structure of FIG.

FIG. 5 shows a third process of the semiconductor device manufacturing process shown in FIGS. 1 and 2 in the cross-sectional structure of FIG.

FIG. 6 illustrates a fourth process of the semiconductor device manufacturing process illustrated in FIGS. 1 and 2 in the cross-sectional structure of FIG. 2.

FIG. 7 shows a fifth process of the semiconductor device manufacturing process shown in FIGS. 1 and 2 in the cross-sectional structure of FIG.

FIG. 8 shows a sixth process of the semiconductor device manufacturing process shown in FIGS. 1 and 2 in the cross-sectional structure of FIG.

Fig. 9 is a sectional view taken along line C-C and a planar layout diagram in which the present invention is applied to a DRAM.

10 is a cross-sectional view showing a problem and proposed improvement of the prior art.

<Explanation of symbols for the main parts of the drawings>

101: p-type silicon substrate

105: trench isolation insulating film

106: gate oxide film

107: gate electrode

108: n-type impurity diffusion layer

109: first protective film

110: second protective film

111: third protective film

112: interlayer insulating film

113: contact hole

116: first wiring

117: second interlayer insulating film

118: contact hole

124 capacitors

Preferred embodiments of the present invention will be described with reference to the accompanying drawings.

1 is a planar layout diagram of an embodiment in which the present invention is applied to a MOS semiconductor device. (A) and (b) is sectional drawing along the AA line and the BB line of FIG. Trench 102 having a depth of 100 to 300 nm is formed on the p-type silicon substrate 101. A silicon thermal oxide film (SiO ₂ ; 103) having a thickness of 20 to 30 nm is formed on the inner surface of the trench 102, and the CVD silicon oxide film (SiO ₂ ) 104 is embedded in the trench to form a trench isolation insulating film 105. On the main surface of the silicon substrate 101, a gate oxide film 106 made of silicon oxide film SiO ₂ and a gate electrode 107 made of polysilicon are formed. An n-type impurity diffusion layer 108 is formed as a source drain region on the main surface region of the silicon substrate 101 partitioned by the trench isolation insulating film 105. The gate oxide film 106 and the gate electrode 107 constitute a MOS transistor. The first passivation film 109 composed of the silicon oxide film SiO ₂ is stacked on the gate electrode 107, and the second passivation film 110 composed of the silicon oxide film SiO ₂ is formed as the sidewall and serves as the gate electrode 107. It is formed on the side of the gate oxide film 106. A third passivation film 111 composed of a silicon nitride film Si ₃ N ₄ having a thickness of 20 to 40 nm is formed on all surfaces of the silicon substrate 101 including the gate electrode 107 and the trench isolation insulating film 105. An interlayer insulating film 112 of BPSG having a thickness of 1.0 μm is formed on the third passivation film 111, and the contact hole 113 reaching the n-type impurity diffusion layer 108 between the gate electrodes 107 is an interlayer insulating film 112. ) And the third passivation layer 111. The first wiring 116 in which the barrier metal film 114 such as titanium nitride (TiN) and the wiring film 115 such as tungsten (W) are stacked thereon is electrically connected to the n-type impurity diffusion layer 108. Is formed in the contact hole 113.

The manufacturing process of the MOS type semiconductor device will be described with reference to Figs. In each of these figures, (a) and (b) correspond to sectional views taken along line A-A and line B-B in Fig. 1, respectively. First, as shown in FIG. 3, a trench isolation insulating film 105 is formed on a given region of the main surface of the p-type silicon substrate 101 as is conventional. For example, the silicon oxide film 131 and the silicon nitride film 132 are stacked on the surface of the p-type semiconductor substrate 101 as an oxidation resistant film and then selectively etched to leave the element formation region. The trench 102 is formed by etching the silicon substrate 101 to a depth of 100 to 300 nm using the silicon nitride film 132 as a mask. Then, the inner surface of the trench 102 is thermally oxidized to form a silicon thermal oxide film 103 having a thickness of 20 to 30 nm. Then, a silicon oxide film 104 deeper than the trench 102 is buried by the CVD technique. The buried silicon oxide film 104 is etched, for example, by CMP (Chemical Mechanical Polishing), and then the silicon nitride film 132 is etched away to form a trench isolation insulating film 105.

Then, as shown in FIG. 4, the silicon oxide film 131 in the element formation region partitioned by the trench isolation insulating film 105 is etched away, and thermal oxidation is performed again to obtain a thickness of about 20 nm on the main surface of the silicon substrate. Gate oxide film 106 is formed. Then, the polysilicon film 107 is grown to a thickness of about 80 to 120 nm over all surfaces, and a silicon oxide film 109 serving as the first protective film is formed thereon to a thickness of about 50 nm. Then, using a photoresist (not shown) as a mask, the silicon oxide film 109 and the polysilicon film 107 are selectively etched in a given pattern so that the first passivation film 109 on the gate electrode 107 and the gate electrode. ) At the same time. In the selective etching, the polysilicon film 107 is etched at an etching rate higher than that of the gate oxide film 106. Therefore, the etching can be stopped at an appropriate point to leave a part of the gate oxide film 106. Therefore, it is not necessary to etch the trench isolation insulating film 105 in this process. Then, the remaining gate oxide film 106 is removed with, for example, buffered hydrofluoric acid, and the semiconductor substrate is formed by a self-aligning technique using the gate electrode 107 and the trench isolation insulating film 105 as a mask. An n-type impurity diffusion layer 108 is formed as a source drain region by ion implantation of an n-type impurity such as arsenic on the main surface of 101.

Then, as shown in FIG. 5, the silicon oxide film is grown to a thickness of about 80 nm over the entire surface, and then the silicon oxide film is anisotropically etched by RIE technology to form the first protective film 109, the gate electrode 107, And sidewalls on the side surfaces of the gate oxide film 106 as the second protective film 110. Then, as shown in Fig. 6, a silicon nitride film is formed as a third protective film 111 with a thickness of 20 to 40 nm on the entire surface, and then an interlayer insulating film 112 of BPSG having a thickness of 1.0 mu m is formed thereon. do.

Then, as shown in FIG. 7, the contact hole 113 is opened to electrically connect the n-type impurity diffusion layer 108 to the interlayer insulating film 112. In the opening of the contact hole 113, a photoresist film (not shown) having a window in the opening area of the contact hole is formed on the surface of the interlayer insulating film 112, and using the photoresist film as a mask, the interlayer insulating film ( The plasma etching process is performed using C ₄ F ₈ / Ar / O ₂ gas under the condition that the etching rate of 50: 1 is between 112) and the third passivation film, that is, between the BPSG film and the silicon nitride film. Therefore, the third protective film 111 acts as an etching stopper when the interlayer insulating film 112 is etched, thereby reducing the film reduction of the third protective film 111 by about 50 even when the over etching amount of the interlayer insulating film 112 is set to 50%. It is reduced to%, and therefore the etching of the third protective film can be suppressed to about 1/2 on the surface side thereof. Therefore, the surfaces of the n-type impurity diffusion layer 108 and the trench isolation insulating film 105 (silicon oxide films 103 and 104) are never etched. The first and second protective films 109 and 110 are also never etched.

Then, as shown in FIG. 8, the third protective film 111 remaining on the base of the contact hole 113 is etched away by a plasma etching technique using CHF ₃ / O ₂ gas. In that process, a condition is selected such that the etching rate is about 2: 1 between the third protective film 111 and the trench isolation insulating film 105, that is, between the silicon nitride film and the silicon oxide film. The third passivation layer 111 left in the contact hole 113 has a depth of about 10 to 20 nm. Therefore, even when the over etching amount of the third passivation film 111 is 50%, the film reduction of the trench isolation insulating film 105 can be suppressed to about 10 to 15 nm. On the surface of the n-type impurity diffusion layer 108, silicon is etched at a lower rate than the silicon nitride film, so that even if the third protective film 111 is overetched, the surface etching of the n-type impurity diffusion layer 108 is minimized, and thus n-type The depth of the impurity diffusion layer 108 hardly decreases. It is apparent that the first and second passivation layers 109 and 110 are not etched even when the third passivation layer 111 is etched in the contact hole 113, so that the gate electrode 107 is not exposed.

Then, as shown in FIG. 2, a barrier metal film 114 made of titanium nitride is laminated on the surface of the interlayer insulating film 112, and then a wiring film 115 made of tungsten is stacked thereon. Then, the first wiring 116 is formed in the contact hole 113 which is selectively etched in a given pattern and electrically connected to the n-type impurity diffusion layer 108. Thus, the MOS type semiconductor device shown in Figs. 1 and 2 is provided.

As described above, in the process of the present invention, before forming the interlayer insulating film 112, the third protective film 111 made of a material having etching selectivity compared to the interlayer insulating film 112 is formed. It forms on the surface, especially on the surface of the trench isolation insulating film 105 and the n-type impurity diffusion layer 108. Therefore, even when misalignment occurs in the photoresist mask used to open the contact hole 113 in the etching process for opening the contact hole 113 in the interlayer insulating film 112, the trench isolation insulating film 105 is not etched. Do not. In the continuous etching removal of the third protective film 111, even when the trench isolation insulating film 105 is slightly etched, a concave surface as shown in FIG. 10B is formed on the surface of the trench isolation insulating film 105. The etching amount can be sufficiently suppressed so as not to be formed. Therefore, even when the first wiring 116 is embedded in the contact hole 113 during the formation process of the first wiring 116, the effective separation distance of the trench isolation insulating film 105 is shortened by the first wiring 116. It is possible to prevent the deterioration of the separation characteristics with respect to the insulation separation.

In the process of simultaneously etching the interlayer insulating film 112 for opening the contact hole 113, the surface of the n-type impurity diffusion layer 108 is covered by the third protective film 111, so that the n-type impurity diffusion layer 108 Is not etched. In addition, during the etching of the third passivation film 111, the surface of the n-type impurity diffusion layer 108 is hardly etched due to the etching selectivity between the silicon nitride film (ie, the third passivation film) and silicon. Therefore, when the n-type impurity diffusion layer 108 is thin due to the highly integrated MOS-type semiconductor device, its diffusion depth is not greatly reduced, which is due to the contact resistance between the n-type impurity diffusion layer 108 and the first wiring 116. The increase can be prevented, and the junction leakage in the n-type impurity diffusion layer 108 can be prevented.

In terms of the manufacturing process of the MOS semiconductor device, it is not necessary to selectively form an etching stopper film on the surface of the trench isolation insulating film 105 in the prior art as shown in Fig. 10C. In addition, it is not necessary to perform a process required in the prior art in which a polysilicon film is grown to form an etching stopper film, and the film is anisotropically etched and left as a sidewall. In the process of the present invention, a process of forming the third passivation film 111 and etching away the third passivation film 111 at the time of opening of the contact hole is necessary, but the third passivation film 111 is formed at the time of forming the interlayer insulating film 112. The third protective film 111 is continuously etched when the interlayer insulating film 113 is etched continuously. Therefore, the process of the present invention can achieve more simplified process and shorter process time compared to the process of the prior art in which the deposition and etching processes are performed separately.

Furthermore, as described in the above embodiment, in the process of opening the contact hole 113 in the region of the n-type impurity diffusion layer 108 adjacent to the gate electrode 107, the first protective film 109 is formed by the gate electrode ( 107 is formed on the upper surface, and the second protective film 110 is formed on the side surface of the gate electrode 107, so that the opening window of the photoresist film, which is a mask at the opening of the contact hole 113, is formed of an n-type impurity diffusion layer ( Even if the size is wider than the region 108, the first and second passivation layers may be formed during etching of the interlayer insulation layer 112 by having an appropriate etching rate between the interlayer insulation layer 112 and the first and second passivation layers 109 and 110. Although the 109 and 110 are etched to some extent, the gate electrode 107 is prevented from being etched. Therefore, the opened contact hole 113 is suppressed to a region sandwiched with the second passivation layer 110 in the array direction of the gate electrode 107, that is, in the X direction of FIG. 1, and the X-direction on the trench isolation insulating film 105 It is suppressed to the area | region enclosed by the 3rd protective film 111 in the perpendicular direction, ie, the Y direction in FIG. In the end, regions are defined by self-alignment. Therefore, even when the opening size of the contact hole is reduced due to the highly integrated MOS type semiconductor device, and furthermore, even when a high precision alignment with respect to the opening window is absolutely necessary due to the difficulty of reducing the opening size of such contact hole, the self-alignment The contact hole 113 can be opened by appropriate precision.

In the above embodiment, when the third passivation film 111 is thin, each of the first and second passivation films 109 and 110 is a silicon nitride film. This is because, in the process of FIG. 7, the third passivation layer 111 is formed at a corner sensitive to etching in which the third passivation layer 111 contacts the first and second passivation layers 109 and 110 when the third passivation layer 111 is etched. Allows to etch relatively faster. Therefore, even when the lower layers, that is, the first and second protective films 109 and 110 are exposed, these protective films can be prevented from being etched. Therefore, since the third passivation film 111 can be made thinner, the distance between adjacent gate electrodes is reduced, which is advantageous for high integration.

9 (a) and 9 (b) are cross-sectional views taken along the plane layout and the C-C lines when the present invention is applied to a DRAM, respectively. The same elements as those of the above embodiment use the same reference numerals. In the present embodiment, the contact hole 113 is opened for the n-type impurity diffusion layer 108d as the drain region for the region adjacent to the MOS transistors constituting the memory cell, and the bit line is connected to the first wiring 116. It is formed as. After forming the second interlayer insulating film covering the bit line 116, in the same manner, the contact hole 118 passes through the second interlayer insulating film 117 and the interlayer insulating layer 112 as an n-type impurity diffusion layer (as a source region). 108s). In the opening of the contact holes 113 and 118, etching of the trench isolation insulating film 105 and the n-type impurity diffusion layers 108d and 108s is the same as in the above embodiment by using the etching selectivity compared to the third protective film 111. Can be suppressed. In addition, the storage electrode 121 is formed by embedding the barrier metal film 119 and the wiring material 120 such as tungsten in the contact hole 118. The storage electrode 121 and the counter electrode 123 formed on the upper surface of the storage electrode 121 as well as the capacitance insulating film 122 constitute a capacitor 124 for storing memory information charges, which is the third interlayer insulating film. It is coated by 125.

As described above, the present invention can be applied to DRAM, in which case the contact hole 113 for electrically connecting the n-type impurity diffusion layer 108d, which is one of the memory cells, to the bit line 116, and the other At the opening of the contact hole 118 for electrically connecting the n-type impurity diffusion layer 108s to the capacitor 124, etching is performed using the first to third protective films 109, 110, 111, and trench isolation. It is possible to prevent the insulating film 105 and the n-type impurity diffusion layers 108d and 108s from being etched, to prevent deterioration of the separation characteristics of the trench isolation insulating film 105, and to prevent the contact resistance in the n-type impurity diffusion layers 108d and 108s. Prevent increase and junction leakage. Further, even when the size of the opening window of the mask for opening the contact hole is larger than the size of the opening of the contact hole, the contact hole having an appropriate opening dimension is opened by self alignment using the protective films 109, 110, and 111, This makes possible the fabrication of highly integrated DRAMs.

In the present invention, the first, second, and third protective films described above are not limited to those described in the above embodiments, but are composed of any material having desired etching selectivity over the interlayer insulating film and the trench isolation insulating film. Can be. In the above embodiment, the present invention has been applied to a MOS type semiconductor device having an n-channel MOS transistor, but the present invention can also be applied to a MOS type semiconductor device having a p-channel MOS transistor or a bipolar transistor.

As described above, according to the present invention, a trench isolation insulating film formed on the main surface of the semiconductor substrate and a protective film covering the semiconductor element are formed. An interlayer insulating film having etching selectivity compared with the protective film is formed on the protective film. The interlayer insulating film is etched under the condition that the interlayer insulating film is etched at a higher rate than the protective film to open the contact hole, thereby at least covering the trench isolation insulating film surface with a protective film during the etching of the interlayer insulating film, thereby preventing the surface from being etched and trench isolation. It is possible to prevent deterioration of the insulating properties of the insulating film, to prevent etching of the surface of the impurity diffusion layer at the same time, and to increase the contact resistance and the leakage of the junction in the impurity diffusion layer. In addition, even when the opening window of the mask for the contact hole opening is wider than the surface area of the impurity diffusion layer, the protective film prevents the essential area of the semiconductor element from being etched, and the contact hole is controlled to an appropriately controlled opening size by self alignment. Openings, thus enabling the fabrication of highly integrated semiconductor devices.

Claims (9)

In a trench isolation insulating film composed of an insulating material embedded in a trench formed on a semiconductor substrate, an impurity diffusion layer formed on the semiconductor substrate partitioned by the trench isolation insulating film, an interlayer insulating film formed on the surface of the semiconductor substrate, the interlayer insulating film A semiconductor device comprising a contact hole that is opened and provides an opening to the impurity diffusion layer, and a wiring made of a conductive material disposed in the contact hole, A semiconductor device, wherein a protective film having an etching selectivity is formed between the semiconductor substrate and the interlayer insulating film except for the region where the contact hole is opened, compared with the insulating film including the interlayer insulating film and the trench isolation insulating film. . In a semiconductor device, A MOS transistor including an impurity diffusion layer as a gate electrode and a source drain region is formed on a semiconductor substrate, A first passivation layer is formed on the gate electrode, A second passivation film is formed on the side surface of the gate electrode, A third passivation film is formed over the entire surface of the semiconductor substrate covering the first and second passivation films, An interlayer insulating film having etching selectivity relative to the first to third protective films is formed on the third protective film, A contact hole for providing an opening to the impurity diffusion layer is opened in the interlayer insulating film and the third passivation film. A semiconductor device, characterized in that. 3. The contact hole according to claim 2, wherein the contact hole is at least one of the planar directions X and Y in the upper region of the interlayer insulating film than the planar region of the semiconductor substrate partitioned by the first to third protective films and the trench isolation insulating film. Semiconductor device having a larger opening size. 3. The capacitor of claim 2, wherein the MOS transistor constitutes a memory cell of a DRAM, and the contact hole is a contact hole for connecting a bit line to one of the impurity diffusion layers constituting the source drain region of the MOS transistor; And at least one of the contact holes for connecting the electrode wiring for storing the charge thereof to the other said impurity diffusion layer. 4. The capacitor of claim 3, wherein the MOS transistor constitutes a memory cell of a DRAM, and the contact hole is a contact hole for connecting a bit line to one of the impurity diffusion layers constituting the source drain region of the MOS transistor; And at least one of the contact holes for connecting the electrode wiring for storing the charge thereof to the other said impurity diffusion layer. In the semiconductor manufacturing process, Forming a trench on a main surface of the semiconductor substrate; Embedding an insulating material in the trench to form a trench isolation insulating film; Forming a semiconductor device including at least one impurity diffusion layer on a main surface of the semiconductor substrate partitioned by the trench isolation insulating film; Forming a protective film over the entire surface of the semiconductor substrate; Forming an interlayer insulating film having etching selectivity over the protective film on the protective film; And Sequentially etching the interlayer insulating film and the protective film to open a contact hole reaching the impurity diffusion layer Manufacturing process of a semiconductor device comprising a. The method of claim 6, The step of forming the semiconductor device, Forming a stacked structure of a gate oxide film, a gate electrode, and a first passivation film on a main surface of the semiconductor substrate; Forming an impurity diffusion layer as a source drain region on a main surface of the semiconductor substrate sandwiching the gate electrode; And Forming a second passivation layer on side surfaces of the gate electrode Including, The forming of the passivation layer covering the entire surface of the semiconductor substrate includes forming a third passivation layer covering both the first and second passivation layers. The manufacturing process of a semiconductor device characterized by the above-mentioned. The method of claim 6, wherein the opening of the contact hole comprises: etching the interlayer insulating film at an etching rate higher than an etching rate for the third passivation film, and after the etching, higher than an etching rate for the trench isolation insulating film. And a step of etching the third protective film at an etching rate. The opening step of the contact hole is preferably an opening larger in at least one of the planar X and Y directions than the planar region of the semiconductor substrate partitioned by the first to third passivation films and the trench insulating film. A process for manufacturing a semiconductor device, characterized in that it is performed using a mask having a window.