KR100424185B1 - method for fabricating transistor - Google Patents
method for fabricating transistor Download PDFInfo
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- KR100424185B1 KR100424185B1 KR10-2002-0000717A KR20020000717A KR100424185B1 KR 100424185 B1 KR100424185 B1 KR 100424185B1 KR 20020000717 A KR20020000717 A KR 20020000717A KR 100424185 B1 KR100424185 B1 KR 100424185B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823493—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
Abstract
본 발명은 셀 트랜지스터의 마진을 확보할 수 있는 트랜지스터 형성 방법에 관해 개시한다.The present invention discloses a transistor formation method capable of securing a margin of a cell transistor.
개시된 본 발명의 반도체장치의 제조 방법은 반도체기판에 제 1도전형의 불순물을 도핑하여 웰을 형성하는 단계와, 웰을 포함한 반도체기판의 일부분을 식각하여 소자의 활성영역을 정의하는 샬로우 트렌치를 형성하는 단계와, 샬로우 트렌치를 매립시키는 소자격리막을 형성하는 단계와, 소자격리막의 측면 및 상면 일부를 노출시키는 단계와, 노출된 소자격리막의 측면에 도전 스페이서를 형성하는 단계와, 도전 스페이서를 포함한 소자격리막 사이에 잔류되도록 실리콘 질화막을 형성하는 단계와, 결과물 상에 제 1도전형의 불순물을 도핑하여 도전 스페이서 하부에 제 1도전형 불순물 확산영역을 형성하는 단계와, 잔류된 실리콘 질화막을 제거하는 단계와, 결과의 기판 상에 게이트 절연막 및 게이트 전극 형성용 도전막을 차례로 증착하는 단계와, 게이트 전극 형성용 도전막 상에 제 2도전형 불순물을 도핑하여 제 2도전형 소오스/드레인 확산영역을 형성하는 단계를 포함한다.The disclosed method of manufacturing a semiconductor device includes the steps of forming a well by doping a semiconductor substrate with impurities of a first conductivity type, and etching a portion of the semiconductor substrate including the well to define a shallow trench defining an active region of the device. Forming a device, forming a device isolation film filling a shallow trench, exposing a side surface and a portion of an upper surface of the device isolation film, forming a conductive spacer on a side surface of the exposed device isolation film, and forming a conductive spacer. Forming a silicon nitride film so as to remain between the containing device isolation layers, doping a first conductive type impurity on the resultant to form a first conductive impurity diffusion region under the conductive spacer, and removing the remaining silicon nitride film Depositing a gate insulating film and a conductive film for forming a gate electrode on the resulting substrate; And doping the second conductive type impurity on the conductive film for forming the gate electrode to form the second conductive source / drain diffusion region.
Description
본 발명은 반도체장치의 제조 방법에 관한 것으로, 보다 상세하게는 셀 트랜지스터의 마진을 확보할 수 있는 트랜지스터 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a transistor forming method capable of securing a margin of a cell transistor.
도 1은 종래 기술에 따른 트랜지스터 형성 방법을 설명하기 위한 공정단면도이다.1 is a cross-sectional view illustrating a method of forming a transistor according to the prior art.
종래 기술에 따른 트랜지스터 형성 방법은, 도 1에 도시된 바와 같이, 먼저 반도체기판의 격리영역을 식각하여 샬로우 트렌치(104)를 형성하고 나서, 상기 샬로우 트렌치(104)를 매립시키는 소자 분리막(106)을 형성한다.In the transistor forming method according to the related art, as shown in FIG. 1, an isolation layer 104 is formed by first etching an isolation region of a semiconductor substrate, and then filling the shallow trench 104. 106).
이어, 상기 소자 분리막을 포함한 기판 전면에 게이트 절연막(117) 및 게이트 형성용 도전막(118)을 차례로 증착하고 나서, 상기 게이트 전극 형성용 도전막을 패터닝하여 게이트 전극(118)을 형성한다.Subsequently, the gate insulating film 117 and the gate forming conductive film 118 are sequentially deposited on the entire surface of the substrate including the device isolation layer, and then the gate electrode forming conductive film is patterned to form the gate electrode 118.
그 다음, 이온주입 공정을 진행하여 소오스/드레인 전극(미도시)을 각각 형성하여 트랜지스터 형성 공정을 완료한다.Next, an ion implantation process is performed to form source / drain electrodes (not shown), respectively, to complete the transistor forming process.
도 2는 종래 기술에 따른 문제점을 설명하기 위한 공정단면도이다.Figure 2 is a process cross-sectional view for explaining the problem according to the prior art.
그러나, 종래 기술에서는 샬로우 트렌치 형성 시, 도 2에 도시된 바와 같이, 샬로우 트렌치 가장자리 부분(A부분)이 움푹 패이는 모우트(moat) 현상이 발생되거나 디자인 룰 감소에 따른 INWE(Inverse Narrow Width Effect)로 인한 채널 형성 영역에 게이트의 전기장 영향이 중첩되어 전기장 증가를 야기시킨다.However, in the related art, as shown in FIG. 2, when forming the shallow trench, a moat phenomenon occurs in which the shallow trench edge portion (A portion) is pitted or an inverse narrow according to the reduction of the design rule. The effect of the electric field of the gate is superimposed on the channel forming region due to the width effect, causing an increase in the electric field.
이로 인하여 셀 트랜지스터의 경우 리플레쉬 특성이 저하되고 문턱 전압 저하를 유발시키고, 문턱 전압 보상을 위한 추가적인 이온 주입을 실시하나 이로 인한 전기장 증가 현상이 가속화되며, 르플래쉬 타임 특성을 감소시키는 문제점이 있었다.As a result, in the case of the cell transistor, the refresh characteristics are lowered, the threshold voltage is lowered, and additional ion implantation is performed to compensate for the threshold voltage. However, the increase in the electric field is accelerated and the reflash time characteristics are reduced.
이에 본 발명은 상기 종래의 문제점을 해결하기 위해 안출된 것으로, 셀 트랜지스터의 마진을 확보할 수 있는 트랜지스터 형성 방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for forming a transistor capable of securing a margin of a cell transistor.
도 1은 종래 기술에 따른 트랜지스터 형성 방법을 설명하기 위한 공정단면도.1 is a process cross-sectional view for explaining a transistor forming method according to the prior art.
도 2는 종래 기술에 따른 문제점을 설명하기 위한 공정단면도.Figure 2 is a process cross-sectional view for explaining the problem according to the prior art.
도 3a 내지 도 3f는 본 발명에 따른 트랜지스터 형성 방법을 설명하기 위한 공정단면도.3A to 3F are cross-sectional views illustrating a method of forming a transistor in accordance with the present invention.
상기 목적을 달성하기 위한 본 발명의 트랜지스터 형성 방법은 반도체기판에 제 1도전형의 불순물을 도핑하여 웰을 형성하는 단계와, 웰을 포함한 반도체기판의일부분을 식각하여 소자의 활성영역을 정의하는 샬로우 트렌치를 형성하는 단계와, 샬로우 트렌치를 매립시키는 소자격리막을 형성하는 단계와, 소자격리막의 측면 및 상면 일부를 노출시키는 단계와, 노출된 소자격리막의 측면에 도전 스페이서를 형성하는 단계와, 도전 스페이서를 포함한 소자격리막 사이에 잔류되도록 실리콘 질화막을 형성하는 단계와, 결과물 상에 제 1도전형의 불순물을 도핑하여 도전 스페이서 하부에 제 1도전형 불순물 확산영역을 형성하는 단계와, 잔류된 실리콘 질화막을 제거하는 단계와, 결과의 기판 상에 게이트 절연막 및 게이트 전극 형성용 도전막을 차례로 증착하는 단계와, 게이트 전극 형성용 도전막 상에 제 2도전형 불순물을 도핑하여 제 2도전형 소오스/드레인 확산영역을 형성하는 단계를 포함한 것을 특징으로 한다.In order to achieve the above object, a method of forming a transistor of the present invention includes forming a well by doping a semiconductor substrate with an impurity of a first conductivity type, and etching a portion of the semiconductor substrate including the well to define an active region of the device. Forming a low trench, forming a device isolation film to fill the shallow trench, exposing a side surface and a portion of the top surface of the device isolation film, forming a conductive spacer on the exposed device isolation film, Forming a silicon nitride film so as to remain between the device isolation films including the conductive spacers, doping the first conductive impurities on the resultant to form a first conductive impurity diffusion region under the conductive spacers, and remaining silicon Removing the nitride film followed by a gate insulating film and a conductive film for forming a gate electrode on the resulting substrate And depositing a second conductive source / drain diffusion region by doping the second conductive impurity onto the conductive film for forming a gate electrode.
이하, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 3a 내지 도 3f는 본 발명에 따른 트랜지스터 형성 방법을 설명하기 위한 공정단면도이다.3A to 3F are cross-sectional views illustrating a method of forming a transistor according to the present invention.
본 발명에 따른 트랜지스터 형성 방법은, 도 3a에 도시된 바와 같이, 먼저 반도체기판(200) 상에 이온주입 공정을 통해 제 1도전형의 웰(well)(202)을 형성한 후, 기판의 일부분을 식각하여 소자의 활성영역(미도시)을 정의하는 샬로우 트렌치(204)를 형성한다.In the method of forming a transistor according to the present invention, as shown in FIG. 3A, first, a well 202 of a first conductivity type is formed on the semiconductor substrate 200 through an ion implantation process, and then a portion of the substrate is formed. Is etched to form a shallow trench 204 that defines an active region (not shown) of the device.
이어서, 상기 샬로우 트렌치(204)를 포함한 기판 상에 화학기상증착법에 의해 실리콘 산화막을 증착한 후, 상기 실리콘 산화막을 에치백하여 소자격리막(206)을 형성한다. 그 다음, 기판을 일정 두께로 식각하여 상기 소자격리막(206)의 상면 및 측면의 일부를 노출시킨다. 이때, 상기 식각 공정에 의해 샬로우 트렌치(204)보다도 소자의 활성영역이 낮게 형성된다.Subsequently, after depositing a silicon oxide film on the substrate including the shallow trench 204 by chemical vapor deposition, the silicon oxide film is etched back to form a device isolation film 206. Subsequently, the substrate is etched to a predetermined thickness to expose a portion of the top and side surfaces of the device isolation film 206. At this time, the active region of the device is formed lower than the shallow trench 204 by the etching process.
이 후, 상기 소자격리막(206)을 포함한 기판 상에 다시 화학기상증착법에 의해 불순물이 도핑되지 않은 다결정실리콘층(210)을 형성한다.Thereafter, the polysilicon layer 210 which is not doped with impurities is formed on the substrate including the device isolation layer 206 by chemical vapor deposition.
이어서, 도 3b에 도시된 바와 같이, 상기 불순물이 도핑되지 않은 다결정실리콘층을 에치백 (etch back) 또는 화학적-기계적 연마(Chemical Mechnical Polisihing)하여 노출된 소자격리막(206) 측면에 도전 스페이서(211)를 형성한다.Subsequently, as shown in FIG. 3B, the conductive spacer 211 is exposed to the side of the isolation layer 206 exposed by etching back or chemical mechanical polishing with the polysilicon layer not doped with impurities. ).
그런 다음, 상기 도전 스페이서(211)를 포함한 기판 상에 화학기상증착법에 의해 실리콘 질화막(214)을 증착한다.Then, the silicon nitride film 214 is deposited on the substrate including the conductive spacer 211 by chemical vapor deposition.
이 후, 도 3c에 도시된 바와 같이, 상기 실리콘 질화막을 에치백 또는 화학적-기계적 연마하여 상기 도전 스페이서(211)를 포함한 소자격리막(206) 사이에 잔류되도록 한다.Thereafter, as illustrated in FIG. 3C, the silicon nitride film is etched back or chemically-mechanically polished to remain between the device isolation layers 206 including the conductive spacers 211.
이어서, 도 3d에 도시된 바와 같이, 상기 결과물 상에 웰(202)과 동일한 제 1도전형 불순물 도핑 공정을 실시하여 도전 스페이서(211) 하부 기판에 제 1도전형 불순물 확산영역(점선 처리된 부분)을 형성한다. 이때, 제 1도전형 불순물 도핑된 다결정 실리콘인 도전 스페이서(211)에 의해 활성영역에 제 1도전형 불순물 확산영역이 발생하게 되는데, 이 영역은 이 후의 공정을 거쳐서 게이트 전극을 형성한 후에 샬로우 트렌치에 너비(width)방향으로 국부적인 불순물 도핑을 증가시킨다.Subsequently, as shown in FIG. 3D, a first conductive impurity doping process similar to that of the wells 202 is performed on the resultant to form a first conductive impurity diffusion region (dotted portion) on the lower substrate of the conductive spacer 211. ). At this time, the first conductive impurity diffusion region is generated in the active region by the conductive spacer 211 which is the first conductive impurity doped polycrystalline silicon, which is formed after the gate electrode is formed through the following process. Increase local impurity doping in the trench in the width direction.
그 다음, 잔류된 실리콘 질화막을 제거한다.Then, the remaining silicon nitride film is removed.
이 후, 도 3e에 도시된 바와 같이, 상기 결과의 기판 상에 상면 및 측면의 일부가 노출된 소자격리막(206) 및 도전 스페이서(211)을 덮도록 화학기상증착법에 의해 실리콘 산화막(217)을 증착하고 나서, 상기 실리콘 산화막(217) 상에 게이트 전극 형성용 도전막(218)을 증착한다. 이때, 상기 게이트 전극 형성용 도전막(218)은, 도면에 도시되어 있지 않지만, 다결정 실리콘층, 텅스텐 실리사이드층 및 하드마스크인 실리콘 질화막으로 구성된다.After that, as shown in FIG. 3E, the silicon oxide film 217 is formed by chemical vapor deposition so as to cover the device isolation film 206 and the conductive spacer 211 where part of the top and side surfaces thereof are exposed on the resultant substrate. After the deposition, the conductive film 218 for forming a gate electrode is deposited on the silicon oxide film 217. At this time, the gate electrode forming conductive film 218 is composed of a polysilicon layer, a tungsten silicide layer, and a silicon nitride film, which is a hard mask, although not shown in the drawing.
이어서, 도 3f에 도시된 바와 같이, 상기 게이트 전극 형성용 도전막(218) 상에 제 2도전형 불순물 주입 공정(242)을 진행하여 제 2도전형 소오스/드레인 불순물영역(220)을 형성한다.Subsequently, as illustrated in FIG. 3F, a second conductive impurity implantation process 242 is performed on the gate electrode forming conductive film 218 to form a second conductive source / drain impurity region 220. .
이상에서 설명한 바와 같이, 본 발명에서는 샬로우 트렌치 가장자리 부분(트랜지스터의 너비방향)에 다결정실리콘 도전 스페이서의 도핑과 이로 인한 불순물 확산영역을 형성함으로써, INWE 또는 샬로우 트렌치의 모우트 현상으로 인한 전기장 중첩 효과를 방지할 수 있어 문턱 전압 저하로 인한 오프 리키지(off leakage) 감소 효과가 있다.As described above, in the present invention, the doping of the polysilicon conductive spacer and the resulting impurity diffusion region are formed at the edge of the shallow trench (the width direction of the transistor), thereby overlapping the electric field due to the muting phenomenon of the INWE or shallow trench. The effect can be prevented, thereby reducing off leakage due to a threshold voltage drop.
또한, 샬로우 트렌치 가장자리 부분에 다결정 실리콘 도전 스페이서에 불순물을 도핑함으로써, 트랜지스터의 턴 오프(turn off) 시(게이트 전극의 전압이 문턱 전압보다 작은 경우)에는 INWE 또는 샬로우 트렌치의 모우트 현상으로 인한 전기장 중첩 효과 및 문턱 전압 저하로 인한 오프 리키지 감소 효과가 있고, 턴 오프 시(게이트 전극의 전압이 문턱 전압보다 큰 경우) 트랜지스터 전기적너비(electrical width) 증가 효과가 있다.In addition, by doping impurities in the polycrystalline silicon conductive spacers at the shallow trench edges, the INWE or shallow trenches may become muted when the transistor is turned off (when the voltage of the gate electrode is less than the threshold voltage). Due to the electric field overlap effect due to the reduction of the threshold voltage due to the reduction of the threshold voltage, there is an effect of increasing the electrical width of the transistor (when the voltage of the gate electrode is greater than the threshold voltage).
그리고 주변영역의 트랜지스터의 경우에는 샬로우 트렌치 모우트로 인한 흄(hump) 방지 효과가 있다.In the case of the transistor in the peripheral region, there is an effect of preventing a hump due to the shallow trench Mouth.
기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다.In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.
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| KR960019611A (en) * | 1994-11-24 | 1996-06-17 | 문정환 | Semiconductor device manufacturing method |
| KR980012599A (en) * | 1996-07-29 | 1998-04-30 | 김광호 | Methods of forming transistors using salicide process technology |
| US5777370A (en) * | 1996-06-12 | 1998-07-07 | Advanced Micro Devices, Inc. | Trench isolation of field effect transistors |
| JP2000306989A (en) * | 1999-04-20 | 2000-11-02 | Sony Corp | Fabrication of semiconductor device |
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| KR960019611A (en) * | 1994-11-24 | 1996-06-17 | 문정환 | Semiconductor device manufacturing method |
| US5777370A (en) * | 1996-06-12 | 1998-07-07 | Advanced Micro Devices, Inc. | Trench isolation of field effect transistors |
| KR980012599A (en) * | 1996-07-29 | 1998-04-30 | 김광호 | Methods of forming transistors using salicide process technology |
| JP2000306989A (en) * | 1999-04-20 | 2000-11-02 | Sony Corp | Fabrication of semiconductor device |
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