JP3001588B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a method for isolating elements such as MOS transistors.

[Conventional technology]

2. Description of the Related Art In recent years, semiconductor integrated circuits have been steadily miniaturized and highly integrated. Therefore, in order to eliminate the insulation failure due to the parasitic channel and to reduce the parasitic capacitance of the wiring, a thick insulating film is formed in a so-called field region between the elements, and the elements are separated by the insulating film.

As one example of this, a so-called box (Bo) in which a groove is formed in a field region of a wafer and a silicon oxide film is buried in the groove by a CVD method to flatten the surface.
x) There is a method called the method.

In the box method, while isolation between elements is improved, stress is increased due to a difference in coefficient of thermal expansion from substrate silicon because a silicon oxide film is buried in a groove, and crystal defects are generated from a groove bottom and the like. There was a problem. This causes leakage current. In addition, when a MOSFET is formed in such an element isolation region, the corner of the groove is inevitably exposed, electric field concentration from the gate electrode occurs at the corner, the threshold of the MOSFET is reduced, and the sub-threshold is reduced. There is a problem that the characteristics have a hump.

In order to avoid such a problem, as shown in an example in FIG. 7, a method of suppressing a leak current due to the above-described crystal defect by using a low stress material such as polycrystalline silicon as a filling material is also proposed. Have been. This is because a polycrystalline silicon film 104 is buried in a groove V formed in a p-well region 102 formed on the surface of an n-type silicon substrate 101 via a silicon oxide film 103, and the surface of the polycrystalline silicon film 104 is oxidized. Oxide film 105 formed by
There has been proposed an element isolation method in which the element is covered with a. Here, 106 is a p-channel stopper layer. The gate insulating film 107 is formed in an element region surrounded by such an element isolation region.
Let us consider a case in which a gate electrode 108 is formed through the gate electrode and a source / drain region 109 made of an n + diffusion layer is formed to form a MOSFET.

According to this method, since most of the material filling the inside of the groove is polycrystalline silicon, stress due to a difference in thermal expansion coefficient is reduced. However, wedge-shaped oxidation progresses in the groove side view at the time of surface oxidation, and there is a problem that the leakage current increases due to the stress, and a problem still remains with the hump characteristic of the MOSFET due to the exposure of the corner K of the groove. I have. To make matters worse, since polycrystalline silicon is a conductor, between the pn junction formed on the groove side surface,
A gate control diode structure using this polycrystalline silicon as a gate electrode is formed, and a new junction leak current is generated.

(Problems to be Solved by the Invention) As described above, in the conventional device isolation technology, there are various problems such as a leak current due to a crystal defect, a hump characteristic of a MOSFET due to exposure of a groove corner, and a leak current due to a gate control diode structure. Was leaving.

In addition, it is necessary to increase the width of the silicon oxide film formed on the element forming region in consideration of the displacement at the time of patterning the silicon oxide film formed so as to cover the polycrystalline silicon film in the groove. It may be.

The present invention has been made in view of the above circumstances, and has as its object to perform highly reliable element isolation with a small element isolation and a small occupation area.

[Configuration of the invention]

(Means for Solving the Problems) In the first aspect of the present invention, in element isolation using a groove, an embedding material is buried in the groove, and the upper surface thereof is larger than the groove width and the edge thereof has a tapered insulating film. Is formed.

According to a second aspect of the present invention, in a semiconductor device having a plurality of element isolation regions having different widths, the width of the groove is constant with respect to all elements, and a cover of an insulating film provided on the upper surface of the groove according to the element isolation width. I try to determine the size of my body.

Further, in the method of the present invention, a convex portion made of the first film is formed on the surface of the semiconductor substrate, and a second film is formed on a side wall of the convex portion, and the groove is formed using the first and second films as a mask. (Trench) is formed, a third film having a coefficient of expansion substantially equal to that of the semiconductor substrate is buried in the groove, and then the second film is removed. A fourth film having a higher etching rate is deposited, and the fourth film is etched to form a V-shaped groove at a step of the fourth film formed on the region where the first film is present. After exposing the side wall of the first film, the first film is removed by etching to expose the substrate surface in the element formation region.

(Operation) According to the first configuration, since the lid of the insulating layer larger than the groove width is formed at the upper part of the groove, the groove corner is covered with this insulating layer and is not exposed, so that the MOSFET humps. It is also possible to prevent the influence of characteristics and the like. Further, since surface oxidation is not required, generation of defects due to wedge oxidation can be prevented.

Furthermore, because of the lid made of an insulating layer, a pn junction between the activation region and the substrate is formed at a distance from the groove side surface, so that even when polycrystalline silicon is used for the buried layer, The gate control diode structure using this polycrystalline silicon as a gate electrode is also avoided,
The accompanying junction leak current can be suppressed.

Further, according to the second configuration, even when it is necessary to form element isolation regions of various sizes, the groove width is constant for all the elements, and is arranged on the upper surface of the groove according to the element isolation width. Since it is only necessary to change the size of the lid of the insulating film to be provided, it is possible to form the groove with good controllability. Further, according to the current technology, the groove width at which the insulating film can be satisfactorily embedded is at most 1 μm. However, according to this structure, a groove of 1 μm or less is formed, and the width of the lid is adjusted to a desired size. Just do it.

By the way, in order to avoid the above-mentioned problem due to the exposure of the corner portion of the groove, for example, as shown in FIG. 6, a polycrystalline silicon film 303 is formed in a groove V formed on the surface of a silicon substrate 301 via a silicon oxide film 302. Buried in the silicon oxide film by CVD so as to cover the surface of the polycrystalline silicon film 303.
Consider the case where 304 is formed.

Here, the silicon oxide film 304 covering the upper portion of the trench is to be electrically separated from the polycrystalline silicon 303 buried in the trench and to prevent formation of a parasitic channel. , Not only the top of the groove but also the groove V
It is desirable to form it so as to extend slightly on the element formation region adjacent to the device. Since this silicon oxide film is processed in the mask alignment step, the extension widths S1, S extending over the element formation region adjacent to the groove V due to misalignment with the groove V
2 is likely to change. For this reason, in view of the margin, the width of the extension on the element isolation region needs to be generally about 0.4 μm, which may result in preventing high density.

Therefore, in the method of the present invention, an insulating film covering the element isolation groove is formed in a self-alignment manner with respect to the groove, so that the extension width over the element formation region is reduced as much as possible.

That is, according to the above method, the first film as a mask used at the time of forming the element isolation groove is used as it is without patterning the insulating film (fourth film) covering the element isolation groove without going through a photolithography step. Forming in a self-aligned manner by exposing the periphery of the first film by using an insulating film that increases the etching rate on the step around the first film and etching away the first film. Is done.

In other words, we pay attention to the result that the silicon oxide film and the like formed by the plasma CVD method and the like have a weak film quality on the step and the etching rate on the step is significantly faster than the etching rate on the flat part when etching. This is used to perform patterning in a self-aligned manner.

Further, a groove is formed in a state where the second film is formed on the side wall of the first film, and the second film is removed when the fourth film is deposited. Even if the width of the groove is slightly increased due to intrusion, the fourth film overlaps the element formation region by the thickness of the second film, so that the corner portion of the groove is prevented from being exposed.

Further, since a groove is formed using a mask to which the second film formed in the side wall leaving step is added, a groove having a width smaller than the limit of actual lithography can be formed.

Therefore, in addition to the effects of the first and second configurations, it is possible to prevent the extension of the insulating film to the element formation region from increasing in area, and to further remarkably reduce the area of the element isolation region. It can be measured, and higher integration can be achieved.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a view showing a semiconductor device formed by the method according to the first embodiment of the present invention, and FIGS. 2 (a) to 2 (d) are process charts for forming the element isolation region. It is.

In this semiconductor device, a trench V is formed in an element isolation region, and the trench V is filled with a polycrystalline silicon film 4 via a silicon oxide film 3 and has a width larger than the trench width so as to cover this surface. A feature is that a lid of the silicon oxide film 5 is formed. Here, the edge of the silicon oxide film is formed to have a tapered shape to facilitate processing such as a subsequent electrode forming step.

That is, in this semiconductor device, the groove V formed in the surface of the p-type well region 2 formed in the n-type silicon substrate 1 is formed.
An element isolation region formed by filling the inside with a polycrystalline silicon film 4 via a silicon oxide film 3 and forming a silicon oxide film 5 having a width larger than the groove width so as to surround a corner of the groove. A gate electrode 7 formed via a gate insulating film 6 in an element region surrounded by
Composed of n + diffusion layers as source / drain regions 8
A MOSFET is formed. Here, 9 is a p-type channel stopper.

Next, a process of forming the semiconductor device will be described.

First, as shown in FIG. 2 (a), after forming a p-well region 2 in an n-type silicon substrate 1, a silicon oxide film 31 having a thickness of about 2000.degree. A groove having a width of 0.2 μm is formed therein by using lithography and etching techniques, and etching is performed by reactive ion etching using the groove as a mask, and a depth is formed.
A 0.4 μm groove V is formed, and thereafter, boron ions (B +) are implanted into the bottom of the groove at 2 × 10 ¹³ cm ⁻² to form a p-type channel stopper layer 9 for preventing inversion.

Thereafter, as shown in FIG. 2 (b), the silicon oxide film 31 as a mask is removed, and a film thickness of about 3000 .ANG.
The polycrystalline silicon film 4 is deposited and etched by anisotropic etching so that the polycrystalline silicon film remains only in the groove.

Further, as shown in FIG. 2 (c), a silicon oxide film 5 having a thickness of about 2000 Å is deposited by a CVD method, a resist is further applied on the silicon oxide film 5, and a resist pattern R is formed by a usual photolithography method.

Thereafter, as shown in FIG. 2D, isotropic etching is performed using the resist pattern R as a mask.
Anisotropic etching is performed to pattern the silicon oxide film 5 serving as a lid having a tapered edge.

Then, the resist pattern is removed, and through a normal process, a gate insulating film, a gate electrode, an n-type diffusion layer as a source / drain region are formed, a MOSFET is formed, and a semiconductor as shown in FIG. 1 is formed. The device is completed.

In the semiconductor device thus formed, the upper portion of the groove V is covered with a lid made of the silicon oxide film 5. There is no exposure at the corners of the groove, and it is possible to obtain a specific good MOSFET without hump characteristics. Further, there is no occurrence of leakage due to surface oxidation.

Further, because of the lid 5, the pn junction between the activation region and the substrate is formed at a distance from the side surface of the trench, and thereby the gate control using the polysilicon 3 of the buried layer as the gate electrode is performed. The diode structure is also avoided, and the resulting junction leakage current can be suppressed.

In the above embodiment, non-doped polycrystalline silicon is used as the filling material, but a polycrystalline silicon film containing impurities may be used. In this case, electric field shield separation can be performed by applying a potential of 0 V to the polycrystalline silicon in the buried layer. Also,
As an embedding material, not only polycrystalline silicon but also BP
It is also possible to use an insulating film such as an SG film or a silicon nitride film.

Furthermore, in order to positively use the tapered portion of the edge of the lid 5, after the lid is formed, a selective epitaxial growth (SSG) of silicon is performed on the surface of the substrate in advance, so that the activation region is expanded, May be formed.

Furthermore, prior to forming the silicon oxide film as the lid, the surface of the polycrystalline silicon film in the groove V may be oxidized. This makes it possible to obtain an effect that the withstand voltage is further improved.

Embodiment 2 Next, a second embodiment of the present invention will be described. Third
FIGS. 4A to 4I are perspective views showing element isolation regions formed by the method of the embodiment of the present invention.
It is a process chart of the formation of the element isolation region.

This semiconductor device has a p-type impurity concentration of about 5 × 10 ¹⁶ cm ^−3.
The trench V formed on the surface of the mold silicon substrate 10 is filled with a polycrystalline silicon film 17 via a silicon oxide film 16 and formed in a self-aligned manner on the surface of the groove so as to surround the corner of the groove. A gate electrode 23 is formed in an element region surrounded by an element isolation region formed of a silicon oxide film 19, and source / drain regions 24 and 25 formed of an n + diffusion layer formed so as to be self-aligned with the gate electrode 23. Become MOSFET
Are formed.

Next, a process of forming the element isolation region will be described.

First, as shown in FIG. 4 (a), the impurity concentration is 5 × 10 ¹⁶
After a silicon oxide film 11 having a thickness of about 20 nm is formed on the surface of a (100) p-type silicon substrate 10 of about cm ^-3 by a thermal oxidation method, a silicon nitride film having a thickness of about 400 nm which is an oxidation resistant film is formed by a CVD method. The films 12 are sequentially deposited, and these are patterned by a normal photolithography method.

The silicon oxide film 11 and the silicon nitride film
After depositing a silicon oxide film 13 having a thickness of about 150 nm on the upper layer of the pattern 12 by a CVD method, the entire surface is etched by ordinary reactive ion etching, and the silicon oxide film 11 and the silicon nitride film 12 Only the silicon oxide film 13 is left.

Thereafter, the silicon substrate 10 is etched by a reactive ion etching method using the silicon nitride film 12 and the silicon oxide film 13 as a mask to form a groove V having a depth of about 0.5 μm.
Is formed, and a thermal oxide film 14 having a thickness of about 20 nm is formed on the inner wall of the groove.

Subsequently, as shown in FIG. 4 (b), boron ions or the like for preventing field inversion are applied to the bottom of the groove, for example, by 1 ×.
10 ¹³ cm ^-2 , ion implantation at about 100 KeV, p-type impurity layer 1
Form 5 At this time, in order to alleviate the stress, the etching may be performed so that the bottom of the groove is rounded, for example, with a radius of about r = 100 nm. After this, the oxide film on the inner wall of the groove
After removing 14, the inner wall of the groove is etched by about 50 to 100 ° with an etching solution containing, for example, an alkaline solution to remove damage during reactive ion etching. This step may be performed before ion implantation.

Then, as shown in FIG. 4C, a thermal oxide film 16 having a thickness of about 30 nm is formed on the inner wall of the groove, and a polycrystalline silicon film 17 having a thickness of about 500 nm is formed on the entire surface by the CVD method. .
Then, a resist or the like is further applied to flatten the surface and etch back to leave the polycrystalline silicon film 17 only in the groove.

Thereafter, as shown in FIG. 4D, the silicon oxide film 13 formed in the side wall leaving step is selectively etched away using an ammonium fluoride solution or the like.

Further, as shown in FIG.
Oxidized in a steam atmosphere at 850 ° C for 10 minutes to form a silicon oxide film 1
After forming 8, a silicon oxide film 19 having a thickness of 400 nm is formed by a plasma CVD method.

Subsequently, when the surface of the silicon oxide film 19 is etched using a buffered hydrofluoric acid solution such as an ammonium fluoride solution, the etching rate of the silicon oxide film on the side surface of the step becomes flat as shown in FIG. Since the etching rate is about 20 times the etching rate in the portion, a V-shaped groove 20 is formed in the silicon oxide film 19 along the periphery of the element formation region. This is considered to be because the silicon oxide film formed by the plasma CVD method has weak film quality on the step.

Thereafter, as shown in FIG. 4 (g), a fluid material film, for example, a resist film 21 is applied to the entire surface so that the surface is substantially flat. Here, when the resist film 21 is applied, the resist film is thin on the surface of the silicon oxide film 19 in the convex portion, is thickly applied in the concave portion, and the surface is almost flat.

Then, as shown in FIG. 4 (h), the entire surface is etched by a reactive ion etching method to completely remove the silicon oxide film 19 in the convex portion, thereby completely exposing the surface of the silicon nitride film 12. In this step, the etching rate of the resist film and the silicon oxide film 19 are selected by selecting the conditions of the reactive ion etching and the heat treatment time of the resist film.
So that the etching rate is almost the same.

Further, as shown in FIG.
After removing 21, silicon nitride film 12 is removed by CDE using an etching gas containing CF ₄ gas, and silicon oxide film 11 is further etched to expose the substrate surface.

Thus, the polycrystalline silicon film 17 is buried in the groove, and the silicon oxide film 19 is formed so as to cover the convex corner above the groove in a self-aligned manner.

Then, as shown in FIG. 4 (j), a gate oxide film 22 of about 15 nm is formed on the element formation region, and a phosphorus-doped polycrystalline silicon film 23 is deposited by a CVD method, and this is subjected to reactive ion etching. To form a gate electrode.

Finally, the source / drain regions 24, 2 made of an n-type diffusion layer are self-adjusted to the gate electrode 23 by an ordinary method.
5, and the semiconductor device as shown in FIG. 1 is formed.

Although not shown, CV is usually further applied to the entire substrate surface.
D oxide film etc. is deposited, and a contact hole is formed in this to reach the source / drain region and the gate electrode.
An aluminum wiring or the like is formed.

In this way, the silicon oxide film 19 covering the element isolation trench is not subjected to the photolithography process, and the silicon nitride film 12 as a mask used at the time of forming the element isolation trench is used as it is, and the periphery of the silicon nitride film 12 is formed. Etching is performed under conditions that increase the etching rate on the step, exposing the periphery of the silicon nitride film 12, and removing the silicon nitride film 12 by etching to prevent self-alignment. Therefore, the area of the element isolation region can be reduced without taking a margin for the above.

Further, a groove is formed with the silicon oxide film 13 formed on the side wall of the polycrystalline silicon 12, and the silicon oxide film 13 remaining on the side wall is removed when the silicon oxide film 19 is deposited. Even if the groove width is slightly widened due to etching in some cases, the silicon oxide film 19 overlaps the element formation area by the thickness of the silicon oxide film 13, preventing the corner of the groove from being exposed. Is done.

As described above, since the trench corners are covered with the silicon oxide 19 and are not exposed, the influence of the hump characteristic of the MOSFET can be prevented.

Furthermore, a pn junction between the active region and the substrate is formed at a distance from the side surface of the trench, so that a gate control diode structure using polycrystalline silicon of the buried layer as a gate electrode is also avoided. It is also possible to suppress the current.

The trench is a silicon oxide film formed in the sidewall leaving process.
Since a mask to which 13 is added is used, a groove having a width smaller than the limit of actual lithography can be formed. Therefore, it is possible to prevent the area of the silicon oxide film extending to the element formation region from increasing, and to further remarkably reduce the area of the element isolation region, thereby enabling higher integration. .

Also, when forming a wide element isolation region as shown by W in the drawing, a groove having the same width may be formed and formed so as to be surrounded by the groove. Process control is easy. At this time, the protrusions (the oxide film 11 and the silicon nitride film 14) in the wide element isolation region are
In FIG. 4 (b), it is to be removed by a process using ordinary photolithography and etching (region C).

In the above-described embodiment, as shown in FIG. 4 (g), at the time of etching back to expose the silicon nitride film 12 used as a mask when forming the trench, as shown in FIG.
In a case where a flat surface cannot be obtained due to the presence of a wide concave portion, a dummy resist pattern 21 _{1 is formed} on the wide concave region as shown in a modified example in FIG.
May be coated with a resist film 21 ₂ for planarization after forming the.

Further, in the above embodiment, after exposing the periphery of the silicon nitride film 12 used as a mask at the time of forming the groove, a resist film 21 is applied to flatten the surface, and etched back to expose the surface of the silicon nitride film 12. Although the silicon nitride film 12 is further etched, if the periphery of the silicon nitride film 12 is completely exposed in the step of FIG. 4 (f), the selectivity to the silicon oxide film is improved. If only the silicon nitride film is etched off under certain etching conditions, the silicon oxide film can be directly removed as shown in FIG. 4 (i) without going through the steps of FIGS. 4 (g) and 4 (h). The film 19 can be patterned.

Further, in the above embodiment, a polycrystalline silicon film is used as a material for filling the groove V. However, the present invention is not limited to the polycrystalline silicon film, but may be a silicon oxide film, a BPSG film, or a silicon nitride film formed by a CVD method. A multilayer film or the like formed by a combination of a silicon oxide film and a silicon oxide film may be used.

Further, as a gate electrode material, in addition to a polycrystalline silicon film, a so-called polycide structure using a high melting point metal such as molybdenum or tungsten, or a polycrystalline silicon and a silicide such as molybdenum silicide, tungsten silicide, or titanium silicide is used. You may.

In the above embodiment, the silicon nitride film 19 formed by the plasma CVD method is used as the insulating film formed on the step formed by the silicon nitride film 12 (fourth embodiment).
(See Fig. (E).) The film quality becomes weak on steps such as a silicon oxide film formed by a sputtering method or a silicon nitride film or a PSG film formed by a similar method, not limited to a silicon oxide film formed by a plasma CVD method. Such a film may be used, and may be replaced as needed.

In addition, the element isolation method of the present invention can be applied to DRAM cells, n-channel and p-channel single transistors,
It goes without saying that the present invention can be applied to various devices such as an E / D type inverter.

〔The invention's effect〕

As described above, according to the semiconductor device of the present invention, since the lid of the insulating layer having a width larger than the groove width is formed above the groove for element isolation to form the element isolation region, the groove corner portion is By being covered with an insulating layer and eliminating exposure,
Complete element isolation can be performed without affecting the characteristics of elements formed in the element region.

Further, according to the second aspect of the present invention, even when it is necessary to form element isolation regions of various sizes, the groove width is fixed for all the elements, and is arranged on the upper surface of the groove according to the element isolation width. Since the size of the lid of the insulating film to be provided is changed, it is possible to form the groove with good controllability.

According to the element isolation method of the present invention, the patterning of the insulating film covering the element isolation groove does not go through a photolithography step, and the first film as a mask used at the time of forming the element isolation groove is used as it is. A first film is formed in a self-aligned manner by exposing the periphery of the first film by using an insulating film having an increased etching rate on a step around the first film and etching away the first film. Therefore, the area of the element isolation region can be further remarkably reduced, and the high performance and high integration of the element isolation characteristics can be achieved.

[Brief description of the drawings]

FIG. 1 is a diagram showing a semiconductor device according to a first embodiment of the present invention;
2 (a) to 2 (d) are manufacturing process diagrams of the semiconductor device shown in FIG. 1, FIG. 3 is a diagram showing a semiconductor device of a second embodiment of the present invention, and FIG. 4A to 4J are manufacturing process diagrams of the semiconductor device shown in FIG. 3, FIG. 5 is a diagram showing a modification of the manufacturing process of the present invention, FIG. 6 is an explanatory diagram showing the present invention, FIG. 7 is a view showing an element isolation region formed by a conventional method. 301 ... silicon substrate, 302 ... silicon oxide film, 303 ...
... polycrystalline silicon film, 304 ... silicon oxide film, 1 ...
n-type silicon substrate, 2 ... p-type well region, 3 ... silicon oxide film, 4 ... polycrystalline silicon film, 5 ... silicon oxide film (lid), 6 ... gate insulating film, 7 ... gate Electrodes, 8: source / drain regions, 9: p-type channel stopper, 31: silicon oxide film, 10: silicon substrate, 11: silicon oxide film, 12: silicon nitride film, 13
…… Silicon oxide film, 14,16 …… Silicon oxide film, 15…
... p-type impurity layer, 17 ... polycrystalline silicon film, 18, 19 ...
Silicon oxide film, 20 groove, 21 resist film, 21 ₁ , 21
₂ ... resist pattern, 22 ... gate insulating film, 23 ...
Gate electrode, 24, 25 ... source / drain region, V ...
Groove, R: resist pattern.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-62-52957 (JP, A) JP-A-59-188141 (JP, A) JP-A-61-290753 (JP, A) JP-A-63-1987 122147 (JP, A) JP-A-59-188141 (JP, A) JP-A-2-237050 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/76 H01L 29 / 78

Claims (6)

(57) [Claims] 1. A semiconductor device having an element isolation region in which a buried material whose at least a surface in contact with an inner wall of the groove is an insulator is buried in a groove formed on the surface of the semiconductor substrate, The semiconductor device is provided on an upper surface of the semiconductor substrate, and has a substantially flat shape contact with the upper surface of the semiconductor substrate, and has a lid of an insulating film having a tapered edge, and the filling material is formed on an inner wall of the groove. An insulating film,
And a buried conductor layer formed inside the buried conductor layer.The buried conductor layer is connected to an external electrode so that element separation can be realized by an electrolytic effect of electrolysis applied through the external electrode. A semiconductor device characterized by being constituted. 2. A semiconductor device having a plurality of element isolation regions having different widths in which a filling material whose at least a surface in contact with an inner wall of the groove is an insulator is buried in a groove formed on the surface of the semiconductor substrate. Wherein the groove width is constant for all, and the size of the lid of the insulating film disposed on the upper surface of the groove is determined according to the element isolation width. Semiconductor device. 3. A semiconductor device having an element isolation region in which a filling material whose at least a surface in contact with an inner wall of the groove is an insulator is buried in a groove formed on the surface of the semiconductor substrate. A semiconductor device comprising an insulating film lid having a width larger than the groove width and having a taper only at an upper edge thereof. 4. The semiconductor device according to claim 1, wherein said burying material comprises an oxide film formed by oxidizing an inner wall of the groove, and a polycrystalline silicon film formed therein. 3) The semiconductor device according to the above. 5. The buried material includes an insulating film formed on an inner wall of the groove, and a buried conductor layer formed therein. The buried conductor layer is connected to an external electrode, 4. The semiconductor device according to claim 3, wherein element separation is realized by an electrolytic effect of electrolysis applied via an external electrode. 6. A first film forming step of forming a projection made of a first film on a surface of a semiconductor substrate, and a second film forming step of forming a second film on a side wall of the first film. A first groove forming step of forming a groove by etching the surface of the semiconductor substrate using the first and second films as a mask, and embedding a third groove in the groove so that the surface of the groove becomes flat A filling step; a second film removing step of removing the second film; and a fourth step of depositing an insulating fourth film having an etching rate on the step higher than that of the flat portion over the entire surface. 4
A second groove forming step of etching the fourth film to form a groove in the fourth film such that a side wall of the first film is exposed; and a first film forming step. And a device forming step of forming a desired device in the device region formed as described above.