JP2006100839A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a dynamic random access memory cell which can obtain high-speed operation by making the capacitance of a bit line small. <P>SOLUTION: A first semiconductor layer 11, a channel semiconductor layer 12, and a second conductive layer 13, which serves as the other source/drain region and further/serves as a storage node 26, too, are provided on a first impurity diffusion layer 24, which serves as one of the source/drain regions and further becomes a bit line, too. A capacitor insulating layer 13 is made be to interposed on the second conductive layer 21. A cell plate 22 is provided on the storage node 26, with the capacitor insulating layer 13 between. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention generally relates to semiconductor devices, and more particularly to a method of manufacturing a semiconductor device using a vertical surround gate MOSFET (hereinafter referred to as VΦT). The present invention further relates to an improvement of VΦT.

FIG. 114 is a diagram showing a trend of cell size of a dynamic random access memory (DRAM). FIG. 114 also shows design rules for each generation. A conventional DRAM cell includes four components: a bit line (BL), a word line (WL), a bit line contact (BK), and a storage node contact (SK). Therefore, if the cell size is expressed using F (feature size) of the following equation, the cell size is 8F ² .

F (feature size) = r + α
In the equation, F represents a gate width, r represents a minimum line width, and α represents a process margin.

  In FIG. 114, the design rule (minimum line width) is simply F, and 8F2 and 4F2 are superimposed and plotted (white circles and black circles). As is clear from this, it is the limit to make a 256M DRAM in an 8F @ 2 cell. On the other hand, if the cell size is 4F2, it is understood that a G-bit generation DRAM can be realized by following the conventional reduction rule.

A 4F ² cell can be obtained, for example, by providing a vertical transistor at the intersection of BL and WL. From the background as described above, various vertical transistors have been proposed.

  FIG. 115 is a cross-sectional view of a first conventional example of a vertical surround gate transistor disclosed in Japanese Patent Laid-Open No. 5-160408. Referring to FIG. 115, gate 3 is provided around silicon pillar 5 serving as a channel with gate insulating film 4 interposed. A source 6 a and a drain 6 b are connected to the silicon pillar 5.

  The biggest problem when this transistor is applied to a DRAM is the formation of the gate electrode 3 serving as a word line.

FIG. 116 is a cross-sectional view of the semiconductor device, showing the method for manufacturing the surround gate transistor shown in FIG. A gate insulating film 4 is formed so as to cover the silicon pillar 5. Thereafter, polysilicon (3) is deposited so as to cover the silicon pillars 5 with the gate insulating film 4 interposed therebetween. The gate electrode 3 is formed on the sidewall of the silicon pillar 5 by anisotropically etching the polysilicon (3). In this method, the gate length l is determined by the anisotropic etching rate of polysilicon (3). Therefore, the fluctuation v of the gate length l becomes very large. As a result, this method has a problem that it is very difficult to stably obtain 4F ² cells.

  117 and 118 are cross-sectional views in each step of the method of manufacturing a vertical surround gate transistor disclosed in Japanese Patent Laid-Open No. 4-282865.

Referring to FIG. 117, on the bit line 26, an SiO ₂ layer 2a, a polysilicon 3 as a word line, and an SiO ₂ layer 2b are sequentially provided. A contact hole 8 is provided so as to penetrate the SiO ₂ layer 2b, the polysilicon 3, and the SiO ₂ layer 2a. A gate insulating film 4 is formed on the side wall surface of the contact hole 8.

  117 and 118, polysilicon 5 is formed to cover the side wall of contact hole 8. The polysilicon 5 is divided into a source 6a, a channel 7, and a drain 6b. The transistor configured as described above has the following problems. That is, referring to FIG. 117, when the gate insulating film 4 is formed, it is easy to be subjected to the etching amount variation v, and sometimes the corner 3c at the upper end of the gate electrode is exposed, and as a result, the gate corner 3c and the drain 6b are exposed. There was a problem that a leak occurred between.

Further, there are the following problems regarding the transistor operation.
The channel polysilicon is turned off between the source and the drain by depleting the channel polysilicon by making the gate polysilicon and the channel polysilicon have opposite conductivity types and utilizing the difference in the work function. The film thickness must be smaller than the maximum depletion layer width determined from the impurity concentration in the channel polysilicon.

On the other hand, if the source / drain resistance is high, a sufficient ON current cannot be obtained. Therefore, it is necessary to increase the impurity in the channel polysilicon to lower the resistance. In a normal TFT, the amount of source / drain impurities is at most 10 ²⁰ / cm ³ . However, when an impurity of 10 ²⁰ / cm ² is introduced, the maximum depletion layer width is about 40 mm. Therefore, it can be seen that it is almost impossible to stably manufacture the transistor without sacrificing characteristics due to the restriction that the film thickness of the channel polysilicon must be less than this.
Japanese Patent Laid-Open No. 5-160408 JP-A-4-282865

  In order to solve the above-mentioned problems, the applicants have proposed a vertical phi-shape transistor (VΦT) as shown in FIG. 119 (Japanese Patent Application No. 5-345126).

  FIG. 119 is a perspective view showing an extracted main part of VΦT. 120 is a cross-sectional view of VΦT.

  Referring to these drawings, the MOSFET includes a substrate 1. A source region 6 a is provided in the main surface of the substrate 1. A first interlayer insulating film 2 a is provided on the substrate 1. A gate electrode 3 having an upper surface substantially parallel to the surface of the substrate is provided on the first interlayer insulating film 2a. A second interlayer insulating film 2b is provided on first interlayer insulating film 2a so as to cover gate electrode 3. A contact hole 19 for exposing a part of the surface of the source region 6a is provided so as to penetrate the first interlayer insulating film 2a, the gate electrode 3 and the second interlayer insulating film 2b. The side wall surface of the contact hole 19 is covered with the gate insulating film 4. A P-type first semiconductor layer 20 is provided in the contact hole 19 from the surface of the source region 6 a to the height of the lower surface of the gate electrode 3 so as to be in contact with the surface 9 of the source region 6 a. In the contact hole 19, the channel semiconductor layer 7 is provided from the surface of the first semiconductor layer 20 to the height of the upper surface of the gate electrode 3 so as to be in contact with the surface of the first semiconductor layer 20. A P-type second semiconductor layer 5 that becomes the drain region 6 b is provided on the channel semiconductor layer 7 so as to be in contact with the surface of the channel semiconductor layer 7.

  A third interlayer insulating film 2c is provided on the substrate so as to cover drain region 6b. A connection hole 11a for exposing a part of the surface of the drain region 6b is provided in the third interlayer insulating film 2c. The aluminum electrode 10a is connected to the drain region 6b through the connection hole 11a.

  119 and 120 solves the problems of the prior art shown in FIGS. 115 and 117, but there is a problem that there is a limit in reducing the capacity of the bit line.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor device using VΦT, which is improved so as to reduce the capacitance of a bit line and withstand high-speed operation.

  The method of manufacturing a semiconductor device according to the present invention relates to a method of manufacturing a semiconductor device in which information is stored in a capacitor formed by a storage node, a capacitor insulating film, and a cell plate electrode provided at an intersection of a bit line and a word line by a gate transistor. . A substrate on which a dielectric and a semiconductor layer are sequentially formed is prepared. A first conductive layer containing a first conductivity type impurity which becomes one of the source / drain regions and also serves as the bit line is formed in the surface of the semiconductor layer. A first interlayer insulating film is formed on the substrate. A gate electrode having an upper surface and a lower surface, which also serves as the word line, is formed on the first interlayer insulating film. A second interlayer insulating film is formed on the substrate so as to cover the gate electrode. A contact hole that penetrates through the first interlayer insulating film, the gate electrode, and the second interlayer insulating film and reaches the surface of the first conductive layer is formed. A side wall surface of the contact hole is covered with a gate insulating film. A second semiconductor layer is formed on the substrate so as to be in contact with the surface of the first conductive layer and to be embedded in the contact hole. A first conductivity type impurity is implanted into the surface of the second semiconductor layer. The impurity implanted into the surface of the second semiconductor layer is diffused into the second semiconductor layer, and from the first conductive layer to the second semiconductor layer, in the first conductive layer. In the second semiconductor layer, the other region of the source / drain region and also the storage node, the other of the source / drain region and the source are diffused. / A channel region sandwiched between one of the drain regions is formed. A capacitor insulating film is formed on the other of the source / drain regions. A cell plate is formed on the storage node with the capacitor insulating film interposed.

  According to the method for manufacturing a semiconductor device according to the present invention, since the semiconductor layer formed on the dielectric is used for the bit line, the capacity of the bit line can be reduced.

Example 1
FIG. 1 is a perspective view of a surround gate transistor (hereinafter, referred to as a vertical Φ-shape transistor, abbreviated as VΦT) according to the first embodiment, and FIG. FIG. 3 is a cross-sectional view taken along line II, and FIG. 3 is a layout diagram of a DRAM cell array using VΦT. In the DRAM according to the first embodiment, referring to these drawings, a gate transistor is connected to a capacitor formed of a storage node 26, a capacitor insulating film 21, and a cell plate electrode 22 provided at an intersection of a bit line 24 and a word line 25. To store information.

An embedded SiO ₂ layer (dielectric layer) 201 is provided on the substrate (Si) 1. A first conductivity type impurity is implanted on the buried SiO ₂ layer 201 to provide a first impurity diffusion layer 24 of the first conductivity type that becomes one of the source / drain regions and also serves as a bit line. Yes. A first interlayer insulating film 8 is provided on the buried SiO ₂ layer 201 so as to cover the first impurity diffusion layer 24. On the first interlayer insulating film 8, a gate electrode 3 having an upper surface and a lower surface, which also serves as a word line, is provided. A second interlayer insulating film 9 is provided on the first interlayer insulating film 8 so as to cover the gate electrode 3. A contact hole 10 for exposing a part of the surface of the first impurity diffusion layer 24 is provided so as to penetrate the first interlayer insulating film 8, the gate electrode 3, and the second interlayer insulating film 9. . The gate insulating film 4 covers the side wall surface of the contact hole 10.

  In the contact hole 10, the first conductivity is substantially from the surface of the first impurity diffusion layer 24 to the height of the lower surface of the gate electrode 3 so as to be in contact with the surface of the first impurity diffusion layer 24. A first semiconductor layer 11 of a mold is formed. In the contact hole 10, the channel semiconductor layer 12 extends from the surface of the first semiconductor layer 11 to substantially the height of the upper surface of the gate electrode 3 so as to be in contact with the surface of the first semiconductor layer 11. Is formed. A second conductive layer 13 of the first conductivity type that is the other of the source / drain regions and also serves as the storage node 26 is provided on the channel semiconductor layer 12 so as to be in contact with the surface of the channel semiconductor layer 12. ing. A capacitor insulating film 21 is provided on the second interlayer insulating film so as to cover the surface of the second conductive layer 13. A cell plate electrode 22 is provided on the second interlayer insulating film 9 so as to cover the second conductive layer 13 which is also the storage node 26 with the capacitor insulating film 21 interposed therebetween.

  Next, advantages of the DRAM according to this embodiment will be described. First, since VΦT is used, the occupation area can be reduced. Further, since the Si layer (SOI) or the poly-Si layer (poly-SOI) is used for the bit line (24), the bit line (24) is formed on the thick insulating film (201). As a result, the capacity of the bit line can be reduced. As a result, it is possible to obtain a DRAM that operates at high speed.

  Further, when SOI is used, there is an advantage that the channel semiconductor layer 12 can be formed by epitaxial growth.

In addition, since the bit line capacity is small, the capacity of the storage node can be reduced. That is, the sensitivity of the sense amplifier is determined to be a constant value. Accordingly, if the value of C _S (storage node capacity) / C _B (bit line capacity) is constant, information can be read. Therefore, if C _B is reduced, C _S can also be reduced.

Further, since the bit line capacitance is small, an open bit line system as shown in the equivalent circuit diagram of FIG. 16 is possible, and a 4F ₂ cell can be easily obtained.

  Further, when a normal silicon substrate is used, it is necessary to form a well in order to separate the P-channel and the N-channel. However, by using an SOI or poly-SOI structure, it is not necessary to form a well. In turn, the process for manufacturing is simplified.

  Further, when a normal silicon substrate is used, it is necessary to separate these with a LOCOS oxide film in order to separate adjacent transistors. In this embodiment, referring to FIG. Forming it is as it is, separating adjacent transistors. Therefore, in this respect, the manufacturing process is simplified.

  In addition, no leak current occurs between the bit line 24 and the adjacent bit line 24. The fact that no leakage current occurs between the bit lines means that the time interval for refreshing (rewriting) can be lengthened.

  In addition, because of the SOI structure, the DRAM is more resistant to soft errors than when a normal Si substrate is used.

The advantages of using the VΦT structure for the transistor are as follows.
Referring to FIG. 2, the channel can be depleted by reducing the radius of channel semiconductor layer 12. If the entire channel can be depleted, subthreshold current (leakage current in a weak inversion state) can be suppressed, and circuit characteristics can be improved. In addition, the subthreshold coefficient S is a minimum value (60 mV / dec).

  Further, since an electric field is applied from the periphery of the channel semiconductor layer 12, there is an effect that punch-through hardly occurs.

  In addition, since punch-through is difficult to occur, there is an effect that it is strong against disturb refresh. Further, since there is no substrate bias effect, high speed operation is possible. Since the channel width can be widened, it is possible to increase the current that flows.

  The channel semiconductor layer 12 can be single-crystallized by an epitaxial growth method. Since a method of forming a word line and opening a contact hole in the word line is adopted, the formation of the word line is easy. Connection between the transistor and the bit line and between the transistor and the capacitor is easy. Since the film thickness of the word line becomes the gate length, the gate length can be easily controlled. Since the length of the source offset is determined by the thickness of the first interlayer insulating film 8 and the length of the drain offset is determined by the thickness of the second insulating film 9, these lengths can be easily controlled. Can do.

  Source / drain impurities can be implanted by a simple ion implantation process. Similarly, channel ion implantation is easy. Since the gate insulating film is formed by oxidation, the gate insulating film is not thinned at the edge of the gate. As a result, no leakage current occurs at the edge of the gate.

  Next, a method for manufacturing a DRAM using VΦT shown in FIG. 2 will be described. The manufacturing process described below will be described with reference to a cross-sectional view taken along line AA in FIG.

Referring to FIG. 4, SOI substrate 40 in which buried SiO ₂ layer 201 is formed on substrate (Si) 1 and SOI layer (Silicon On Insulator) 202 is formed on buried SiO ₂ layer 201. Prepare.

  The SOI substrate 90 is formed by a SIMOX (Separation by IMplanted Oxgen) method, a ZMR (Zone Melting Recrystallization) method, a laser annealing method, a bonding method, or the like. Further, instead of the SOI substrate, a substrate separated by another dielectric such as SOS (Silicon On Sapphire) can be used. Further, a poly-SOI substrate may be used instead of the SOI substrate.

The thickness of the buried SiO ₂ layer 201 is 5000 mm, and the thickness of the SOI layer 202 is 2000 mm. Since the SOI layer 202 becomes a bit line, as shown in FIG. 4, the impurity 91 is implanted to reduce its resistance. For example, when VΦT is a P-channel type, a P-type impurity is implanted into the SOI layer 202.

  Referring to FIG. 5, 1000 nm of SiN layer 14 is deposited on SOI layer 202. As will be described later, the SiN layer 14 is for preventing the bottom of the contact hole from being oxidized when the gate insulating film of VΦT is formed.

Referring to FIG. 6, SOI layer 202 is patterned into the shape of bit line 24.
The impurity implantation step shown in FIG. 4, the SiN layer deposition step shown in FIG. 5, and the bit line patterning step shown in FIG. 6 may be performed in the following order.

(1) Implantation → SiN → Pattern (2) Implantation → Pattern → SiN
(3) SiN → implantation → patterning (4) SiN → patterning → implantation (5) Patterning → implantation → SiN
(6) Patterning → SiN → implantation Of the above-described steps, the steps shown in (2), (5), and (6) are performed, and the structure shown in FIG. 7 is obtained, unlike the structure shown in FIG. . In the case of the structure shown in FIG. 7, since the SiN layer 14 having a dielectric constant higher than that of SiO ₂ is formed between the bit lines 24, the capacitance between the bit lines and the bit lines increases. Therefore, the thickness of the SiN layer 14 needs to be reduced to about 500 mm.

Referring to FIGS. 6 and 8, 1000 μm of first interlayer insulating film 8 is deposited on buried SiO ₂ layer 201 so as to cover bit line 24. On the first interlayer insulating film 8, 3000 ポ リ of polysilicon is deposited and patterned to form the word line 25. In order to reduce the resistance, the polysilicon into which the impurity is implanted is patterned to form the word line 25. Doped polysilicon may be used as the polysilicon into which the impurity is implanted. Further, impurities may be implanted into non-doped polysilicon.

  9 is a cross-sectional view of the semiconductor device taken along the bit line direction (that is, a cross-sectional view along the line BB in FIG. 3) at the same stage as FIG.

  Referring to FIGS. 8 and 9, the film thickness of the word line 25 becomes the gate length of VΦT. Since control of the film thickness of the word line 25 is easy, the controllability of the gate length is very good.

  Referring to FIG. 10, second interlayer insulating film 9 is formed on first interlayer insulating film 8 so as to cover word line 25.

  Thereafter, a contact hole 10 penetrating the second interlayer insulating film 9, the word line 25, and the first interlayer insulating film 8 is formed at the intersection of the word line 25 and the bit line 24.

  Referring to FIG. 11, the side wall of word line 25 exposed in contact hole 10 is oxidized to form gate insulating film 4 of VΦT. Since the gate insulating film 4 is formed by the oxidation method, the thickness of the gate insulating film 4 is not reduced at the upper end of the gate electrode (25).

  Referring to FIGS. 11 and 12, the SiN layer 14 at the bottom of the contact hole 10 is removed by using hot phosphoric acid or the like, and the surface 24a of the bit line 24 is exposed.

  Referring to FIG. 13, amorphous silicon 15 is embedded in contact hole 10. Amorphous silicon 15 is epitaxially grown from the surface of bit line 24. Single crystal silicon 92 obtained by this epitaxial growth becomes a channel of VΦT. Since the surface 24a of the bit line 24 also serves as a contact of the bit line, the connection between the transistor and the bit line 24 becomes very simple.

  After the epitaxial growth is completed, ion implantation for forming the drain and channel of VΦT is performed. Thereafter, the implanted ions are diffused by heat treatment during the process, and the source 6a and the drain 6b are formed as shown in FIG. In addition, since the impurities of the source 6a, the drain 6b, and the channel 12 are introduced by the implantation method, the respective impurity concentrations can be easily controlled. Further, by controlling the film thicknesses of the first interlayer insulating film 8 and the second interlayer insulating film 9, the lengths of the offset portions 204a and 204b can be easily controlled.

  Referring to FIG. 15, the storage node 26 is generated by patterning the drain portion of VΦT. A capacitor insulating film 21 is formed on second interlayer insulating film 9 so as to cover storage node 26. Cell plate electrode 22 is formed on second interlayer insulating film 9 so as to cover storage node 26 with capacitor insulating film 21 interposed. As a result, a DRAM cell using VΦT is completed.

Since the drain portion 6b of VΦT is also the storage node 26, the connection between the transistor and the capacitor is very easy. Thus, a 4F ² DRAM cell is obtained.

  Example 2-6 described next relates to a method for reducing the resistance of a word line. Embodiments 7 to 12 relate to a method of reducing the resistance of the bit line and thereby operating the VΦT-DRAM at high speed.

  In Embodiment 1, since the word line is formed of doped polysilicon and the bit line is formed of an SOI layer, when a plurality of VΦT are connected, the resistance of the word line and the bit line becomes high. Further, as apparent from FIG. 3, the word line 25 becomes thinner at the portion where VΦT exists, and therefore the resistance is further increased. When the resistance of the word line and the bit line is high, the operation speed of the DRAM becomes slow. Example 2-12 was made to solve these problems.

Example 2
FIG. 17 is a cross-sectional view of a main part of a DRAM cell using VΦT according to the second embodiment. The DRAM cell according to the second embodiment is substantially the same as the DRAM cell shown in FIG. 2 except for the following points. Therefore, illustration of the same or corresponding parts as those of the DRAM cell shown in FIG. 2 is omitted. The same parts as those of the DRAM cell shown in FIG. 2 are denoted by the same reference numerals, and description thereof will not be repeated.

  In the DRAM cell shown in FIG. 17, the word line 25 is formed in a two-layer structure of polysilicon 16 and silicide 17 formed on the polysilicon 16. By adopting a two-layer structure of the polysilicon 16 and the silicide 17, the resistance of the word line 25 can be lowered, and as a result, the DRAM can be operated at high speed.

  Examples of the silicide material include tungsten silicide, titanium silicide, cobalt silicide, platinum silicide, molybdenum silicide, and the like.

Example 3
FIG. 18 is a cross-sectional view of a main part of a DRAM cell according to the third embodiment. The DRAM cell according to this embodiment is different from the DRAM cell shown in FIG. 17 in that a silicide 17 is formed under the polysilicon 16. Similar to the second embodiment, the resistance of the word line 25 can be lowered by forming the word line 25 in a two-layer structure of polysilicon and silicide.

Example 4
FIG. 19 is a cross-sectional view of a main part of a DRAM cell according to the fourth embodiment. In this embodiment, silicide 17 is provided above and below the polysilicon 16. With this configuration, the resistance of the word line 25 can be further reduced.

In the case of an n-channel transistor, a gate made of metal or silicide has a higher threshold voltage _Vth than a gate made of polysilicon because of work function. By making the word line 25 have a laminated structure of the silicide 17 and the polysilicon 16, the threshold voltage _{Vth of} VΦT can be locally changed. For example, as shown in FIG. 17, when the silicide 17 is disposed on the drain side, the channel portion 7 surrounded by the silicide 17 has a higher threshold voltage V _th than the channel portion 7 surrounded by the polysilicon 25. So it is hard to flip. Therefore, even if the drain voltage increases, there is an advantage that punch-through is unlikely to occur between the source 6a and the drain 6b.

Conversely, in the case of the p-channel, the channel portion 7 surrounded by the silicide 17 is weak against punch-through because the threshold voltage _Vth is lowered. Therefore, as shown in FIG. 20, punch-through can be prevented by providing the region 18 in which the amount of n-type impurities is slightly increased from the amount of impurities in the n − channel region 93. Further, as shown in FIG. 21, even if the word line 25 is formed so that the silicide 17 is sandwiched between the polysilicon 16, the resistance of the word line can be lowered in the p-channel 7 and punch-through is prevented. An effect is also obtained.

Example 5
FIG. 22 is a perspective view of the main part of the DRAM cell array according to the fifth embodiment, which corresponds to the stage shown in FIGS. In FIG. 22, members other than the word line 25 and the bit line 24 are omitted to simplify the drawing. In this embodiment, the silicide 17 is formed not only on the upper surface of the polysilicon 16 but also on the side surface. That is, since the three surfaces of the word line 25 are covered with the silicide 17, the resistance of the word line 25 can be further reduced.

Next, a method for manufacturing the apparatus shown in FIG. 22 will be described.
Referring to FIG. 23, word line 25 is formed on first interlayer insulating film 8.

  Referring to FIG. 24, the surface of word line 25 is covered with titanium film 19 having a thickness of 200 mm by sputtering.

Lamp annealing is performed at 600 to 700 ° C. in an N ₂ atmosphere for 30 seconds. As a result, referring to FIG. 25, a titanium silicide film 19a, which is a compound of titanium and silicon, is formed only at the portion where titanium and silicon are in contact. Referring to FIGS. 25 and 26, unreacted titanium film 19 is removed.

  In this embodiment, the case of titanium is exemplified, but cobalt, platinum, nickel, or the like may be used. Thus, the method of forming silicide only in the exposed part of silicon is called salicide.

  FIG. 27 is a cross-sectional view when a contact hole is formed in the word line 25 covered with the titanium silicide film 19a to form VΦT. In this case, the margin M between the word line and the contact hole of VΦT is given by the following equation.

M = superposition margin of photoengraving + silicide film thickness (t ₁ ) + film thickness of oxidized portion (t ₂ )
In consideration of this margin M, it is necessary to form a contact hole in the word line 25.

Example 6
The present embodiment relates to a method of forming silicide only on the side wall of the word line.

Referring to FIG. 28, SiO ₂ layer 20 is formed on word line 25. Referring to FIG. 29, silicide film 17 is formed on the side wall of word line 25. Since the silicide film 17 is formed on the side walls on both sides of the word line 25, the resistance of the word line 35 can be lowered.

  Further, when the contact hole of VΦT is formed, there is no silicide film on the upper surface of the word line 25, so that it is not necessary to perform etching for penetrating the silicide film, and the process stability is improved. .

Example 7
Embodiments 7-12 relate to lowering the resistance of the bit line, and thus to increase the speed of the VΦT-DRAM.

  FIG. 30 is a cross-sectional view in which silicide 31 is formed on SOI layer 30 (BL), SiN film 32 is formed in order, and these are patterned into the shape of bit lines. As described in the first embodiment, any process may be performed for implanting impurities into the SOI layer 30.

  Further, when the SOI layer 30 and the silicide 31 are first patterned and then the SiN film 32 is deposited, the device having a cross-sectional view as shown in FIG. 31 is obtained. 30 and 31 correspond to FIGS. 6 and 7 of the first embodiment, respectively.

  Thereafter, through a process similar to that shown in FIGS. 8 to 14, a VΦT-DRAM having a low bit line resistance and capable of high-speed operation is obtained.

  In this embodiment, referring to FIG. 32, contact hole 10 of VΦT is formed, gate insulating film 4 is formed by oxidation, and then SiN provided to prevent the bit line from being oxidized. When the film is removed, the device has a cross-sectional structure as shown in the figure. At this time, since the upper surface of the SOI layer 30 is covered with the silicide 31, even if amorphous silicon is buried in the contact hole 10 and this is solid-phase grown, the channel of VΦT is single. It does not become a crystal. Example 8 described below is an improvement of this.

Example 8
Referring to FIGS. 32 and 33, silicide 31 at the bottom of contact hole 10 of VΦT is etched. When the silicide 31 is etched, the surface 30a of the SOI layer 30 is exposed, so that the channel of VΦT can be single-crystallized by epitaxial growth.

Example 9
This embodiment relates to lowering the resistance of the bit line by providing silicide under the bit line.

Referring to FIG. 34, silicide 17 is formed on SiO ₂ layer 20. Polysilicon 16 serving as a bit line is formed on the silicide 17. In this way, the resistance of the bit line can be lowered. However, since the bit line is polysilicon, when VΦT is formed on the polysilicon 16, the channel of VΦT cannot be formed into a single crystal by epitaxial growth.

  In such a case, it is possible to form a bit line in which single crystal silicon is provided over silicide by a bonding method.

That is, referring to FIG. 35, second silicon substrate 34 is bonded to first silicon substrate 33 on which silicide 17 and SiO ₂ layer 20 are formed. The pasting is performed by causing both to adhere by performing a high-temperature heat treatment. Since the second silicon substrate 34 is merely a support substrate, the material thereof is not limited.

  Referring to FIGS. 35 and 36, the first silicon substrate 33 is polished by a chemical mechanical polishing method (CMP) with the upper side and the lower side turned upside down to form a thin film. Thereby, a bit line layer (33) having a single crystal silicon layer (SOI layer) on the silicide 17 can be formed.

  Thereafter, through the same process as in the first embodiment, a VΦT-DRAM having a single crystal channel can be manufactured and the resistance of the bit line can be lowered.

Example 10
This embodiment relates to further reducing the resistance of the bit line. Referring to FIGS. 36 and 37, if silicide 17 is further formed on single crystal silicon layer 30, a bit line having further reduced resistance and having silicide 17 above and below single crystal silicon layer 30 is formed. Is possible. 35, if polysilicon 94 is sandwiched between the silicide 17 and the SiO ₂ layer 20, as shown in FIG. 38, the polysilicon 30 and the silicide 17 are placed under the silicide 17 as shown in FIG. A bit line having the single crystal silicon layer 33 can be obtained. Even with such a structure, the resistance of the bit line can be lowered.

Example 11
This embodiment also relates to lowering the resistance of the bit line.

  Referring to FIG. 39, after forming SOI layer 30 to be a bit line by patterning, it is salicided. Thus, the upper surface and the left and right side surfaces of the bit line (30) are covered with the silicide 17. Since the three surfaces of the bit line (30) can be covered with the silicide 17, the resistance of the bit line can be further reduced.

  Further, by combining the bonding methods shown in Embodiment 9, it is possible to cover the upper, lower, left, and right surfaces of the bit line with silicide.

Example 12
This embodiment also relates to lowering the resistance of the bit line. Referring to FIG. 40, a film 35 for preventing silicidation is provided on the SOI layer 30 which is a bit line. By providing the film 35 for preventing silicidation on the SOI layer 30, the silicide 17 can be formed only on the side surface of the SOI layer 30 which is a bit line. In this case, the resistance of the bit line is higher than that shown in FIG. 39, but the resistance of the bit line is sufficiently low because both sides of the bit line are silicided.

  The film 35 for preventing silicidation may be an oxide film, but may be a nitride film provided on the SOI layer as used in the first embodiment. This eliminates the need for forming a hole in the silicide as in the eighth embodiment. As a result, a VΦT-DRAM having a low bit line resistance can be obtained simply by adding a silicidation step to the first embodiment.

The following Examples 13 to 16 relate to reducing the capacity of the bit line.
Example 13
The thirteenth embodiment relates to increasing the speed of the VΦT-DRAM by reducing the capacity of the bit line.

  Referring to FIG. 41, the bit line capacitance of VΦT-DRAM mainly includes a bit line-silicon substrate capacitance 36, a bit line-bit line capacitance 37, and a bit line-word line capacitance 38. Is the sum of

Referring to FIG. 41, in the SOI substrate, since buried SiO ₂ layer 20 exists under the SOI layer which is bit line 24, capacitance 36 between bit line 24 and substrate 1 is very small. However, when an SOI substrate is formed by the SIMOX method, the thickness of the buried SiO ₂ layer 20 cannot be arbitrarily determined due to the manufacturing method. The film thickness of the buried SiO ₂ layer 20 is about 4000 mm. However, when the bonded SOI substrate is used, the thickness of the embedded SiO ₂ layer can be freely selected. Referring to FIG. 42, if a VΦT-DRAM is formed using an SOI substrate having a buried SiO ₂ layer 20 having a film thickness of 0.5 μm or more, sufficient capacitance 36 between bit line 24 and substrate 1 is obtained. Since the size can be reduced, the VΦT-DRAM can be further increased in speed.

Example 14
This embodiment relates to lowering the capacitance between a bit line and a word line.

  Referring to FIG. 41, part 25a of word line 25 is fitted in the groove between bit line 24 and bit line 24, so that capacitance 38 between word line 25 and bit line 24 increases. Yes.

  43 to 45 relate to a method of manufacturing a VΦT-DRAM improved so as to reduce the capacitance between the bit line and the word line.

Referring to FIG. 43, grooves 36 are formed in the shape of bit lines in the surface of buried SiO ₂ layer 20. Referring to FIG. 44, a polysilicon layer 37 is formed on buried SiO ₂ layer 20 so as to fill trench 36. Referring to FIGS. 44 and 45, by etching back polysilicon layer 37, bit line 24 embedded in trench 36 is formed. When the VΦT-DRAM is formed on the bit line 24, the word line 25 having a flat lower surface 25b is formed, whereby the capacitance 38 between the bit line 24 and the word line 25 can be reduced.

Example 15
This embodiment also relates to reducing the capacitance between the bit line and the word line.

Referring to FIG. 46, to deposit interlayer SiO ₂ film 38 on the buried SiO ₂ layer 20 to cover the bit line 24 to form a bit line 24 on buried SiO ₂ layer 20. The interlayer SiO ₂ film 38 is etched back to a desired height, and a VΦT-DRAM is formed on the bit line 24 as shown in FIG. Since the interlayer SiO ₂ film 38 is buried in the gap between the bit line 24 and the bit line 24, a VΦT-DRAM having a small capacitance 38 between the bit line 24 and the word line 25 is obtained. In this case, when the bit line 24 is formed of a single crystal, the channel 7 of VΦT becomes a single crystal.

Example 16
This embodiment also relates to reducing the capacitance between the bit line and the word line.

  FIG. 48 is a sectional view of the VΦT-DRAM according to the sixteenth embodiment. Referring to FIG. 48, in this embodiment, bit lines 24 are separated by LOCOS oxide film 39. Since the word line 25 and the bit line 24 are further separated by the LOCOS oxide film 39, the capacitance 38 between the bit line 24 and the word line 25 can be reduced. A method of obtaining the bit line 24 separated by the LOCOS oxide film 39 is as follows. That is, the surface of the SOI layer (24) is oxidized using a silicon nitride film (not shown) patterned in a predetermined shape as a mask to form a LOCOS oxide film 39. Thereafter, impurities are implanted through the silicon nitride film to form the bit line 24. The silicon nitride film used in the LOCOS process is used again when the VΦT gate insulating film is formed by oxidation.

  In combination with the silicidation of the bit line as shown in the eleventh embodiment, referring to FIG. 49, after forming the silicide layer 40 (TiSi, WSi) on the surface of the bit line 24, VΦT is again formed. It is necessary to deposit the SiN film 42 necessary for forming the gate insulating film.

Example 17
This embodiment relates to a margin between the bit line and the VΦT contact and a margin between the word line and the VΦT contact.

Referring to FIG. 50, bit line 24 is formed on buried SiO ₂ layer 20. A first interlayer insulating film 8 is formed on the buried SiO ₂ layer 20 so as to cover the bit line 24. A word line 25 is formed on the first interlayer insulating film 8. A second interlayer insulating film 9 is formed on first interlayer insulating film 8 so as to cover word line 25. An opening 9 a is formed in the second interlayer insulating film 9 at a position where a contact hole of VΦT is to be formed. In FIG. 50, the case where the edge 24a of the bit line 24 and the edge (9a) of the contact hole of VΦT coincide is shown, but even if it is slightly shifted due to mask displacement, there is no problem as will be described later.

  In this embodiment, the case where the width of the bit line 24 is 0.2 μm (this corresponds to the minimum line width) is exemplified.

Referring to FIGS. 50 and 51, 500 nm of SiO ₂ film 42 is deposited so as to uniformly cover openings 9a of second interlayer insulating film 9. By dry-etching the SiO ₂ film 42, the SiO ₂ film 43 is left in a sidewall shape as indicated by a dotted line.

Thereafter, a contact hole of VΦT is formed using the sidewall-like SiO ₂ film 43 as a mask. FIG. 52 shows a sectional view of the obtained contact hole 10 in the word line direction, and FIG. 53 shows a sectional view in the bit line direction. According to this method, referring to FIG. 52, the margin m ₁ between the VΦT contact and the bit line can be provided in the minimum line width w. Referring to FIG. 53, a margin m ₂ between the VΦT contact and the word line can be provided in the minimum line width w. As a result, the cell size can be made smaller than 4F ² and 4r ² . Here, r represents the minimum line width, and F (feature size) = r + α (α is a process margin).

  Further, by this method, the diameter of the channel of VΦT can be further reduced, so that a VΦT-DRAM having high speed, stability, and small area can be obtained.

Example 18
Example 18A
This embodiment relates to a method for obtaining a VΦT-DRAM cell having a cell size of 4r ² .

FIG. 54 is a plan view of a photomask for forming a bit line or a word line using a phase shift mask. In FIG. 54, a hatched portion 95 is a portion (shifter) where the phase of light is shifted by 180 °. A portion 96 between the shaded portion 95 and the shaded portion 95 is a portion where the phase shift of light is 0 °. The width W ₄ between the width W ₃ and shifter shifter is twice the respective minimum line width. FIG. 54 shows the light intensity on the wafer surface when the above-described photomask is irradiated with light. When the above-described mask and negative resist are used, a portion exposed to light remains after development. If the exposure time is adjusted appropriately, a thick bit in the minimum line width × 2 (W ₅ ) as shown in FIG. A space S between the line (BL) and the thin BL-BL can be formed.

Similarly, if a word line is formed, a contact hole for VΦT having a minimum line width (minimum dimension) can be formed at the intersection of the word line and the bit line, and thus a VΦT-DRAM having a cell size of 4r ^2. A cell can be realized.

In the following description, unless otherwise specified, 4F ² includes 4r ² .

Example 18B
FIG. 56 is a plan view of a photomask used in this embodiment. The photomask includes a 0 ° phase shifter, a 90 ° phase shifter, a 180 ° phase shifter, and a 270 ° phase shifter. 0 °, 90 °, 180 °, and 270 ° represent the phase of light shifted by the phase shifter. Since the light intensity is 0 at the part where the light emitted from the four shifters overlaps, only the very vicinity of the intersection part of the boundary of the shifter is opened small.

If a contact hole of VΦT is formed using a photomask as shown in FIG. 56 and a negative resist, the contact hole 10 smaller than the minimum dimension can be opened with reference to FIG. In the figure, m ₂ represents a process margin.

Next, a method for manufacturing the photomask shown in FIG. 56 will be described. 121, a first SiN film 90a, a first SiO ₂ film 90b, a second SiN film 90c, a second SiO ₂ film 90d, and a third SiN film 90e are formed on a quartz substrate 90. Then, a third SiO ₂ film 90f and a fourth SiN film 90g are sequentially deposited. The sum of the film thicknesses of the SiN film and the SiO ₂ film is set to 90 ° in terms of the phase of light.

  Next, a resist 90h is formed on the fourth SiN film 90g. The resist 90h is patterned so that an opening 90i is formed only on the portion where the phase difference is to be 0 °, 90 °, and 180 °. In FIG. 121, the shifters of 0 °, 90 °, 180 °, and 270 ° are shown side by side for convenience, but actually, the shifters are arranged in a grid pattern as shown in FIG.

Referring to FIG. 122, fourth SiN film 90g and third SiO ₂ film 90f are etched using resist 90h as a mask. At this time, the third SiN film 90e functions as an etching stopper. Therefore, the film thickness to be etched is constant. After the etching is completed, the resist 90h is removed.

Referring to FIG. 123, a resist 90j is formed on quartz substrate 90. An opening 90k is provided only in a portion of the resist 90j where the phase difference is desired to be 0 ° and 90 °. Referring to FIG. 124, third SiN film 90e and second SiO ₂ film 90d are etched using resist 90j as a mask. At this time, the second SiN film 90c serves as an etching stopper. After the etching is completed, the resist 90j is removed.

Referring to FIG. 125, a resist 90l is formed on quartz substrate 90. The resist 90l is patterned so that an opening 90m is formed only in a portion of the resist 90l where the phase difference is desired to be 0 °. Referring to FIG. 126, second SiN film 90c and first SiO ₂ film 90b are etched using resist 90l as a mask. At this time, the first SiN film 90a serves as an etching stopper. After the etching is completed, the photomask is completed by removing the resist.

Except for the first SiN film 90a, there is nothing on the quartz substrate 90 and at the phase 0 °. A first SiN film 90a, a first SiO ₂ film 90b, and a second SiN film 90c exist above the 90 ° phase portion, and the sum of the film thicknesses is converted into a phase difference of light. 90 °.

  Therefore, the light transmitted through this 90 ° phase portion has a 90 ° phase difference with respect to the 0 ° phase portion.

  Similarly, light transmitted through the phase 180 ° and phase 270 ° portions has a phase difference of 180 ° and 270 ° with respect to the phase 0 ° portion, respectively.

  Referring to FIG. 127, a photomask as shown in FIG. 56 can also be obtained by a method of cutting the surface of quartz substrate 90 by FIB by the amount of each phase difference.

The following Examples 19 to 21 relate to improving the gate breakdown voltage of VΦT.
Example 19
Example 19 relates to improving the gate breakdown voltage of VΦT.

58 shows the surface of the bit line (BL) penetrating through the second interlayer insulating film (SiO ₂ ) 9, the word line (WL) 3, and the first interlayer insulating film (SiO ₂ ) 8. It is sectional drawing of an apparatus when the contact hole 10 is formed. A silicon nitride film (SiN) for preventing the surface of the bit line from being oxidized is provided on the surface of the bit line (BL).

  58 and 59, when the gate insulating film 4 is formed by a dry O2 oxidation method at 1100 ° C., the edge portion 45 of the word line (WL) can be rounded. By rounding the edge portion 45 of the word line (WL), the electric field concentrated on the edge portion 45 can be relaxed, and the gate breakdown voltage can be improved.

Example 20
This embodiment also relates to improving the gate breakdown voltage of VΦT.

FIG. 60 is a diagram for explaining the present embodiment. A bit line (BL) is formed on the buried SiO ₂ layer 20. A silicon nitride film (SiN) is formed on the bit line (BL). A first interlayer insulating film (SiO ₂ ) 8 is formed on the buried SiO ₂ layer 20 so as to cover the bit line (BL). A word line (WL) made of doped polysilicon is provided on the first interlayer insulating film 8. A second interlayer insulating film 9 is formed on the first interlayer insulating film 8 so as to cover the word line (WL). A contact hole 10 penetrating the second interlayer insulating film 9, the word line (WL), and the first interlayer insulating film 8 is formed. A gate insulating film 4 is formed by oxidizing the side surface of the word line (WL) made of doped polysilicon. Referring to FIG. 60, when the grain of doped polysilicon is fine, the surface of gate insulating film 4 is uneven according to the plane orientation of the grain of doped polysilicon, and the gate breakdown voltage is lowered. Therefore, referring to FIG. 61, doped amorphous silicon is deposited when the word line (WL) film is deposited. Next, this dope and amorphous silicon are solid-phase grown by annealing at about 600 ° C. to form polysilicon 97 having a large grain size. As a result, as shown in FIG. 61, the gate insulating film 4 with no breakdown and high breakdown voltage can be formed.

Example 21
As in Example 20, a word line film is deposited in the state of doped amorphous silicon. Next, a contact hole of VΦT is opened in the amorphous silicon state. Thereafter, the amorphous silicon is solid-phase grown simultaneously with the oxidation of the gate insulating film. Even if the gate insulating film is formed by this method, the same effect as that of the embodiment 20 is obtained, and the same device as that shown in FIG. 61 is obtained.

  Examples 22 to 25 relate to further improving the punch-through breakdown voltage of the VΦT transistor, thereby obtaining a VΦT-DRAM that is more resistant to disturb refresh.

Example 22
FIG. 62 is a sectional view of the VΦT-DRAM according to the twenty-second embodiment. When voltage is applied to the bit line 24 or charge is accumulated in the storage node 26, a depletion layer extends from the source or drain of VΦT. A state where the source and the drain are connected by the depletion layer is a punch-through state. The extension Xdmax of the depletion layer is expressed by the following equation where V _R is the voltage applied to the drain and N _A is the impurity concentration of the channel.

In the equation, K _s is the relative dielectric constant of silicon, ε ₀ is the dielectric constant of vacuum, and q is the amount of elementary charges. Φ _FP is the pseudo Fermi level of the channel, expressed by the following equation.

In the formula, k is a Boltzmann constant, T is an absolute temperature, and _ni is an intrinsic carrier concentration.
In order to improve the punch-through breakdown voltage, the thickness (t ₁ , t ₂ ) of the interlayer insulating film existing above and below the gate of VΦT is changed according to the extension Xdmax of the depletion layer. Specifically, the film thicknesses of the first interlayer insulating film and the second interlayer insulating film may be selected so as to satisfy the following expressions, respectively.

Interlayer insulating film thickness (t ₁ , t ₂ ) = Xdmax + impurity diffusion length (l 1, l 2)
For example, when the power supply voltage is 1.5 V (V _R = 1.5 V) and N _A = 1 × 10 ¹⁸ / cm ³ , Xdmax = 700Å.

Further, when N _A = 1 × 10 ¹⁷ / cm ³ , Xdmax = 2200 mm.
If the impurity diffusion length (l ₁ , l ₂ ) is 300 mm, the film thickness of the interlayer insulating film in the above case is 1000 mm and 2500 mm, respectively.

  By selecting the thickness of the interlayer insulating film in this way, the electric field is relaxed in the region (offset region) surrounded by the first and second interlayer insulating films in the channel of VΦT, so that punch-through is unlikely to occur. As a result, it becomes stronger to disturb refresh.

  Further, if the interlayer insulating films (8, 9) are deposited by CVD or the like, this offset region can be formed with very good controllability.

Example 23
FIG. 63 is a sectional view of a VΦT-DRAM according to the twenty-third embodiment. The DRAM shown in FIG. 63 is the same as the DRAM shown in FIG. 2 except for the following points. Therefore, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

  The apparatus shown in FIG. 63 is provided with LDD portions 46a and 46b instead of the offset in FIG. If LDD is used, the punch-through breakdown voltage can be increased as in the case of offset. As described in Japanese Patent Application No. 5-345126, the LDD is formed by implanting impurity ions into the bit line 24, the LDD portion 46a, the channel region 7, the LDD portion 46b, and the storage node 26 with the injection voltage and the injection voltage. Form by injecting in varying amounts.

  It can also be formed by introducing impurities in the LDD part during the epitaxial growth.

Example 24
This embodiment is a method for forming LDD using abnormal diffusion of phosphorus.

  64 is an impurity profile in the VΦT channel plug taken along the line CC ′ in FIG.

  In the case of the N channel, arsenic (As) and phosphorus (P) are generally used as the source / drain impurities, but the distribution is Gaussian. Unlike arsenic, phosphorous has a low-concentration distribution as shown in the figure. When this phenomenon is applied to VΦT, an LDD structure is automatically created. Thereby, the punch-through breakdown voltage is improved.

  In addition, since the offset and LDD in the above-described Examples 22 to 24 alleviate the electric field between the channel and the drain, the parasitic bipolar effect can also be prevented.

Example 25
Example 25 relates to increasing the punch-through breakdown voltage by changing the impurity profile of the channel.

  FIG. 65 shows the impurity profile of the channel cut along the line CC ′ in FIG. As shown in FIG. 65, when two channel implantations ((1) and (2)) with different implantation depths are performed, a channel profile having peaks at both ends of the channel is obtained.

  The extension of the depletion layer from the source / drain can be suppressed at the peak portions at both ends. Further, since the entire channel of VΦT is depleted or inverted at a portion where the concentration between peaks is low, an ideal S factor can be obtained and a high current driving capability can be obtained.

  Thereby, the punch-through breakdown voltage can be improved without impairing the advantage of VΦT. In the figure, the case of performing channel injection once is indicated by a dotted line 3 as a comparative example.

Example 26
Example 26 relates to suppressing the parasitic bipolar effect. Unlike a normal MOS transistor in which the channel potential is fixed at the well potential, the channel potential is electrically floating in VΦT. Therefore, majority carriers are accelerated in the high electric field portion between the channel and the drain, and these collide with the lattice of Si. Minority carriers generated by this collision are confined in the channel. This is called the impact ionization phenomenon. For example, in the case of N-channel VΦT, electrons are accelerated and holes are generated by impact ionization, which are confined in the channel, so that the potential of the channel decreases. Then, new electron injection from the source is invited to increase the drain current. This increased drain current causes further impact ionization, and positive feedback is applied, so that the electric field between the channel and the drain becomes stronger. As a result, a phenomenon in which the drain current increases discontinuously occurs. Since this is similar to the operation of a bipolar transistor, it is called a parasitic bipolar effect. The phenomenon that the drain current increases discontinuously makes the operation of the VΦT-DRAM unstable. In order to suppress this, there are a method of relaxing the electric field between the channel and the drain, a method of forming an offset, and a method of forming an LDD as shown in Examples 22-24.

  Also, as shown in FIG. 66, if P-channel VΦT is used for the memory cell of the VΦT-DRAM, the hole has a smaller impact ionization efficiency than the electron, so that the parasitic bipolar effect can be suppressed.

Example 27
Examples 27 and 28 relate to increasing the capacitor capacity of VΦT-DRAM.

  FIG. 67 shows the upper part of the contact hole of VΦT buried with amorphous silicon. The components of the VΦT-DRAM other than the capacitor are not shown. A contact hole 10 of VΦT is formed in the second interlayer insulating film 9. Amorphous silicon 15 is embedded in the contact hole 10. The amorphous silicon 15 is single-crystallized by epitaxial growth.

  67 and 68, after the channel portion of VΦT is made into a single crystal, this single crystal is etched back to expose the surface of second interlayer insulating film 9.

  Referring to FIGS. 68 and 69, polysilicon 47 having a small particle diameter is deposited on second interlayer insulating film 9.

  Conventionally, as a method of increasing the capacitor capacity, there has been a method of increasing the surface area by using polysilicon having a rough surface for the storage node, thereby increasing the capacitor capacity. For example, instead of polysilicon having a small particle size shown in FIG. 69, polysilicon having a large uneven surface as shown in FIG. 70 is deposited and processed into a storage node shape as shown in FIG. As a result, the upper surface of the storage node 26 is uneven, so that the capacity of the capacitor can be increased accordingly. However, in this method, the side surface 26a exposed by etching of the storage node 26 becomes a flat plane, and thus the surface area of the side surface 26a cannot be increased.

  Therefore, in this embodiment, referring to FIGS. 69 and 72, polysilicon 47 is patterned to form storage node 26. Referring to FIGS. 72 and 73, the surface of storage node 26 is oxidized. Since the grain boundary of polysilicon has a higher oxidation rate than the grain, the grain boundary of polysilicon is preferentially oxidized. As a result, irregularities corresponding to the size of the grains are formed on the upper and side surfaces of the storage node 26.

The SiO ₂ film 99 formed on the surface of the storage node 26 can be used as a capacitor insulating film as it is. However, as shown in FIG. 74, the SiO ₂ film is removed and the two-layer film of SiN and SiO ₂ is again formed. It is also possible to attach a film 49 having a high dielectric constant such as.

  By the above-described method, irregularities can also be formed on the side surface of the storage node 26, so that the capacitance of the capacitor can be sufficiently increased. Such a storage node can also be applied to DRAMs other than VΦT-DRAM.

Example 28
This embodiment relates to increasing the capacitance of a capacitor using a high dielectric material. Referring to FIGS. 68 and 75, after the amorphous silicon etch-back is completed, a titanium nitride film 50 is deposited, and a first Pt film 51 is deposited thereon. Process into shape. Next, a (Ba, Sr) TiO ₃ film 52 as a high dielectric film is deposited on the second interlayer insulating film 9. A second platinum film 53 is deposited on the (Ba, Sr) TiO ₃ film 52. A polysilicon cell plate 22 is formed on the second platinum film 53.

In the 4F ² DRAM cell, since the area for forming the capacitor is very small, it is effective to increase the capacitor capacity by using a high dielectric film such as a (Ba, Sr) TiO ₃ film. . In the present embodiment, the case where the (Ba, Sr) TiO ₃ film is used as the high dielectric film is exemplified, but the present invention is not limited to this, and other high dielectric films can also be used. .

Example 29
The present embodiment relates to increasing the degree of integration further than 4F ² or 4r ² .

Referring to FIG. 76, when VΦT contact holes 10 are arranged at the vertices of an equilateral triangle whose sides are twice the minimum line width, VΦT contact holes 10 are arranged at the highest density. At this time, the area 100 of one cell is 2√3r ² ≈3.5r ² , which indicates that the cell has a higher degree of integration than 4r ^{2 in} Examples 17 and 18.

  However, when this cell is used as a DRAM cell array, adjacent cells must be connected by a word line (WL) and a bit line (BL). In order to form a word line (WL) and a bit line (BL). The given width W4 is √3r≈1.73r.

  When making BL, normally, the width of BL (= r) and the width between BL and BL (= r) are added, and at least a width of 2r is required, but 1.73r is insufficient. Similarly, when a WL is formed, a width of at least 2r is required by adding the width of WL (= r) and the width between WL-WL (= r), but 1.73r is not sufficient.

Therefore, although a 3.5r ² cell cannot be obtained, if BL and WL are patterned using a mask having a phase shifter capable of shifting the phase by 180 ° at intervals of 1.73r as shown in FIG. BL, WL as shown in 77 can be formed, and a 3.5r ² cell is obtained.

Example 30
Examples 30 and 31 relate to the layout of peripheral circuits.

In the case of a 4F ² cell array, the space for creating peripheral circuits is also very small. As shown in FIG. 78, the sense amplifiers are arranged above and below the memory cells every other bit line BL, and the decoders are arranged on the left and right sides of the memory cells every other word line WL, thereby increasing the space for creating a peripheral circuit. Can take. The above concept may be applied only to either the sense amplifier or the decoder.

Example 31
This embodiment relates to a connection method in a DRAM cell array or in a peripheral circuit between VΦT and VΦT and a position where a contact is desired to be made is very deep.

  Referring to FIG. 79, if the position between VΦT and VΦT and the position where contact is desired is very deep, it is very difficult to directly contact with Al wiring 54 and there is a risk of disconnection. .

  Therefore, as shown in FIG. 80, if a dummy VΦT57 is provided between the first VΦT55 and the second VΦT56, the Al wiring 54 can be easily contacted.

  However, as shown in FIG. 80, the dummy VΦT channel section 7 needs to be introduced with a high concentration impurity having the same conductivity type as that of the source / drain.

Example 32
Example 32 relates to a process for forming a peripheral circuit of a VΦT-DRAM with SOI transistors.

Referring to FIG. 81, a substrate is prepared in which buried SiO ₂ layer 20 and SOI layer 30 are formed on silicon substrate 1. The SOI layer 30 is patterned to simultaneously form the active region 58 of the SOI transistor and the BL of the VΦT-DRAM cell array. Here, the active region 58 and BL are separated by patterning the SOI layer 30 by dry etching, but these may be separated by a LOCOS oxide film as in the sixteenth embodiment.

  By simultaneously patterning the SOI transistor active region 58 and the BL of the VΦT-DRAM, the process can be simplified.

  82, an SOI transistor gate insulating film 59 and gate electrode 60 are formed. Referring to FIG. 83, side wall spacers 101 are formed on the side walls of active region 58 and gate electrodes 60, BL. Ions are implanted into the source / drain portions 102a and 102b of the SOI transistor, and at the same time, ions are implanted into BL. This simultaneous injection further simplifies the process.

  Referring to FIG. 84, the surface of source 102a, the surface of gate electrode 60, the surface of drain 102b and the surface of BL of the SOI transistor are simultaneously silicidized, and silicide film 62 is formed on each surface. Since each surface is silicided simultaneously, the process can be simplified. Thereafter, VΦTDRAM is formed on BL.

  Next, another process for forming the peripheral circuit of VΦTDRAM with SOI transistors will be described.

Referring to FIG. 128, embedded SiO ₂ film 80a is provided on substrate 80. On the buried SiO ₂ film 80a, an SOI transistor source 80b, an SOI transistor channel 80c, an SOI transistor drain 80d, and a VΦT source 80e are provided. A gate 80f of VΦT is provided on the source of VΦT80e. A VΦT channel 80g is provided so as to penetrate the VΦT gate 80f.

  The channel 80g of VΦT is formed by being embedded and crystallized with amorphous silicon. Next, VΦT channel implantation 80h is performed. At this time, if VΦT channel implantation 80h is performed over the entire surface, the channel implantation impurity of VΦT is also introduced into the channel 80c of the SOI transistor. The threshold goes crazy. In order to avoid this, channel implantation of VΦT may be performed by covering the SOI transistor portion with a resist mask. However, doing so increases the number of masks by one and increases the manufacturing cost.

  Therefore, in order to solve this problem, referring to FIG. 129, the dummy pattern 80i of the gate of VΦT is arranged on the channel 80c of the SOI transistor. With this VΦT gate dummy pattern 80i, no impurity is introduced into the channel 80c of the SOI transistor even if the channel injection 80h of VΦT is performed on the entire surface. According to this method, since the mask is not used, the manufacturing cost does not increase.

Example 33
This embodiment relates to a stacked structure in which bit lines are shared by upper and lower VΦTDRAMs. FIG. 85 is a sectional view of the VΦTDRAM according to the thirty-seventh embodiment. A first VΦT 63 is formed on the bit line 24, and a trench type capacitor 64 is connected on the first VΦT. A second VΦT 65 is connected below the bit line 24, and a trench-type second capacitor 65 is connected to the second VΦT. Such a laminated structure is made by bonding the memory cell 1 and the memory cell 2 together. The structure of VΦT is the same as that shown in FIGS.

  According to this embodiment, the process of creating the bit line is only required once. Therefore, the number of processes can be reduced, and cost can be reduced. Further, since the thickness of one bit line layer can be reduced, the height of the memory cell portion can be suppressed, and the difference in height between the memory cell portion and the peripheral circuit can be reduced. Therefore, it becomes easy to create a semiconductor device. Furthermore, capacitive coupling between wirings can be reduced, and high speed and high performance can be achieved. Moreover, when making by bonding, a channel can be single-crystallized.

Example 34
In the conventional SOI structure transistor, it is difficult to fix the body electrode. As a result, there were the following problems. That is a phenomenon called latching. In FIG. 86, curve (a) represents the electrical characteristics of a normal bulk Si transistor. A curve (b) represents electrical characteristics of the SOI structure transistor. In a transistor having an SOI structure, unlike the characteristic (a) of a normal bulk Si transistor, when the gate voltage is increased, a drain current suddenly flows out from a certain voltage. This phenomenon is considered to be caused by the following reasons.

  Referring to FIG. 87, when a positive voltage is applied to gate electrode 305, electrons 307 flow from source 302 to drain 303 on the surface of body 301. In the vicinity of the drain 303, since the electric field is strong, a phenomenon called impact ionization occurs in which accelerated electrons collide with the silicon crystal lattice to generate electron-hole pairs. The generated electrons are absorbed by the drain 303, but the holes 306 are accumulated in the body 301 and raise the potential of the body 301. When the potential of the body 301 rises, more electrons are injected from the source 302, the above phenomenon works in positive feedback, and the drain current flows excessively. This problem occurs because the body 301 is floating.

The thirty-fourth embodiment has been made to solve the above problems.
FIG. 88 is a cross-sectional view of VΦT according to the thirty-fourth embodiment. In the main surface of the substrate 1, a first impurity diffusion layer 6a serving as one of the source / drain regions is provided. A first interlayer insulating film 2 a is provided on the substrate 1. A gate electrode 3 is provided on the first interlayer insulating film 2a. A second interlayer insulating film 2 b is provided on the first interlayer insulating film 2 a so as to cover the gate electrode 3. A contact hole 19 for exposing a part of the surface of the first impurity diffusion layer 6a is provided so as to penetrate the first interlayer insulating film 2a, the gate electrode 3 and the second interlayer insulating film 2b. The side wall surface of the contact hole 19 is covered with the gate insulating film 4. The device is provided so as to be in contact with the first impurity diffusion layer 6a and continuously cover the side wall surface of the contact hole 19 with a gate insulating film interposed, and having a recess in the contact hole 19 portion. A thin film 39 is provided. The silicon thin film 39 is divided into three portions: a cylindrical channel region 7 located in a portion surrounded by the gate electrode 3, and a source region 6aa and a drain region 6b sandwiching the channel region 7 from above and below. A silicon oxide film 32 is embedded in the recess of the silicon thin film 39 at a position lower than the channel region 7. A body polysilicon 66 is buried in the recess of the silicon thin film 39 and on the silicon oxide film 32. Body polysilicon 66 is in contact with channel region 7. By using the body polysilicon 66 as an extraction electrode, the potential of the channel region 7 can be fixed. Body polysilicon 66 is in contact with aluminum electrode 68 through body contact 67 provided in silicon oxide film 103. A P ⁺ layer 69 is formed on the surface of the body polysilicon 66. Aluminum electrode 68 and body silicon 66 are ohmically connected through P ⁺ layer 69.

The device shown in FIG. 88 is manufactured as follows.
Referring to FIG. 89, silicon oxide film 32 is embedded in contact portion 19, the surface of silicon oxide film 32 is etched away, and the upper end of channel region 7 is exposed. Thereafter, referring to FIGS. 89 and 90, body polysilicon 66 having a P-type impurity added to the entire surface is deposited by LPCVD. The film thickness of the body polysilicon 66 is set so as to fill the contact hole 19. The body polysilicon 66 is etched until the drain region 6b is exposed. As a result, the body polysilicon 66 is buried in the contact hole 19. Next, returning to FIG. 88, a silicon oxide film 103 is deposited and a body contact 67 is opened. Arsenic is implanted into the opening, and a P ⁺ layer 69 is formed on the surface of the body contact by self-alignment. An aluminum electrode 68 is connected to the P ⁺ layer 69.

  In the above embodiment, the aluminum electrode 68 is brought into contact with the body polysilicon 66. However, the present invention is not limited to this, and polysilicon may be used instead of aluminum.

  Moreover, it seems difficult to detect the end point when etching the body polysilicon 66 only with FIG. However, the drain region 6b is actually patterned, and the second interlayer insulating film 2b is exposed in most regions. Therefore, there is no problem because the end point may be when the second interlayer insulating film 2b is exposed.

Example 35
FIG. 91 is a cross-sectional view of VΦT according to the thirty-fifth embodiment. In this embodiment, unlike the embodiment 34, the body polysilicon 66 does not completely fill the contact hole 19. Even with such a structure, the potential of the channel region 7 can be fixed. However, in this embodiment, since an aluminum electrode cannot be connected to the body polysilicon 66 on the transistor, aluminum must be connected at a place other than the transistor. On the other hand, in Example 34, the body polysilicon must be deposited thick, but Example 35 has an advantage that a thin film is sufficient.

  In Examples 34 and 35, the upper side of the channel region is the drain region and the lower side is the source region, but these may be reversed. If the upper side is the drain, the junction area between the drain and the body polysilicon is increased, which may result in an increase in drain leakage current and a decrease in drain breakdown voltage. Therefore, in the structure according to the embodiment, the source is better on the upper side.

  According to the thirty-fourth and thirty-fifth embodiments, the body potential of the channel region can be fixed by the body polysilicon, so that the latch due to the parasitic bipolar effect does not occur, and the generation of an abnormal drain current can be suppressed.

Example 36
In VΦT of Japanese Patent Application No. 5-345126, the diameter of the cylindrical body of VΦT is determined by the inner diameter of the contact hole. Therefore, VΦT having a body with a diameter smaller than the minimum hole diameter determined by the lithography technique cannot be obtained. When the diameter of the body is large, the junction area at the drain end increases, and as a result, the leakage current proportional to the area increases. Further, if the body is thick, it is difficult to completely deplete the body, and there is a problem that the drain current cannot be increased.

The present embodiment has been made to solve the above problems.
Referring to FIG. 92, 500 nm of silicon nitride film 12 is deposited on n ⁻ type substrate 1. The silicon nitride film 12 is patterned into a predetermined shape. A portion where the silicon nitride film 12 is not covered is oxidized, and an isolation oxide film 13 is formed on the main surface of the substrate 1. Impurities are implanted into the main surface of the substrate 1 through the silicon nitride film 12 to form the source region 6. 200 μm of first interlayer insulating film 2 a is deposited on substrate 1 so as to cover silicon nitride film 12 and isolation oxide film 13. On the first interlayer insulating film 2a, 500 nm of polysilicon is deposited and patterned to form the gate electrode 3. A second interlayer insulating film 2 b is deposited on the substrate 1 so as to cover the gate electrode 3. A contact hole 8 is formed through the first interlayer insulating film 2a, the gate electrode 3, and the second interlayer insulating film 2b to expose the surface 9a of the silicon nitride film 12. Polysilicon 70 doped with n-type impurities is deposited on the entire surface by a 200 nm LP-CVD method.

  92 and 93, when the entire surface of polysilicon 70 is etched by an anisotropic dry etching method, polysilicon side wall 71 is formed on the inner wall of contact hole 8 to a thickness of 200 nm. Is done. If the inner diameter of the contact hole 8 is 600 nm, the inner diameter of the remaining space in the contact hole is 200 nm.

  Referring to FIG. 94, the surface of sidewall spacer 71 is oxidized by a thermal oxidation method at 800 ° C. to 1000 ° C. to form gate insulating film 4 made of a silicon oxide film. At this time, the surface of the silicon substrate 1 at the bottom of the contact hole 8 is not oxidized because it is covered with the silicon nitride film 12. 94 and 95, silicon nitride film 12 exposed at the bottom of the contact hole is removed using a phosphoric acid solution.

  At this time, since the etching also proceeds in the lateral direction, if the etching becomes excessive, the silicon nitride film 12 below the side wall spacer 71 is removed, so that the channel polysilicon and side wall spacers deposited in a later step are removed. 71 comes into contact. Therefore, it is important that this etching with phosphoric acid is not performed excessively. If there is a problem, it is preferable to use anisotropic dry etching. However, in this case, since the gate insulating film 4 is also exposed to etching, this etching is required to have a high etching selection ratio between the silicon oxide film and the silicon nitride film and less damage.

Referring to FIG. 95, silicon 103 serving as the body of the transistor is deposited by the LP-CVD method to fill the contact hole 8 with this. Thereafter, the silicon 103 is crystallized by a solid phase growth method (annealing at 600 ° C.). Thereafter, impurities are implanted into the surface of silicon to form the drain region 6b. In the case of the P-channel, a P-type impurity such as boron is implanted at an implantation energy of 8 keV and a concentration of 5 × 10 ¹⁵ / cm ² . When heat treatment is performed at 850 ° C. for about 30 minutes, impurities diffuse from the source region 6 into the silicon 103 and diffuse from the drain region 6 b into the silicon 103. Thereby, VΦT is completed. In this embodiment, since the polysilicon side wall spacer 71 is formed on the inner wall of the contact hole 8, the diameter of the columnar channel 7 is larger than the inner diameter of the contact hole 8 and the thickness of the side wall spacer 71 and the gate insulating film. 4 times the thickness of 4 plus the thickness. Since the sidewall spacer 71 made of polysilicon is in contact with the gate electrode 3, the sidewall spacer 71 acts as the gate of the transistor, and there is no problem in operation.

Example 37
96 is a cross-sectional view of VΦT according to Example 37. FIG.

  In VΦT shown in FIG. 95, the upper end of the sidewall spacer 71 coincides with the upper surface of the second interlayer insulating film 2b. With such a structure, the overlap between the drain portion 6b and the gate (sidewall spacer 71) is large, the capacity increases, and consequently the circuit speed may be reduced, and the leakage current induced by the drain voltage may increase. There is. The present embodiment has been made to solve this problem.

  Referring to FIG. 96, the upper end of sidewall spacer 71 which is the second gate is set lower than the upper surface of second interlayer insulating film 2b. With this configuration, there is no overlap between the drain portion 6b and the gate (sidewall spacer 71), and the above problem is solved. However, the junction area between the drain 6b and the channel 7 is determined by the inner diameter of the contact hole 8 and becomes wider as originally.

  In the example 36 and example 37, the case where the upper part is the drain and the lower part is the source is illustrated, but the opposite may be possible. In particular, in Example 37, when the drain is at the bottom, the junction area at the drain end can be reduced, and the leakage current can be reduced. In this case, if the thickness of the silicon nitride film 12 is increased, the capacitance of the drain 6b and the gate (71) can be reduced. Since the silicon nitride film 12 has a dielectric constant twice that of the silicon oxide film, the thickness of the silicon nitride film 12 needs to be at least twice that of the silicon oxide film as the gate insulating film 4 (capacitance = dielectric constant). / Film thickness).

  According to this embodiment, since the silicon side wall spacer is formed on the inner wall of the contact hole and used as the gate electrode, the diameter of the channel portion of the body can be reduced. As a result, it is possible to reduce the leakage current and increase the drain current when turned on.

Example 38
The present embodiment relates to a two-input OR circuit using VΦT.

  Referring to FIG. 97, when a contact hole of VΦT is formed so as to straddle between two gates (first gate 72 and second gate 73), a circuit as shown in a dotted line in FIG. Can be made in a very small area. As shown in FIG. 98, a 2-input OR circuit can be easily formed by attaching a load such as a resistor to the circuit. This OR circuit is very sensitive to the mask. For example, in FIG. 97, when the VΦT contact hole 74 is shifted upward, the first channel 104 becomes wider and the second channel 105 becomes narrower. In other words, the first channel 104 becomes narrower and the second channel 105 becomes wider.

  In FIG. 98, by comparing the current between Vcc and GND when the first gate 72 and the second gate 73 are separately turned on, the amount of mask deviation can be known electrically. In this way, when used as a mask displacement detection circuit, it is not necessary to add a load in FIG. Also, changing the shape of the contact hole of VΦT changes the channel width change method with respect to the shift, so that the sensitivity can be changed.

  Just as in the above embodiment, referring to FIG. 99, if a contact hole of VΦT is provided at the intersection of the gates patterned in a cross shape, a 4-input OR circuit as shown in FIG. 100 can be obtained. Further, by changing the shape of the contact hole of VΦT, an OR circuit having more inputs can be made.

Example 39
This embodiment relates to forming a 2-input AND circuit using VΦT.

FIG. 101 is a cross-sectional view of an AND circuit using VΦT according to the 39th embodiment. A first SiO ₂ film 75 is provided so as to cover the GND. A first gate 76 is provided on the first SiO ₂ film 75. A second SiO ₂ film 77 is provided on the first SiO ₂ film 75 so as to cover the first gate 76. A second gate electrode 78 is provided on the second SiO ₂ film 77. A third SiO ₂ film 79 is provided on the second SiO ₂ film 77 so as to cover the second gate electrode 78. Contact for exposing the surface of the GND through the third SiO ₂ film 79, the second gate electrode 78, the second SiO ₂ film 77, the first gate electrode 76, and the first SiO ₂ film 75 A hole 10 is provided. In the contact hole 10, an N ⁺ semiconductor layer 106, an N ⁻ semiconductor layer 107, and an N ⁺ semiconductor layer 108 are sequentially formed. The p ⁻ semiconductor layer surrounded by the first gate electrode 76 is the first channel, and the p ⁻ semiconductor layer surrounded by the second gate electrode 78 is the second channel.

  As described above, if a contact hole of VΦT is formed so as to penetrate the two gates 76 and 78, a 2-input AND circuit as shown in FIG. 103 is formed. If the contact holes of VΦT are formed by overlapping the gates, the number of inputs can be further increased.

As shown in FIG. 101, when the interlayer film (second SiO ₂ film 77) between the two gates is thin, it is necessary to introduce high-concentration impurities of the same conductivity type as the source / drain between the channels of VΦT. However, when the thickness of the second SiO ₂ film 77 is large as shown in FIG. 102, it is necessary to introduce a high-concentration impurity having the same conductivity type as the source / drain between the two channels. As a method for introducing impurities, there are a method by ion implantation and a method of epitaxial growth.

  Further, as shown in FIG. 104, the second VΦT81 may be formed after the first VΦT80 is formed.

In the circuits shown in the thirty-eighth and thirty-ninth embodiments, the P type and the N type may be interchanged.
Example 40
FIG. 105 is a cross-sectional view of the semiconductor device according to Example 40 in which an inverter circuit is formed by vertically stacking P-channel VΦT and N-channel VΦT. In order to eliminate the PN junction formed between the two VΦTs, a silicide 82 is sandwiched between them.

  An opening 82a is provided in a part of the silicide 82 in order to single-crystal the channel of the P channel VΦT. However, if it is not necessary to single-crystal the channel of the P channel VΦT, it is not necessary to provide such an opening 82 a in the silicide 82.

Example 41
FIG. 106 is a cross-sectional view of the semiconductor device according to Example 41. FIG. Referring to FIG. 106, the two VΦTs share the first VΦT gate and the second VΦT source, and share the first VΦT drain and the second VΦT gate. Then, a circuit as shown in FIG. 107 can be made. When such a structure is formed by the P channel VΦT and the N channel VΦT and is connected as shown in FIG. 108, a flip-flop can be formed.

  In FIG. 106, in order to single-crystal the channel of the second VΦT, the gate of the first VΦT needs to be a single crystal. A single-crystal first VΦT gate can be obtained by laminating a single-crystal first VΦT gate on the SiO2 film from a layer on the first VΦT source.

Example 42
This embodiment relates to a gain cell using VΦT.

  Referring to FIG. 109, when VΦT is formed on the gate electrode of the bulk MOS transistor, a circuit as shown in FIG. 110 can be formed. As a result, the gain cell (the charge accumulated in the storage node is transferred to the cell). A cell that can be amplified and read out in a cell). Writing is performed using WL and writing BL as in the case of DRAM.

When reading the electric charge stored in the storage node, the WL voltage and the write BL voltage are changed as shown in FIG. When the storage node is charged, the MOS transistor is immediately turned on, and a current immediately flows into the read BL. However, when no charge is stored in the storage node, it is necessary to allow excess charge to flow from the write BL to turn on the MOS transistor, so that a current does not easily flow through the read BL. Further, the _Vth of the MOS transistor is set high so that a leak current does not flow through the MOS transistor when the cell is not being accessed. The MOS transistor has a very high sensitivity for detecting the gate charge amount because the current is greatly amplified and changed with only a slight change in the gate charge amount.

When the gate charge is detected, the write BL voltage is changed and rewriting is performed.
Like the DRAM, the gain cell leaks the storage node charge due to the leakage current of VΦT. Therefore, it is necessary to refresh the data by performing this read operation every certain period. Such a circuit operation can be applied to any structure as long as the circuit is shown in FIG.

An SOI transistor may be used as the MOS transistor.
Also, as shown in FIG. 112, a structure that is upside down from that of FIG. 109 may be used.

  In the case of the device shown in FIG. 109, since the contact of VΦT comes on the gate polysilicon of the MOS transistor, the channel of VΦT cannot be monocrystallized by epitaxial growth. However, in the case of the apparatus shown in FIG. 112, the channel of VΦT can be single-crystallized by epitaxial growth. At this time, the upper MOS transistor may be a polysilicon TFT.

Example 43
FIG. 113 is a conceptual diagram of an apparatus according to Example 43. As shown in FIG. 113, VΦT can be applied to the matrix of the liquid crystal display.

  That is, the structure shown in FIG. 113 can be obtained by replacing the storage node portion in the DRAM cell array shown in FIG. 3 with a pixel electrode.

It is a perspective view of VΦT according to Embodiment 1 of the present invention. It is sectional drawing which follows the II-II line in FIG. It is a layout diagram of a cell array of DRAM using VΦT. FIG. 6 is a cross-sectional view of the semiconductor device in the first step in the order of the method of manufacturing a DRAM using VΦT according to the first embodiment. FIG. 6 is a cross-sectional view of the semiconductor device in the second step in the order of the method for manufacturing the DRAM using VΦT according to the first embodiment. FIG. 10 is a cross-sectional view of the semiconductor device in the third step in the order of the method of manufacturing a DRAM using VΦT according to the first embodiment. FIG. 10 is a cross-sectional view of the semiconductor device in the fourth step in the order of the method of manufacturing a DRAM using VΦT according to the first embodiment. FIG. 10 is a cross-sectional view of the semiconductor device in the fifth step in the order of the method of manufacturing a DRAM using VΦT according to the first embodiment. It is sectional drawing of the semiconductor device in the 6th process of the order of the manufacturing method of DRAM which uses V (PHI) T based on Example 1. FIG. FIG. 10 is a cross-sectional view of the semiconductor device in the seventh step in the order of the method of manufacturing a DRAM using VΦT according to the first embodiment. It is sectional drawing of the semiconductor device in the 8th process of the order of the manufacturing method of DRAM which uses V (PHI) T based on Example 1. FIG. It is sectional drawing of the semiconductor device in the 9th process of the order of the manufacturing method of DRAM which uses V (PHI) T based on Example 1. FIG. It is sectional drawing of the semiconductor device in the 10th process of the order of the manufacturing method of DRAM using V (PHI) T based on Example 1. FIG. It is sectional drawing of the semiconductor device in the 11th process of the order of the manufacturing method of DRAM using V (PHI) T based on Example 1. FIG. It is sectional drawing of the semiconductor device in the 12th process of the order of the manufacturing method of DRAM which uses V (PHI) T based on Example 1. FIG. 1 is an equivalent circuit diagram of a DRAM array according to Embodiment 1. FIG. FIG. 6 is a cross-sectional view of a main part of a DRAM cell using VΦT according to a second embodiment. 7 is a cross-sectional view of a main part of a DRAM cell according to Embodiment 3. FIG. 7 is a cross-sectional view of a main part of a DRAM cell according to Embodiment 4. FIG. 14 is a cross-sectional view of a main part of another DRAM cell according to Embodiment 4. FIG. FIG. 14 is a cross-sectional view of the main part of still another DRAM cell according to Embodiment 4. FIG. 10 is a perspective view of a main part of a DRAM cell array according to Embodiment 5. 12 is a cross-sectional view of a semiconductor device in a first step in the sequence of a method for manufacturing a DRAM cell array according to Embodiment 5. FIG. FIG. 10D is a cross-sectional view of the semiconductor device in the second process in the order of the method of manufacturing the DRAM cell array according to the fifth embodiment. FIG. 10D is a cross-sectional view of the semiconductor device in the third step in the sequence of the manufacturing method of the DRAM cell array according to the fifth embodiment. FIG. 10D is a cross-sectional view of the semiconductor device in the fourth process in the order of the manufacturing method of the DRAM cell array according to Embodiment 5; FIG. 10D is a cross-sectional view of the semiconductor device in the fifth process in the order of the manufacturing method of the DRAM cell array according to the fifth embodiment. 12 is a cross-sectional view of a semiconductor device in a first step in the sequence of a method for manufacturing a semiconductor device according to Example 6. FIG. 12 is a cross-sectional view of a semiconductor device in a second step in the sequence of the method for manufacturing a semiconductor device according to Example 6. FIG. 7 is a cross-sectional view of a semiconductor device according to Example 7. FIG. FIG. 10 is a cross-sectional view of another semiconductor device according to Example 7. FIG. 10A is a cross-sectional view of a semiconductor device in a first process in the order of the manufacturing method of the semiconductor device according to Example 8; FIG. 12A is a cross-sectional view of a semiconductor device in a second process in the order of the manufacturing method of the semiconductor device according to Example 8; FIG. 10 is a diagram for explaining the method for manufacturing the semiconductor device according to Example 9. FIG. 10A is a cross-sectional view of a semiconductor device in a first process in the order of the manufacturing method of the semiconductor device according to Example 9; It is sectional drawing of the semiconductor device in the 2nd process of the order of the manufacturing method of the semiconductor device which concerns on Example 9. FIG. 12 is a cross-sectional view of a semiconductor device according to Example 10. FIG. FIG. 10 is a cross-sectional view of another semiconductor device according to Example 10; 12 is a sectional view of a semiconductor device according to Example 11. FIG. 14 is a cross-sectional view of a semiconductor device according to Example 12. FIG. It is a figure for demonstrating the objective which performed Examples 13-16. 14 is a sectional view of a semiconductor device according to Example 13. FIG. 24 is a cross-sectional view of a semiconductor device in a first process in the order of the manufacturing method of the semiconductor device according to Example 14. FIG. FIG. 29 is a cross-sectional view of a semiconductor device in a second process in the order of the manufacturing method of the semiconductor device according to Example 14; FIG. 29 is a cross-sectional view of a semiconductor device in a third step in the sequence of the manufacturing method of the semiconductor device according to Example 14; FIG. 29A is a cross-sectional view of a semiconductor device in a first process in the order of the manufacturing method of the semiconductor device according to Example 15; FIG. 28A is a cross-sectional view of a semiconductor device in a second process in the order of the manufacturing method of the semiconductor device according to Example 15; 22 is a cross-sectional view of a semiconductor device according to Example 16. FIG. FIG. 30 is a cross-sectional view of another semiconductor device according to Example 16; 24 is a cross-sectional view of a semiconductor device in a first process in the order of the manufacturing method of the semiconductor device according to Example 17. FIG. 24 is a sectional view of a semiconductor device in a second process in the order of the manufacturing method of the semiconductor device according to Example 17. FIG. FIG. 29 is a cross-sectional view of a semiconductor device in a third step in the sequence of the manufacturing method of the semiconductor device according to Example 17; FIG. 29D is another cross-sectional view in the third step in the sequence of the manufacturing method of the semiconductor device according to Example 17; It is a top view of the photomask used in Example 18A. It is a top view of the VΦTDRAM cell according to Example 18A. It is a top view of the photomask used in Example 18B. FIG. 44 is a layout view of contact holes of VΦT according to Example 18B. FIG. 29A is a cross-sectional view of a semiconductor device in a first process in the order of the manufacturing method of the semiconductor device according to Example 19; FIG. 29A is a cross-sectional view of a semiconductor device in a second process in the order of the manufacturing method of the semiconductor device according to Example 19; 22 is a cross-sectional view of a semiconductor device according to Example 20. FIG. 22 is a sectional view of a semiconductor device according to Example 21. FIG. 24 is a cross-sectional view of a VΦT-DRAM according to Example 22. FIG. 24 is a cross-sectional view of a VΦT-DRAM according to Embodiment 23. FIG. FIG. 63 is an impurity profile in a VΦT channel plug cut along the line CC ′ in FIG. 62. FIG. FIG. 63 is an impurity profile of a channel cut along the line CC ′ in FIG. 62. FIG. 27 is a cross-sectional view of a semiconductor device according to Example 26. FIG. 27 is a cross-sectional view of a semiconductor device in a first process in the order of the manufacturing method of the semiconductor device according to Example 27; FIG. 27 is a cross-sectional view of a semiconductor device in a second process in the order of the manufacturing method of the semiconductor device according to Example 27; FIG. 27 is a cross-sectional view of a semiconductor device in a third step in the sequence of the manufacturing method of the semiconductor device according to Example 27; FIG. It is sectional drawing of the conventional semiconductor device. It is sectional drawing of the conventional semiconductor device. 27 is a cross-sectional view of a semiconductor device in a fourth step in the sequence of the manufacturing method of the semiconductor device according to Example 27; FIG. 27 is a cross-sectional view of a semiconductor device in a fifth step in the sequence of the manufacturing method of the semiconductor device according to Example 27; FIG. FIG. 28A is a cross-sectional view of a semiconductor device in a sixth step in the sequence of the manufacturing method of the semiconductor device according to Example 27; 42 is a cross-sectional view of a semiconductor device according to Example 28; FIG. FIG. 38 is a layout diagram of contact holes of VΦT according to Example 29. FIG. 44 is a layout diagram of BL and WL according to Example 29. 32 is a layout of a peripheral circuit of a semiconductor device according to Example 30. It is a figure for demonstrating the objective which performed Example 31. FIG. 42 is a cross-sectional view of a semiconductor device according to Example 31; FIG. 32 is a cross-sectional view of a semiconductor device in a first process in the order of the manufacturing method of the semiconductor device according to Example 32; FIG. 42 is a cross-sectional view of a semiconductor device in a second step in the sequence of the method for manufacturing a semiconductor device according to Example 32. FIG. 32 is a sectional view of a semiconductor device in a third step in the sequence of the manufacturing method of the semiconductor device according to Example 32. FIG. 32 is a cross-sectional view of a semiconductor device in a fourth step in the sequence of the method for manufacturing a semiconductor device according to Example 32. FIG. 42 is a cross-sectional view of a semiconductor device according to Example 33. FIG. It is a figure for demonstrating the problem of the transistor of the conventional SOI structure. It is a figure for demonstrating the problem which generate | occur | produces in the transistor of the conventional SOI structure. 42 is a cross-sectional view of a semiconductor device according to Example 34; FIG. FIG. 46 is a cross-sectional view of a semiconductor device in a first process in the order of the manufacturing method of the semiconductor device according to Example 34; FIG. 48 is a sectional view of a semiconductor device in a second process in the order of the manufacturing method of the semiconductor device according to Example 34; 42 is a cross-sectional view of a semiconductor device according to Example 35; FIG. 42 is a cross-sectional view of a semiconductor device in a first process in the order of the manufacturing method of the semiconductor device according to Example 36; FIG. 42 is a cross-sectional view of a semiconductor device in a second process in the order of the manufacturing method of the semiconductor device according to Example 36. FIG. FIG. 29A is a cross-sectional view of a semiconductor device in a third step in the sequence of the manufacturing method of the semiconductor device according to Example 36. FIG. 46 is a cross-sectional view of a semiconductor device in a fourth step in the sequence of the manufacturing method of the semiconductor device according to Example 36; 42 is a cross-sectional view of another semiconductor device according to Example 37; FIG. FIG. 38 is a plan view of a two-input OR circuit using VΦT according to Example 38. 98 is a circuit diagram of the semiconductor device shown in FIG. 97. FIG. FIG. 44 is a plan view of another semiconductor device according to Example 38. FIG. 100 is a circuit diagram of the semiconductor device shown in FIG. 99. 42 is a cross-sectional view of a semiconductor device according to Example 39; FIG. 42 is a cross-sectional view of another semiconductor device according to Example 39; FIG. It is a circuit diagram of the AND circuit shown in FIG. FIG. 38 is a cross-sectional view of still another semiconductor device according to Example 39. 42 is a cross-sectional view of a semiconductor device according to Example 40; FIG. 42 is a cross-sectional view of a semiconductor device according to Example 41; FIG. 42 is a circuit diagram of a semiconductor device according to Example 41; FIG. 40 is a circuit diagram of a flip-flop circuit according to Example 41. FIG. 42 is a cross-sectional view of a gain cell according to Example 42. FIG. FIG. 45 is a circuit diagram of a circuit made using a gain cell according to Example 42. FIG. 38 is a diagram for explaining an operation of the semiconductor device according to Example 42. 42 is a cross-sectional view of another semiconductor device according to Example 40; FIG. 44 is a plan view of a matrix of a liquid crystal display according to Example 43. FIG. It is a figure of the trend of DRAM cell size. It is sectional drawing of the conventional vertical surround gate transistor. FIG. 116 is a cross sectional view for illustrating the method for manufacturing the semiconductor device shown in FIG. 115. It is sectional drawing of the semiconductor device in the 1st process of the order of the manufacturing method of the conventional vertical surround gate transistor. It is sectional drawing of the semiconductor device in the 2nd process of the order of the manufacturing method of the conventional vertical surround gate transistor. FIG. 3 is a perspective view of a vertical phi-shape transistor previously proposed by the applicant. FIG. 119 is a cross-sectional view of the semiconductor device shown in FIG. 119. FIG. 57 is a cross-sectional view of a substrate in a first step in the order of the manufacturing method of the photomask shown in FIG. 56. FIG. 57 is a cross-sectional view of a substrate in a second step in the order of the manufacturing method of the photomask shown in FIG. 56. FIG. 57 is a cross-sectional view of a substrate in a third step in the order of the manufacturing method of the photomask shown in FIG. 56. FIG. 57 is a cross sectional view of a substrate in a fourth step in the order of the manufacturing method of the photomask shown in FIG. 56. FIG. 57 is a cross sectional view of a substrate in a fifth step in the order of the manufacturing method of the photomask shown in FIG. 56. FIG. 57 is a cross sectional view of a substrate in a sixth step in the order of the manufacturing method of the photomask shown in FIG. 56. FIG. 57 is a diagram for explaining another method of manufacturing the photomask shown in FIG. 56. It is sectional drawing of the semiconductor device which shows the problem of the manufacturing method of the other semiconductor device which formed the peripheral circuit with the SOI transistor. It is sectional drawing of the semiconductor device which shows the improved manufacturing method of the other semiconductor device which formed the peripheral circuit with the SOI transistor.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Substrate, 3 Gate electrode, 4 Gate insulating film, 8 First interlayer insulating film, 9 Second interlayer insulating film, 10 Contact hole, 11 First semiconductor layer, 12 channel semiconductor layer, 13 Second conductive layer , 21 capacitor insulating film, 22 cell plate, 24 bit line, 26 storage node, 201 buried SiO ₂ layer.

Claims (14)

A semiconductor device manufacturing method for storing information by a gate transistor in a capacitor comprising a storage node, a capacitor insulating film and a cell plate electrode provided at an intersection of a bit line and a word line,
Preparing a substrate on which a dielectric and a semiconductor layer are sequentially formed; and
Forming a first conductive layer containing a first conductivity type impurity which becomes one of the source / drain regions and also becomes the bit line in the surface of the semiconductor layer;
Forming a first interlayer insulating film on the substrate;
Forming a gate electrode having an upper surface and a lower surface, which also serves as the word line, on the first interlayer insulating film;
Forming a second interlayer insulating film on the substrate so as to cover the gate electrode;
Forming a contact hole that penetrates the first interlayer insulating film, the gate electrode, and the second interlayer insulating film and reaches the surface of the first conductive layer;
Coating the side wall surface of the contact hole with a gate insulating film;
Forming a second semiconductor layer on the substrate so as to be in contact with the surface of the first conductive layer and to be embedded in the contact hole;
Injecting a first conductivity type impurity into the surface of the second semiconductor layer;
The impurity implanted into the surface of the second semiconductor layer is diffused into the second semiconductor layer, and from the first conductive layer to the second semiconductor layer, in the first conductive layer. In the second semiconductor layer, the other region of the source / drain region and the storage node, the other of the source / drain region, and the source are diffused. Forming a channel region sandwiched between one of the / drain regions;
Forming a capacitor insulating film on the other of the source / drain regions;
Forming a cell plate on the storage node with the capacitor insulating film interposed therebetween;
A method for manufacturing a semiconductor device comprising:   2. The method of manufacturing a semiconductor device according to claim 1, further comprising: siliciding an outer surface of the gate electrode after forming the gate electrode and prior to forming the second interlayer insulating film.   The method further includes the step of silicidizing the surface of the first conductive layer after forming the first conductive layer that also becomes the bit line and prior to forming the first interlayer insulating film. 2. A method for manufacturing a semiconductor device according to 1.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the bit line is formed by forming a LOCOS oxide film between adjacent bit lines. The contact hole is formed by
Providing an opening in the second interlayer insulating film;
Covering the inner wall of the opening with an oxide film;
The method for manufacturing a semiconductor device according to claim 1, further comprising: forming a hole penetrating the gate electrode and the first interlayer insulating film using the oxide film as a mask.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the forming of the bit line is performed using a phase shift mask including a portion in which the phase is not shifted at all and a portion in which the phase is shifted by 180 °.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the forming of the word line is performed using a phase shift mask including a portion whose phase is not shifted at all and a portion whose phase is shifted by 180 °.   The contact hole is formed using a phase shift mask including a portion that does not shift the phase at all, a portion that shifts the phase by 90 °, a portion that shifts the phase by 180 °, and a portion that shifts the phase by 270 °. 2. A method for manufacturing a semiconductor device according to 1. The formation of the gate electrode
Depositing amorphous silicon on the first interlayer insulating film;
The method for manufacturing a semiconductor device according to claim 1, further comprising: solid-phase growing the amorphous silicon, and changing the amorphous silicon into polysilicon having a larger particle diameter. Forming an LDD portion between the bit line and the channel region;
Forming an LDD portion between the storage node and the channel region;
The method for manufacturing a semiconductor device according to claim 1, further comprising:   The method of manufacturing a semiconductor device according to claim 1, wherein the first conductivity type impurity includes phosphorus. After embedding a semiconductor layer in the contact hole,
2. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of implanting a second conductivity type impurity in the vicinity of the height position of the upper surface and the height position of the lower surface of the gate electrode.   2. The method of manufacturing a semiconductor device according to claim 1, further comprising forming irregularities on a surface of the storage node before forming the cell plate after forming the storage node. Forming an active region of a MOS transistor of a peripheral circuit simultaneously with the formation of the bit line;
Forming a gate insulating film of the MOS transistor on the active region;
Forming a gate electrode of a MOS transistor on the active region with the gate insulating film interposed therebetween;
Injecting the impurity into the active region of the MOS transistor simultaneously with injecting the impurity into the bit line, thereby forming a source / drain region of the MOS transistor;
The method for manufacturing a semiconductor device according to claim 1, further comprising siliciding the surface of the bit line, the gate electrode of the MOS transistor, and the surface of the source / drain region of the MOS transistor.

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