JP2013105841A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor substrate having an easy manufacturing process and high current driving capability, and to provide a manufacturing method thereof.SOLUTION: A semiconductor device comprises a semiconductor substrate. A Fin-type semiconductor layer of a first conductivity type is formed on the semiconductor substrate. A source layer of the first conductivity type and a drain layer of the first conductivity type are provided on both ends of the Fin-type semiconductor layer in a longitudinal direction. A gate insulating film is provided on both side surfaces of the Fin-type semiconductor layer. A gate electrode is provided on both the side surfaces of the Fin-type semiconductor layer via the gate insulating film. A punch through stopper layer of a second conductivity type is provided under the gate electrode and the Fin-type semiconductor layer. Dopant concentration of the punch trough stopper layer is higher than dopant concentration of the semiconductor substrate positioned under the source layer and the drain layer.

Description

  Embodiments described herein relate generally to a semiconductor device and a method for manufacturing the same.

  Conventionally, junctionless transistors have been developed. Junctionless transistors are excellent in current drive capability, but their characteristics vary between elements due to variations in the impurity concentration of the channel portion (Random-Dopant Fraction (RDF)) or variations in the thickness of the body portion (LEF). There is a problem.

  The Saddle-FinFET used for a DRAM cell transistor or the like is easier to manufacture than a normal FinFET. However, the Saddle-FinFET has a problem that only the upper part of the Fin channel contributes to conduction, so that the effective channel width is narrow and the current driving capability is disadvantageous.

  A Standard-FinFET used in Logic-LSI can obtain a high current drive capability, but has a problem that the manufacturing process is very complicated.

J.P.Colinge, “SOI gated resistor: CMOS without junctions”, SOI conference 2009 Makoto Yoshida, “Recessed Channel Fin Field Effect Transistor Cell technology for future generation dynamic random access memories”, Japanese Journal of Applied Physics 2008, pp. 2672-2675 A, Kaneko et. Al. “High-Performance FinFET with Dopant-Segregated Schottky Source / Drain, International Electron Devices Meeting, 2006. IEDM '06. Page (s): 893-896

  It is an object of the present invention to provide a semiconductor device having a simple manufacturing process and high current driving capability, and a manufacturing method thereof.

  The semiconductor device according to the present embodiment includes a semiconductor substrate. The first conductivity type Fin-type semiconductor layer is formed on the semiconductor substrate. The first conductivity type source layer and the first conductivity type drain layer are provided at both ends in the longitudinal direction of the Fin type semiconductor layer. The gate insulating film is provided on both side surfaces of the Fin type semiconductor layer. The gate electrode is provided on both side surfaces of the Fin-type semiconductor layer via a gate insulating film. The punch-through stopper layer of the second conductivity type is provided under the gate electrode and the Fin type semiconductor layer. The impurity concentration of the punch-through stopper layer is higher than the impurity concentration of the semiconductor substrate under the source layer and the drain layer.

FIG. 2 is a cross-sectional perspective view showing the configuration of the Fin-type FET according to the first embodiment. 1 is a cross-sectional perspective view illustrating a method for manufacturing a transistor according to a first embodiment. The cross-sectional perspective view which shows the manufacturing method following FIG. FIG. 4 is a cross-sectional perspective view illustrating the manufacturing method following FIG. 3. The cross-sectional perspective view which shows the manufacturing method following FIG. FIG. 6 is a cross-sectional perspective view illustrating the manufacturing method following FIG. 5. FIG. 7 is a cross-sectional perspective view illustrating the manufacturing method following FIG. 6. FIG. 6 is a cross-sectional perspective view showing a configuration of a Fin-type FET according to the second embodiment. FIG. 6 is a cross-sectional perspective view showing the configuration of a Fin-type FET according to the third embodiment. Sectional perspective view which shows the structure of Fin type FET according to 4th Embodiment.

  Embodiments according to the present invention will be described below with reference to the drawings. This embodiment does not limit the present invention.

(First embodiment)
1A and 1B are cross-sectional perspective views showing the configuration of a Fin-type FET (Field-Effect Transistor) according to the first embodiment. FIG. 1B is a diagram in which the structure on the semiconductor substrate 10 is omitted in order to show the Fin-type semiconductor layer 20.

  A Fin-type FET (hereinafter, also simply referred to as a transistor) includes a semiconductor substrate 10, an n-type (first conductivity type) Fin-type semiconductor layer 20, an n-type source layer S, an n-type drain layer D, A gate insulating film 30, a gate electrode G, and a p-type (second conductivity type) punch-through stopper layer 50 are provided.

  The semiconductor substrate 10 is p-type or has a p-type well. The semiconductor substrate 10 is provided with element isolation STI (Shallow Trench Isolation), and an active area AA is provided between the element isolation STIs. An n-type impurity is implanted into the surface of the active area AA. Therefore, as shown in FIG. 1B, the n-type impurity is similarly introduced into the source layer S, the drain layer D, and the Fin-type semiconductor layer 20.

  A Fin type semiconductor layer 20 shown in FIG. 1B is sandwiched between gate trenches TRg formed in the active area AA, and is defined by the gate trench TRg. The Fin-type semiconductor layer 20 is provided between the source layer S and the drain layer D and is provided on the semiconductor substrate 10. The Fin type semiconductor layer 20 functions as a channel portion of the transistor according to the present embodiment. The source layer S and the drain layer D are provided at both ends in the longitudinal direction (channel length direction) of the Fin type semiconductor layer 20 and are integrally formed with the Fin type semiconductor layer 20. Thereby, the mechanical strength of the Fin-type semiconductor layer 20 is reinforced.

  The gate insulating film 30 shown in FIG. 1A is provided on the inner surface of the gate trench TRg including both side surfaces of the Fin-type semiconductor layer 20. The gate electrode G is embedded in the gate trench TRg, and is provided on both side surfaces of the Fin-type semiconductor layer 20 via the gate insulating film 30. The gate electrode G extends in the width direction (channel width direction) of the Fin-type semiconductor layer 20 and is electrically connected to a wiring or a contact (not shown).

  The punch-through stopper layer 50 is provided under the bottom portion of the gate trench TRg (under the gate electrode G) and under the Fin type semiconductor layer 20. The concentration of the p-type impurity in the punch-through stopper layer 50 is higher than the concentration of the p-type impurity in the semiconductor substrate 10 (or well) under the source layer and the drain layer. In other words, the punch-through stopper layer 50 is locally provided under the gate electrode G and the Fin-type semiconductor layer 20, but is not provided under the source layer S and the drain layer D. Thereby, the punch-through stopper layer 50 can suppress punch-through between the source layer S and the drain layer D. Further, since the punch-through stopper layer 50 is not provided under the source layer S and the drain layer D, the junction capacitance (parasitic capacitance) between the drain layer D (or the source layer S) and the semiconductor substrate 10 is small. .

  The transistor according to the present embodiment further includes a SiN hard mask 60 provided on the gate electrode G, interlayer insulating films ILD1 and ILD2, and contact plugs PLG embedded in the interlayer insulating films ILD1 and ILD2. . The contact plug PLG is connected to the source layer S or the drain layer D through the interlayer insulating films ILD1 and ILD2.

  Since the transistor according to the present embodiment has a small junction capacitance between the drain layer D (or source layer S) and the semiconductor substrate 10, the punch-through stopper layer 50 is provided below the source layer S and the drain layer D. Compared with, switching speed is fast.

  The transistor according to the present embodiment does not have a pn junction between the source layer S and the Fin type semiconductor layer 20 as the channel portion and between the drain layer D and the Fin type semiconductor layer 20. That is, the transistor according to the present embodiment is a junctionless Fin-type FET. A gate electrode G is provided on the entire side surface of the Fin-type semiconductor layer 20. Accordingly, the junctionless and the entire Fin-type semiconductor layer 20 becomes a channel portion, so that bulk conduction is realized and high current driving capability can be obtained.

  Since the width of the Fin type semiconductor layer 20 is very narrow compared to the source layer S and the drain layer D, the short channel effect can be suppressed. Further, since the width of the source layer S and the drain layer D is wider than the width of the Fin-type semiconductor layer 20, the contact resistance of the source and drain can be reduced.

  In the present embodiment, as shown in FIG. 1B, the upper surface of the Fin-type semiconductor layer 20 is substantially flush with the upper surfaces of the source layer S and the drain layer D. This simplifies the manufacturing method, as will be described later.

2 to 7 are cross-sectional perspective views showing a method for manufacturing a transistor according to the first embodiment. First, as shown in FIG. 2, n-type impurities are introduced into the surface of the semiconductor substrate 10 to form the n-type semiconductor layer 11. The semiconductor substrate 10 is, for example, a bulk silicon substrate. The n-type impurity is, for example, phosphorus or arsenic. The impurity concentration of the n-type semiconductor layer 11 is, for example, 1E20 cm ⁻³ .

  Next, a first mask 13 is formed on the surface of the semiconductor substrate 10 so as to cover the active area AA. The first mask 13 is formed using, for example, a silicon nitride film having a thickness of about 70 nm. The semiconductor substrate 10 is etched by RIE (Reactive Ion Etching) using the first mask 13 as a mask. Thereby, an isolation trench TRsti for STI is formed in the element isolation region. Next, the element isolation STI is formed by filling the isolation trench TRsti with an insulating material (for example, a silicon oxide film). Thereby, the structure shown in FIG. 3 is obtained. The width of the active area AA surrounded by the element isolation STI is, for example, about 40 nm. The n-type semiconductor layer 11 may be formed after the element isolation STI is formed.

Next, the first mask 13 is isotropically etched back by about 15 nm using hot phosphoric acid to leave a part of the first mask 13 at the center of the active area AA as shown in FIG. . Hereinafter, the remaining part of the first mask 13 is referred to as a first mask 14 for convenience. Note that lithography technique and RIE may be used when the first mask 13 is etched. The width of the first mask 14 after etching (width in the channel width direction) is substantially equal to the width (channel width) of the Fin-type semiconductor layer 20. The length of the first mask 14 (the length in the channel length direction) is longer than the length between the source layer S and the drain layer D (channel length).

  Next, as shown in FIG. 5, the second mask 15 is formed so as to cover the regions of the source layer S and the drain layer D on both sides in the longitudinal direction of the first mask 14. An interval between the source layer S and the drain layer D is, for example, about 30 nm. The second mask 15 is formed of a material that can be selectively etched with respect to the first mask 14. The second mask 15 is formed using, for example, a silicon oxide film. Thus, the second mask 15 can be processed while maintaining the first mask 14. The second mask 15 is left as an interlayer insulating film ILD1 after completion.

  Next, as shown in FIG. 6, using the first and second masks 14 and 15 as masks, the semiconductor substrate 10 is etched by RIE to form a gate trench TRg. The depth of the gate trench TRg from the surface of the semiconductor substrate 10 is, for example, about 200 nm, and the width thereof is, for example, about 30 nm. As a result, the Fin-type semiconductor layer 20 can be formed under the first mask 14, and the source layer S and the drain layer D can be formed under the second mask 15. At this time, the Fin-type semiconductor layer 20, the source layer S, and the drain layer D are simultaneously formed in the same etching process. Therefore, the Fin-type semiconductor layer 20, the source layer S, and the drain layer D can be easily formed integrally. That is, since the Fin-type semiconductor layer 20, the source layer S, and the drain layer D are integrally formed of the same n-type semiconductor layer, the upper surface of the Fin-type semiconductor layer 20 is flush with the upper surfaces of the source layer S and the drain layer D. Become one. The height of the Fin-type semiconductor layer 20 is, for example, about 200 nm, and the width is about 10-15 nm.

Next, using the first and second masks 14 and 15 as masks as they are, p-type impurities are implanted under the bottom of the gate trench TRg and under the Fin type semiconductor layer 20. The p-type impurity is, for example, boron, and the concentration thereof is, for example, about 5E13 cm ⁻² . Thereby, the punch-through stopper layer 50 is not formed under the source layer S and the drain layer D, but can be locally formed under the bottom of the gate trench TRg and the Fin-type semiconductor layer 20. A part of the impurity ions is also diffused under the Fin type semiconductor layer 20 by lateral recoil and thermal diffusion from the bottom of the gate trench TRg. Therefore, the punch-through stopper layer 50 is also formed below the Fin type semiconductor layer 20.

  Next, as shown in FIG. 7, a gate insulating film 30 is formed on the inner wall of the gate trench TRg. The gate insulating film 30 is formed using, for example, a silicon oxide film or a high dielectric material having a dielectric constant higher than that of the silicon oxide film. The film thickness of the gate insulating film 30 is about 2 nm, for example.

  Next, the material of the gate electrode G is filled in the gate trench TRg. The material of the gate electrode G is, for example, a laminated film of tungsten and TiN. Then, the material of the gate electrode G is etched back so that the height of the upper surface of the gate electrode G is lower than the upper surface of the second mask 15 by, for example, about 30 nm.

  Next, the material of the hard mask 60 is deposited, and the material of the hard mask 60 is polished using CMP (Chemical Mechanical Polishing) until the second mask 15 is exposed. The material of the hard mask 60 is formed using, for example, a silicon nitride film. Thereby, the hard mask 60 that protects the gate electrode G is formed in a self-aligning manner. The hard mask 60 protects the gate electrode G when forming the contact plug PLG, and prevents a short circuit between the gate electrode G and the source side contact PLG (or the drain side contact PLG).

  Thereafter, an interlayer insulating film ILD2 is deposited. Contact holes reaching the source layer S and the drain layer D are formed in the interlayer insulating film ILD2, and are filled with contact plugs PLG. Further, the transistor according to the present embodiment is completed by forming an interlayer insulating film, wiring, and the like (not shown).

  The transistor according to the present embodiment is a junctionless transistor, has no PN junction between the source layer S and the Fin-type semiconductor layer 20 and between the drain layer D and the Fin-type semiconductor layer 20, and has an impurity concentration difference. There is no. Therefore, the impurity concentrations of the source layer S, the drain layer D, and the Fin type semiconductor layer 20 can be determined by the same impurity implantation process.

  In the transistor according to the present embodiment, the source layer S, the drain layer D, and the Fin type semiconductor layer 20 are integrally formed, and their upper surfaces are formed flush with each other. Therefore, the source layer S, the drain layer D, and the Fin type semiconductor layer 20 can be simultaneously formed by the process of forming the gate trench TRg. Furthermore, the punch-through stopper layer 50 can be locally formed under the Fin trench semiconductor layer 20 and the bottom of the gate trench TRg by using the gate trench TRg and the masks 14 and 15. That is, the gate trench TRg is used not only for processing the source layer S, the drain layer D, and the Fin type semiconductor layer 20, but also for forming the punch-through stopper layer 50. As a result, a junctionless Fin-type FET having a high current driving capability and a high switching speed can be easily manufactured.

  Since the source layer S, the drain layer D, and the Fin type semiconductor layer 20 are integrally formed, a transistor can be manufactured while maintaining the mechanical strength of the narrow Fin type semiconductor layer 20. Since the width of the source layer S and the drain layer D is wider than the width of the Fin-type semiconductor layer 20, the manufacture is facilitated.

  The transistor according to the present embodiment can be manufactured using a bulk substrate, and it is not necessary to use processes such as an epitaxial process, oblique ion implantation, and plasma doping for forming a source / drain. Therefore, the manufacturing process is simple and the manufacturing cost is low.

(Second Embodiment)
FIG. 8 is a cross-sectional perspective view showing the configuration of the Fin-type FET according to the second embodiment. A cross-sectional perspective view in which the gate electrode G and the gate insulating film 30 are omitted is the same as that in FIG.

  In the second embodiment, the gate electrode G is configured as poly-metal gates Gp and Gm. The poly gate electrode Gp is formed using doped polysilicon having a thickness of 150 nm, for example. The metal gate electrode Gm provided on the polysilicon gate electrode Gp is formed using, for example, a laminated film of a TiN / Ti film having a thickness of 10 nm and a tungsten film having a thickness of 70 nm.

  Furthermore, the transistor according to the second embodiment further includes a hard mask 80 provided on the metal gate electrode Gm and a sidewall film 90 provided on the side surface of the gate electrode G. The hard mask 80 and the sidewall film 90 are formed using, for example, a silicon nitride film. The hard mask 80 and the sidewall film 90 are provided to protect the gate electrode G when forming contact plugs connected to the source layer S and the drain layer D. Note that only the outer edge of the sidewall film 90 is shown for convenience.

  An interlayer insulating film (not shown) is provided so as to cover hard mask 80 and sidewall film 90, and a contact plug (not shown) is formed in the interlayer insulating film.

  Other configurations of the transistor according to the second embodiment may be the same as the corresponding configurations in the first embodiment. Therefore, the second embodiment can obtain the same effects as those of the first embodiment.

  In the transistor according to the second embodiment, the polysilicon gate electrode Gp is filled in the gate trench TRg. Therefore, it is not necessary to embed metal in the gate trench TRg, and it is not necessary to use the damascene method. That is, when processing the gate electrode G, lithography technology and etching technology such as RIE can be used. However, in the lithography process of the gate electrode G, it is necessary to align the photomask in accordance with the gate trench TRg. Other manufacturing steps of the transistor according to the second embodiment may be the same as the corresponding manufacturing steps of the first embodiment. Therefore, the manufacturing method according to the second embodiment can obtain the same effects as the manufacturing method according to the first embodiment.

(Third embodiment)
FIG. 9A and FIG. 9B are cross-sectional perspective views showing the configuration of the Fin-type FET according to the third embodiment. In FIG. 9A, for convenience, the interlayer insulating film ILD2 is shown only by its outer edge. FIG. 9B is a diagram in which the structure on the semiconductor substrate 10 is omitted in order to show the Fin-type semiconductor layer 20.

  In the third embodiment, the upper surface of the Fin-type semiconductor layer 20 is lower than the upper surfaces of the source layer S and the drain layer D. The upper surface of the gate electrode G is substantially flush with or lower than the upper surfaces of the source layer S and the drain layer D and higher than the upper surface of the Fin-type semiconductor layer 20. By making the Fin-type semiconductor layer 20 lower than the source layer S and the drain layer D, even if the height of the gate electrode G is equal to or less than the height of the source layer S and the drain layer D, the gate electrode G It is not divided by the semiconductor layer 20 and can be connected in the gate trench TRg.

  Since the upper surface of the gate electrode G is substantially flush with or lower than the upper surfaces of the source layer S and the drain layer D, the distance between the contact plug PLG and the gate electrode G is increased. Thereby, the parasitic capacitance between the contact plug PLG and the gate electrode G can be reduced. Furthermore, the process margin between the contact plug PLG and the gate electrode G can be improved, and a short circuit between them can be suppressed.

  As long as the gate electrode G is connected in the gate trench TRg, the upper surface of the gate electrode G may be lower than the upper surfaces of the source layer S and the drain layer D. That is, the upper surface of the gate electrode G may be higher than the upper surface of the Fin-type semiconductor layer 20 and may be at a position below the upper surfaces of the source layer S and the drain layer D.

  The upper surface of the hard mask 60 is substantially flush with the upper surface of the interlayer insulating film ILD1. Thereby, the hard mask 60 covers the gate electrode G.

  Other configurations of the transistor according to the third embodiment may be the same as the corresponding configurations in the first embodiment. Therefore, the third embodiment can also obtain the effects of the first embodiment.

  A method for manufacturing a transistor according to the third embodiment will be described. After the steps shown in FIGS. 2 to 5, the gate trench TRg and the punch-through stopper layer 50 are formed as shown in FIG.

  Next, the first mask 14 is removed using RIE, and the upper surface of the Fin-type semiconductor layer 20 is exposed. Next, the upper part of the Fin type semiconductor layer 20 is etched by RIE using the second mask 15 as a mask. Thereby, the Fin type semiconductor layer 20 becomes lower than the source layer S and the drain layer D. For example, the Fin-type semiconductor layer 20 is approximately 70 nm lower than the source layer S and the drain layer D.

  Next, after forming the gate insulating film 30, the material of the gate electrode G is filled in the gate trench TRg. The material of the gate electrode G is, for example, a laminated film of TiN having a thickness of 10 nm and tungsten having a thickness of 150 nm. Next, the material of the gate electrode G is etched back. As a result, the gate electrode G is formed at the same height as or lower than the source layer S and the drain layer D. For example, the upper surface of the gate electrode G is about 0 to 30 nm lower than the upper surfaces of the source layer S and the drain layer D.

  Next, the material of the hard mask 60 is deposited, and the material of the hard mask 60 is polished using CMP until the second mask 15 is exposed. The second mask 15 and the hard mask 60 may be further polished to a desired thickness. For example, in the third embodiment, the second mask 15 and the hard mask 60 may be polished until the second mask 15 has a thickness of about 30 nm. The material of the hard mask 60 is formed using, for example, a silicon nitride film. Thereby, the hard mask 60 that protects the gate electrode G is formed in a self-aligning manner. The hard mask 60 protects the gate electrode G when forming the contact plug PLG, and prevents a short circuit between the gate electrode G and the source side contact PLG (or the drain side contact PLG).

  Thereafter, similar to the manufacturing method according to the first embodiment, the interlayer insulating film ILD2, the contact plug PLG, the interlayer insulating film, the wiring, and the like (not shown) are formed, thereby completing the transistor.

  According to the third embodiment, the gate electrode G is provided at a position equal to or lower than the surface of the semiconductor substrate 10. Accordingly, the process margin of the contact plug PLG is improved (the alignment margin is reduced), and the manufacture of the contact plug PLG is facilitated. The third embodiment can also obtain the effects of the first embodiment.

(Fourth embodiment)
FIG. 10 is a cross-sectional perspective view showing the configuration of the Fin-type FET according to the fourth embodiment. In the fourth embodiment, the impurity concentration of the Fin-type semiconductor layer 20 is lower than the impurity concentration of the source layer S and the drain layer D. That is, the n-type impurity concentration of the Fin-type semiconductor layer 20 is, for example, 2E19 cm ^{−3 to} 5E19 cm ⁻³ . Therefore, the n-type impurity concentration of the Fin-type semiconductor layer 20 is lower than the n-type impurity concentration (for example, 1E20 cm ⁻³ ) of the source layer S and the drain layer D. Thereby, the variation (RDF) of the impurity concentration in the channel portion can be suppressed.

  Other configurations of the transistor according to the fourth embodiment may be the same as the corresponding configurations in the first embodiment. Therefore, the fourth embodiment can also obtain the effect of the first embodiment.

A method for manufacturing a transistor according to the fourth embodiment will be described. After the steps shown in FIGS. 2 to 5, the gate trench TRg and the punch-through stopper layer 50 are formed as shown in FIG.

  Next, p-type impurities are implanted into the Fin-type semiconductor layer 20 from an oblique direction. Thereby, the n-type impurity concentration of the Fin-type semiconductor layer 20 is lower than the n-type impurity concentration of the source layer S and the drain layer D. The subsequent manufacturing process may be the same as the manufacturing process according to the first embodiment.

  The fourth embodiment can be combined with the second embodiment or the third embodiment.

  The Fin-type FETs according to the first to fourth embodiments can be applied to peripheral circuit transistors of DRAM and MRAM, and cell transistors of DRAM and MRAM memory cells.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are also included in the invention described in the claims and the equivalents thereof.

DESCRIPTION OF SYMBOLS 10 ... Semiconductor substrate, 13, 14 ... 1st mask, 15 ... 2nd mask, 20 ... Fin type semiconductor layer, 30 ... Gate insulating film, 50 ... Punch through Stopper layer, 60 ... hard mask, STI ... element isolation, AA ... active area, S ... source layer, D ... drain layer, G ... gate electrode, ILD1, ILD2, ... Interlayer insulating film, PLG ... contact plug, TRg ... gate trench,

Claims (8)

A semiconductor substrate;
A first conductivity type Fin-type semiconductor layer formed on the semiconductor substrate;
A first conductivity type source layer and a first conductivity type drain layer provided at both ends in the longitudinal direction of the Fin type semiconductor layer;
Gate insulating films provided on both side surfaces of the Fin-type semiconductor layer;
A gate electrode provided on both side surfaces of the Fin-type semiconductor layer via the gate insulating film;
A second conductivity type punch-through stopper layer provided under the gate electrode and the Fin-type semiconductor layer;
A gate trench provided between the source layer and the drain layer and defining the Fin-type semiconductor layer;
The gate electrode is embedded in the gate trench;
The punch-through stopper layer is provided on the semiconductor substrate at the bottom of the gate trench,
The semiconductor device according to claim 1, wherein an impurity concentration of the punch-through stopper layer is higher than an impurity concentration of the semiconductor substrate under the source layer and the drain layer. A semiconductor substrate;
A first conductivity type Fin-type semiconductor layer formed on the semiconductor substrate;
A first conductivity type source layer and a first conductivity type drain layer provided at both ends in the longitudinal direction of the Fin type semiconductor layer;
Gate insulating films provided on both side surfaces of the Fin-type semiconductor layer;
A gate electrode provided on both side surfaces of the Fin-type semiconductor layer via the gate insulating film;
A punch-through stopper layer of a second conductivity type provided under the gate electrode and the Fin type semiconductor layer;
The semiconductor device according to claim 1, wherein an impurity concentration of the punch-through stopper layer is higher than an impurity concentration of the semiconductor substrate under the source layer and the drain layer. A gate trench provided between the source layer and the drain layer and defining the Fin-type semiconductor layer;
The gate electrode is embedded in the gate trench;
The semiconductor device according to claim 2, wherein the punch-through stopper layer is provided on the semiconductor substrate at the bottom of the gate trench.   4. The semiconductor device according to claim 2, wherein a width of the source layer and the drain layer is wider than a width of the Fin-type semiconductor layer. 5.   5. The semiconductor device according to claim 2, wherein an upper surface of the Fin-type semiconductor layer is substantially flush with upper surfaces of the source layer and the drain layer. The height of the upper surface of the Fin-type semiconductor layer is lower than the upper surfaces of the source layer and the drain layer,
The height of the upper surface of the gate electrode is substantially the same as or lower than the upper surfaces of the source layer and the drain layer, and is higher than the upper surface of the Fin-type semiconductor layer. 6. The semiconductor device according to any one of items 5.   The semiconductor device according to claim 2, wherein an impurity concentration of the Fin-type semiconductor layer is lower than an impurity concentration of the source layer and the drain layer. Introducing a first conductivity type impurity into the surface of the semiconductor substrate;
Forming a first mask covering an active area on a surface of the semiconductor substrate;
Forming an isolation trench in an element isolation region using the first mask as a mask;
Filling the isolation trench with an insulating material to form element isolation,
Leaving a portion of the first mask over the active area by etching the first mask;
Forming a second mask so as to cover the source layer and the drain layer formed on both sides in the longitudinal direction of the first mask after the etching;
The semiconductor substrate is etched using the first and second masks as a mask to form a gate trench, thereby forming a Fin-type semiconductor layer under the first mask, and the second Forming the source layer and the drain layer under the mask of
Using the first and second masks as masks, a second conductivity type impurity is implanted under the bottom of the gate trench and under the Fin type semiconductor layer to form a punch-through stopper layer,
Forming a gate insulating film on the inner wall of the gate trench;
Filling the gate trench with a gate electrode;
A method of manufacturing a semiconductor device, wherein an impurity concentration of the punch-through stopper layer is higher than an impurity concentration of the semiconductor substrate under the source layer and the drain layer.

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