US7719056B2 - Semiconductor memory device having a floating body and a plate electrode - Google Patents

Semiconductor memory device having a floating body and a plate electrode Download PDF

Info

Publication number
US7719056B2
US7719056B2 US11/687,131 US68713107A US7719056B2 US 7719056 B2 US7719056 B2 US 7719056B2 US 68713107 A US68713107 A US 68713107A US 7719056 B2 US7719056 B2 US 7719056B2
Authority
US
United States
Prior art keywords
source
floating body
region
memory device
drain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active, expires
Application number
US11/687,131
Other versions
US20080032474A1 (en
Inventor
Takeshi Hamamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kioxia Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Assigned to KABUSHIKI KAISHA TOSHIBA reassignment KABUSHIKI KAISHA TOSHIBA ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HAMAMOTO, TAKESHI
Publication of US20080032474A1 publication Critical patent/US20080032474A1/en
Application granted granted Critical
Publication of US7719056B2 publication Critical patent/US7719056B2/en
Assigned to TOSHIBA MEMORY CORPORATION reassignment TOSHIBA MEMORY CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KABUSHIKI KAISHA TOSHIBA
Assigned to TOSHIBA MEMORY CORPORATION reassignment TOSHIBA MEMORY CORPORATION CHANGE OF NAME AND ADDRESS Assignors: K.K. PANGEA
Assigned to KIOXIA CORPORATION reassignment KIOXIA CORPORATION CHANGE OF NAME AND ADDRESS Assignors: TOSHIBA MEMORY CORPORATION
Assigned to K.K. PANGEA reassignment K.K. PANGEA MERGER (SEE DOCUMENT FOR DETAILS). Assignors: TOSHIBA MEMORY CORPORATION
Active legal-status Critical Current
Adjusted expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/764—Air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7841—Field effect transistors with field effect produced by an insulated gate with floating body, e.g. programmable transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/20—DRAM devices comprising floating-body transistors, e.g. floating-body cells

Definitions

  • the present invention relates to a semiconductor memory device and a method of manufacturing a semiconductor memory device.
  • FBC Floating Body Cell
  • DRAM Dynamic Random Access Memory
  • 1T Transistor
  • 1C Capacitor type memory cells
  • Patent document 1 The FBC can dispense with the capacitor essential to an ordinary DRAM cell, so that the memory cell structure of the FBC memory device is simpler than that of the DRAM cell.
  • the FBC is, therefore, advantageously easier to manufacture than the DRAM cell.
  • the FBC is constituted by a MISFET (Metal Insulator Semiconductor Field Effect Transistor) formed on an SOI (Silicon On Insulator) substrate.
  • the SOI substrate is more expensive than an ordinary bulk-silicon substrate. Due to this, the manufacturing cost of the FBC is disadvantageously higher than the DRAM cell.
  • design environment e.g., SPICE MODEL
  • SPICE MODEL SPICE MODEL
  • high breakdown-voltage transistor characteristics and ESD (Electrostatic Discharge) characteristics of an input/output circuit or the like are often, disadvantageously deteriorated in the LSI region other than the memory region.
  • a method of manufacturing a semiconductor memory device comprises forming a plurality of trenches in a semiconductor substrate; forming a semiconductor layer provided on a cavity by connecting lower spaces of the trenches to one another and closing upper openings of the trenches in a heat treatment under a hydrogen atmosphere; etching the semiconductor layer in an isolation formation area; forming an insulating film on a side surface and a bottom surface of the semiconductor layer; filling the cavity under the semiconductor layer with an electrode material; and forming a memory element on the semiconductor layer.
  • a semiconductor memory device comprises a semiconductor substrate; a source and a drain formed in a surface region of the semiconductor substrate; a support column provided below the source and intervening between the source and the semiconductor substrate; a floating body provided between the source and the drain and accumulating or releasing charges to store data; a gate insulating film provided on the floating body; a gate electrode provided on the gate insulating film; and a plate electrode provided below the drain and the floating body, and electrically isolated from the floating body and the semiconductor substrate, wherein the drain and the floating body are electrically isolated from the semiconductor substrate by the plate electrode.
  • FIGS. 1 to 14B are cross-sections or plan views showing a method of manufacturing an FBC memory according to a first embodiment of the present invention.
  • FIGS. 15 to 28 are cross-sections or plan views showing a method of manufacturing an FBC memory device according to the second embodiment.
  • FIGS. 1 to 14B are cross-sections or plan views showing a method of manufacturing an FBC memory according to a first embodiment of the present invention.
  • a structure shown in FIGS. 1 to 14B is the memory cell structure of the FBC memory in a memory region.
  • a logic region (“LSI region”) other than the memory region is formed on an ordinary bulk-silicon substrate and not formed on an SON (Silicon On Nothing) structure or an SOI structure (to be described later). Due to this, the logic region is not shown in FIGS. 1 to 14A , except for FIGS. 4C and 14B .
  • FIGS. 1 , 3 , 5 , 7 , 9 , 11 , and 13 are plan views showing steps of the method of manufacturing the FBC memory device according to the first embodiment.
  • FIGS. 1 , 3 , 5 , 7 , 9 , 11 , and 13 are plan views showing steps of the method of manufacturing the FBC memory device according to the first embodiment.
  • FIGS. 2A , 4 A, 6 A, 8 A, 10 A, 12 A, and 14 A are cross-sections taken along lines A-A of FIGS. 1 , 3 , 5 , 7 , 9 , 11 , and 13 , respectively.
  • FIGS. 2B , 4 B, 6 B, 8 B, 10 B, and 12 B are cross-sections taken along lines B-B of FIGS. 1 , 3 , 5 , 7 , 9 , and 11 , respectively.
  • a silicon nitride film used as a hard mask 21 is first deposited on a bulk-silicon substrate 10 serving as a semiconductor substrate.
  • a plurality of openings are formed in the hard mask 21 using lithography and RIE (Reactive Ion Etching).
  • the bulk-silicon substrate 10 is etched by the RIE.
  • a plurality of trenches 22 is formed in the bulk-silicon substrate 10 as shown in FIGS. 1 , 2 A, and 2 B.
  • the trenches 22 are formed equidistantly in a matrix.
  • Each of the trenches 22 has an opening diameter of, for example, 0.5 ⁇ m and a depth of, for example, 1.0 ⁇ m.
  • the distance between the two adjacent trenches 22 is, for example, 0.5 ⁇ m. That is, the opening diameters of the trenches 22 are respectively almost equal to distances between two adjacent trenches of the trenches 22 .
  • the depths of the trenches 22 are twice as large as the opening diameters of the trenches 22 .
  • the bulk-silicon substrate 10 is subjected to a heat treatment in hydrogen atmosphere.
  • the heat treatment is performed, for example, at an atmospheric pressure of 300 Torr for about three minutes under the hydrogen atmosphere at 1000° C.
  • upper openings of the respective trenches 22 are closed as shown in FIG. 3 .
  • lower spaces of the trenches 22 are connected to one another. Accordingly, a cavity 25 is provided on the bulk-silicon substrate 10 , and a silicon layer 26 serving as a semiconductor layer is formed on the cavity 25 .
  • the structure shown in FIGS. 4A and 4B is so-called silicon on nothing (SON) structure. Namely, by performing the heat treatment under the hydrogen atmosphere, the SON structure can be formed in the memory region while maintaining the state of the bulk-silicon substrate 10 in the logic region (See FIG. 4C ).
  • the heat treatment under the hydrogen atmosphere causes silicon on the surface of each trench 22 to flow to thereby minimize surface energy, and deforms the inner space of the trench 22 into a spherical shape.
  • the upper openings of the trenches 22 are gradually closed, thereby eventually forming the silicon layer 26 .
  • the inner spaces of the adjacent trenches 22 are connected to one another, whereby the cavity 25 is formed.
  • the silicon layer 26 is supported by the boundary with the bulk-silicon substrate around the silicon layer.
  • a silicon nitride film to be used as a hard mask 27 is deposited.
  • the silicon nitride film is patterned into a line-space shape by the lithography and the RIE so as to cover up active areas AA.
  • the silicon layer 26 in element-isolation formation areas IA is etched into the line-space shape by the RIE.
  • the cavity 25 is communicated with the outside in the element-isolation formation areas IA as shown in FIG. 6B .
  • the bulk-silicon substrate 10 is then oxidized.
  • the cavity 25 is communicated with the outside through the element-isolation formation areas IA. Due to this, as shown in FIGS. 8A and 8B , the interior of the cavity 25 and the surface of the silicon layer 26 are oxidized. Accordingly, a silicon oxide film 30 is formed on the side surface of the silicon layer 26 , the bottom of the silicon layer 26 , and the bottom of the cavity 25 .
  • the thickness of the silicon oxide film 30 is, for example, 10 nm.
  • a polysilicon layer 31 is deposited as an electrode material using CVD (Chemical Vapor Deposition). As a result, the cavity 25 is filled with the polysilicon layer 31 as shown in FIGS. 7 , 8 A, and 8 B. The polysilicon layer 31 filled up in the cavity 25 is used as a plate electrode.
  • CVD Chemical Vapor Deposition
  • the polysilicon layer 31 is etched back, thereby removing the polysilicon layer 31 located at higher level than the surface level of the silicon layer 26 as shown in FIGS. 10A and 10B .
  • the polysilicon layer 31 filled up in the cavity 25 and in the element-isolation formation areas IA is left unremoved.
  • the exposed surface of the polysilicon layer 31 in the element-isolation formation areas IA is oxidized.
  • a silicon oxide film 32 serving as an element-isolation layer is formed in the element-isolation formation areas IA as shown in FIGS. 9 and 10B .
  • a gate insulating film 35 is then formed on the silicon layer 26 .
  • Polysilicon is deposited subsequently to formation of the gate insulating film 35 , and the polysilicon is patterned by the lithography and the RIE, thereby forming a gate electrode 36 as shown in FIGS. 11 , 12 A, and 12 B.
  • LDD Lightly Diffused Drain
  • Metal e.g., nickel
  • a silicide layer 39 is formed on the source/drain diffusion layers 38 and a silicide layer 40 is formed on the gate electrode 36 .
  • an interlayer insulating film 42 , contacts 43 , source lines SL, and bit lines BL are formed as shown in FIGS. 13 and 14 .
  • wirings are formed in the logic region, as shown in FIG. 14B .
  • the FBC memory is formed.
  • the gate electrode 36 acts as a word line WL and that the polysilicon layer 31 acts as the plate electrode.
  • a floating body FB present under the word line WL (gate electrode 36 ) is surrounded by the source/drain diffusion layers 38 , the gate insulating film 35 , the silicon oxide film 30 , and the element isolation layer 32 .
  • the floating body FB is, therefore, in an electrically floating state.
  • Impact ionization occurs to the boundary between the drain diffusion layer and the floating body FB when potential is applied to the word line WL and the bit line BL. Charges generated by the impact ionization are accumulated in the floating body FB. If the FBC is, for example, an n-type FET, holes are accumulated in the floating body FB. Electrons generated by the impact ionization are discharged to the drain diffusion layer 38 .
  • the FBC stores therein data “0” or “1” according to the number of majority carriers accumulated in the floating body FB.
  • the FBC memory having the SOI structure can be formed using the bulk-silicon substrate 10 . Therefore, the FBC memory can be manufactured at low cost with the manufacturing method according to the first embodiment.
  • the FBC memory can be formed on the SOI substrate whereas the LSI circuit in the logic region can be directly formed on the ordinary bulk-silicon substrate 10 . Therefore, it is possible to improve only the characteristics of the FBC memory without influencing the surrounding logic region. As a consequence, the existing design environment can be applied to the logic region. This can enhance design-development efficiency for the semiconductor memory device.
  • the LSI circuit in the logic region is directly formed on the bulk-silicon substrate 10 .
  • the LSI circuit formed on the bulk-silicon substrate 10 is superior to that formed on the SOI substrate in breakdown characteristics and ESD characteristics.
  • the semiconductor memory device according to the first embodiment can be applied as a device which requires high breakdown voltage such as an input/output circuit.
  • the thickness of the silicon oxide film 30 between the polysilicon layer 31 serving as the plate electrode and the floating body FB is 10 nm. If the silicon oxide film 30 is thinner, a signal difference (potential difference between the data “0” and the data “1”) is larger in data read operation. Furthermore, if the silicon oxide film 30 is thinner, then the charge-retention characteristics in the floating body FB are improved and more stable operation of the FBC memory can be ensured. If a charge-retention time is longer, the frequency of refresh operations can be made lower, thereby realizing high-rate operation and low power consumption. In view of the characteristics of the FBC memory, therefore, it is preferable that the silicon oxide film 30 is thinner.
  • a BOX (Buried Oxide) layer in the logic region is made thinner while the SOI substrate, for example, is used, parasitic capacity between the substrate and a channel region becomes higher. This may possibly deteriorate the performance of the FBC.
  • the plate electrode is formed only in the memory region, and the surrounding logic circuit is formed on the bulk-silicon substrate 10 . It is, therefore, possible to stabilize the operation of the FBC memory without influencing the surrounding logic circuit according to the first embodiment.
  • the entire memory region has the SOI structure.
  • the source region of the memory cell is provided on the bulk-silicon substrate, the characteristics of the FBC memory are not deteriorated.
  • a source diffusion layer is formed on a bulk-silicon substrate.
  • FIGS. 15 to 28 are cross-sections or plan views showing a method of manufacturing an FBC memory device according to the second embodiment.
  • a structure shown in FIGS. 15 to 28 is the memory cell structure of the FBC memory in a memory region, and a logic region other than the memory region is not shown in FIGS. 15 to 28 .
  • the SOI structure is not provided in the logic region, and an LSI circuit in a logic region is formed on an ordinary bulk-silicon substrate.
  • FIGS. 15 , 17 , 19 , 21 , 23 , 25 and 27 are plan views showing steps of the method of manufacturing the FBC memory device according to the second embodiment.
  • FIGS. 16A , 18 A, 20 A, 22 A, 24 A, 26 A, and 28 are cross-sections taken along lines A-A of FIGS. 15 , 17 , 19 , 21 , 23 , 25 , and 27 , respectively.
  • FIGS. 16B , 18 B, 20 B, 22 B, 24 B, and 26 B are cross-sections taken along lines B-B of FIGS. 15 , 17 , 19 , 21 , 23 , and 25 , respectively.
  • a silicon nitride film used as a hard mask 21 is first deposited on a bulk-silicon substrate 10 serving as a semiconductor substrate.
  • a plurality of openings is formed in the hard mask 21 using the lithography and the RIE. At this moment, the openings are formed equidistantly in a matrix in the first embodiment. However, no openings are formed in a source formation region of the memory region in the second embodiment.
  • the bulk-silicon substrate 10 is etched by the RIE. As a result, a plurality of trenches 22 is formed in the bulk-silicon substrate 10 as shown in FIGS. 15 , 16 A, and 16 B.
  • Each of the trenches 22 has an opening diameter of, for example, 0.5 ⁇ m and a depth of, for example, 1.0 ⁇ m.
  • the distance between the two adjacent trenches 22 is, for example, 0.5 ⁇ m.
  • the distance between the two adjacent trenches 22 is twice or more as large as the opening diameter.
  • the distance between the two adjacent trenches 22 in the source formation region is, for example, equal to or larger than 1 ⁇ m.
  • the bulk-silicon substrate 10 is subjected to a heat treatment in hydrogen atmosphere.
  • the heat treatment is performed, for example, at an atmospheric pressure of 300 Torr for about three minutes under the hydrogen atmosphere at 1100° C.
  • upper openings of the respective trenches 22 are closed as shown in FIG. 17 .
  • lower spaces of the trenches 22 are connected to one another. Accordingly, a cavity 25 is provided on the bulk-silicon substrate 10 , and a silicon layer 26 serving as a semiconductor layer is formed on the cavity 25 .
  • the state of the bulk-silicon substrate 10 is maintained similarly to the logic region.
  • a supporting column 50 made of silicon is formed in the source formation region. Parts of the memory region other than the source formation region are formed to have the SON structure.
  • the silicon layer 26 is supported not only by the boundary between the memory region and the logic region but also by the supporting column 50 . It is, therefore, possible to maintain the mechanical strength of the silicon layer 26 , and prevent the silicon layer 26 from being caved in the cavity 25 .
  • a silicon nitride film to be used as a hard mask 27 is deposited.
  • the silicon nitride film is patterned into a line-space shape by the lithography and the RIE so as to cover up active areas AA.
  • the silicon layer 26 in isolation formation areas IA is etched into the line-space shape by the RIE.
  • the cavity 25 is communicated with the outside in the isolation formation areas IA as shown in FIG. 20B .
  • the bulk-silicon substrate 10 is then oxidized.
  • the cavity 25 is communicated with the outside through the isolation formation areas IA. Due to this, as shown in FIGS. 22A and 22B , the interior of the cavity 25 and the surface of the silicon layer 26 are oxidized. Accordingly, a silicon oxide film 30 is formed on the side surface of the silicon layer 26 , the bottom of the silicon layer 26 , and the bottom of the cavity 25 .
  • the thickness of the silicon oxide film 30 is, for example, 10 nm.
  • a polysilicon layer 31 is deposited as an electrode material using the CVD. As a result, the cavity 25 is filled with the polysilicon layer 31 as shown in FIGS. 21 , 22 A, and 22 B. The polysilicon layer 31 filled up in the cavity 25 is used as a plate electrode.
  • the polysilicon layer 31 is etched back, thereby removing the polysilicon layer 31 located at higher level than the surface level of the silicon layer 26 as shown in FIGS. 24A and 24B .
  • the polysilicon layer 31 filled up in the cavity 25 and in the isolation formation areas IA is left unremoved.
  • the exposed surface of the polysilicon layer 31 in the isolation formation areas IA is oxidized.
  • a silicon oxide film 32 serving as an element-isolation layer is formed in the isolation formation areas IA as shown in FIGS. 23 and 24B .
  • a gate insulating film 35 is then formed on the silicon layer 26 .
  • Polysilicon is deposited subsequently to formation of the gate insulating film 35 , and the polysilicon is patterned by the lithography and the RIE, thereby forming a gate electrode 36 as shown in FIGS. 25 , 26 A, and 26 B.
  • a sidewall insulating film 37 is formed on the side surface of the gate electrode 36 .
  • impurity ions are further implanted, thereby forming a source diffusion layer 51 and a drain diffusion layer 52 in the silicon layer 26 .
  • Metal e.g., nickel
  • a silicide layer 39 is formed on the source diffusion layer 51 and the drain diffusion layers 52 and a silicide layer 40 is formed on the gate electrode 36 .
  • an interlayer insulating film 42 , contacts 43 , source lines SL, and bit lines BL are formed as shown in FIGS. 27 and 28 .
  • wirings are formed in the logic region.
  • the FBC memory is formed.
  • the gate electrode 36 acts as a word line WL and that the polysilicon layer 31 acts as the plate electrode.
  • the source diffusion layer 51 is opposite in conduction type to the bulk-silicon substrate 10 . Due to this, a pn junction is present between the source diffusion layer 51 and the bulk-silicon substrate 10 . A bias in forward direction is not applied to the pn junction. Accordingly, even if the source of the memory element is connected to the bulk-silicon substrate 10 , the characteristics of the memory cell are not deteriorated. In addition, no problems related to the operation of the memory cell occur.
  • the support column 50 made of silicon is formed in the source formation region in the second embodiment. Parts of the memory region other than the source formation region are formed to have the SOI structure.
  • the silicon layer 26 is supported by not only the boundary between the memory region and the logic region but also by the support column 50 . Due to this, the silicon layer 26 is stress-resistant at a subsequent oxidation step and not caved in the cavity 25 .
  • the second embodiment has the same effect as that of the first embodiment.
  • the plate electrode 31 is provided only below the drain layer 52 and the floating body FB and not provided below the source layer 51 .
  • the source layer 51 is electrically connected to the bulk-silicon substrate 10 through the support column 50 .
  • the support column 50 can be made of any one of a conductive material and an insulating material.
  • the plate electrode 31 is electrically isolated from the drain layer 52 , the floating body FB, and the bulk-silicon substrate 10 . Furthermore, the drain layer 52 and the floating body FB are electrically isolated from the bulk-silicon substrate 10 by the plate electrode 31 .
  • the silicon layer 26 is supported not only by the boundary between the memory region and the logic region but also by the support 50 .
  • the silicon layer 26 is, therefore, resistant against mechanical stress.
  • the FBC memory according to the second embodiment is advantageously easy to manufacture.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Thin Film Transistor (AREA)

Abstract

This disclosure concerns a method of manufacturing a semiconductor memory device comprising forming a plurality of trenches in a semiconductor substrate; forming a semiconductor layer provided on a cavity by connecting lower spaces of the trenches to one another and closing upper openings of the trenches in a heat treatment under a hydrogen atmosphere; etching the semiconductor layer in an isolation formation area; forming an insulating film on a side surface and a bottom surface of the semiconductor layer; filling the cavity under the semiconductor layer with an electrode material; and forming a memory element on the semiconductor layer.

Description

CROSS-REFERENCE TO RELATED APPLICATION
This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 2006-190585, filed on Jul. 11, 2006, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and a method of manufacturing a semiconductor memory device.
2. Related Art
Development of an FBC (Floating Body Cell) memory device that stores data in each FBC according to the number of a plurality of carries accumulated in a floating body of the FBC has been underway in place of a DRAM (Dynamic Random Access Memory) comprised of 1T (Transistor)-1C (Capacitor) type memory cells (Patent document 1). The FBC can dispense with the capacitor essential to an ordinary DRAM cell, so that the memory cell structure of the FBC memory device is simpler than that of the DRAM cell. The FBC is, therefore, advantageously easier to manufacture than the DRAM cell.
Generally, the FBC is constituted by a MISFET (Metal Insulator Semiconductor Field Effect Transistor) formed on an SOI (Silicon On Insulator) substrate. The SOI substrate is more expensive than an ordinary bulk-silicon substrate. Due to this, the manufacturing cost of the FBC is disadvantageously higher than the DRAM cell. Furthermore, design environment (e.g., SPICE MODEL) used for forming an LSI circuit on the bulk substrate cannot be applied to the SOI substrate as it is. Therefore, it is disadvantageously necessary to change the design environment to be suited for the SOI substrate in an LSI region other than a memory region. Moreover, high breakdown-voltage transistor characteristics and ESD (Electrostatic Discharge) characteristics of an input/output circuit or the like are often, disadvantageously deteriorated in the LSI region other than the memory region.
SUMMARY OF THE INVENTION
A method of manufacturing a semiconductor memory device according to an embodiment of the present invention comprises forming a plurality of trenches in a semiconductor substrate; forming a semiconductor layer provided on a cavity by connecting lower spaces of the trenches to one another and closing upper openings of the trenches in a heat treatment under a hydrogen atmosphere; etching the semiconductor layer in an isolation formation area; forming an insulating film on a side surface and a bottom surface of the semiconductor layer; filling the cavity under the semiconductor layer with an electrode material; and forming a memory element on the semiconductor layer.
A semiconductor memory device according to an embodiment of the present invention comprises a semiconductor substrate; a source and a drain formed in a surface region of the semiconductor substrate; a support column provided below the source and intervening between the source and the semiconductor substrate; a floating body provided between the source and the drain and accumulating or releasing charges to store data; a gate insulating film provided on the floating body; a gate electrode provided on the gate insulating film; and a plate electrode provided below the drain and the floating body, and electrically isolated from the floating body and the semiconductor substrate, wherein the drain and the floating body are electrically isolated from the semiconductor substrate by the plate electrode.
BRIEF DESCRIPTION OF THE DRAWINGS
FIGS. 1 to 14B are cross-sections or plan views showing a method of manufacturing an FBC memory according to a first embodiment of the present invention; and
FIGS. 15 to 28 are cross-sections or plan views showing a method of manufacturing an FBC memory device according to the second embodiment.
 DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be explained below with reference to the accompanying drawings. The present invention is not limited to the embodiments.
First Embodiment
FIGS. 1 to 14B are cross-sections or plan views showing a method of manufacturing an FBC memory according to a first embodiment of the present invention. A structure shown in FIGS. 1 to 14B is the memory cell structure of the FBC memory in a memory region. A logic region (“LSI region”) other than the memory region is formed on an ordinary bulk-silicon substrate and not formed on an SON (Silicon On Nothing) structure or an SOI structure (to be described later). Due to this, the logic region is not shown in FIGS. 1 to 14A, except for FIGS. 4C and 14B. FIGS. 1, 3, 5, 7, 9, 11, and 13 are plan views showing steps of the method of manufacturing the FBC memory device according to the first embodiment. FIGS. 2A, 4A, 6A, 8A, 10A, 12A, and 14A are cross-sections taken along lines A-A of FIGS. 1, 3, 5, 7, 9, 11, and 13, respectively. FIGS. 2B, 4B, 6B, 8B, 10B, and 12B are cross-sections taken along lines B-B of FIGS. 1, 3, 5, 7, 9, and 11, respectively.
A silicon nitride film used as a hard mask 21 is first deposited on a bulk-silicon substrate 10 serving as a semiconductor substrate. A plurality of openings are formed in the hard mask 21 using lithography and RIE (Reactive Ion Etching). Using the hard mask 21 as a mask, the bulk-silicon substrate 10 is etched by the RIE. As a result, a plurality of trenches 22 is formed in the bulk-silicon substrate 10 as shown in FIGS. 1, 2A, and 2B. In the first embodiment, the trenches 22 are formed equidistantly in a matrix. Each of the trenches 22 has an opening diameter of, for example, 0.5 μm and a depth of, for example, 1.0 μm. The distance between the two adjacent trenches 22 is, for example, 0.5 μm. That is, the opening diameters of the trenches 22 are respectively almost equal to distances between two adjacent trenches of the trenches 22. The depths of the trenches 22 are twice as large as the opening diameters of the trenches 22.
After removing the hard mask 21, the bulk-silicon substrate 10 is subjected to a heat treatment in hydrogen atmosphere. The heat treatment is performed, for example, at an atmospheric pressure of 300 Torr for about three minutes under the hydrogen atmosphere at 1000° C. As a result, upper openings of the respective trenches 22 are closed as shown in FIG. 3. Furthermore, as shown in FIGS. 4A and 4B, lower spaces of the trenches 22 are connected to one another. Accordingly, a cavity 25 is provided on the bulk-silicon substrate 10, and a silicon layer 26 serving as a semiconductor layer is formed on the cavity 25. The structure shown in FIGS. 4A and 4B is so-called silicon on nothing (SON) structure. Namely, by performing the heat treatment under the hydrogen atmosphere, the SON structure can be formed in the memory region while maintaining the state of the bulk-silicon substrate 10 in the logic region (See FIG. 4C).
Specifically, the heat treatment under the hydrogen atmosphere causes silicon on the surface of each trench 22 to flow to thereby minimize surface energy, and deforms the inner space of the trench 22 into a spherical shape. As a result, the upper openings of the trenches 22 are gradually closed, thereby eventually forming the silicon layer 26. Moreover, the inner spaces of the adjacent trenches 22 are connected to one another, whereby the cavity 25 is formed. The silicon layer 26 is supported by the boundary with the bulk-silicon substrate around the silicon layer.
As shown in FIGS. 5 and 6A, a silicon nitride film to be used as a hard mask 27 is deposited. The silicon nitride film is patterned into a line-space shape by the lithography and the RIE so as to cover up active areas AA. Using the hard mask 27 thus formed, the silicon layer 26 in element-isolation formation areas IA is etched into the line-space shape by the RIE. As a result, the cavity 25 is communicated with the outside in the element-isolation formation areas IA as shown in FIG. 6B.
The bulk-silicon substrate 10 is then oxidized. During the oxidization, the cavity 25 is communicated with the outside through the element-isolation formation areas IA. Due to this, as shown in FIGS. 8A and 8B, the interior of the cavity 25 and the surface of the silicon layer 26 are oxidized. Accordingly, a silicon oxide film 30 is formed on the side surface of the silicon layer 26, the bottom of the silicon layer 26, and the bottom of the cavity 25. The thickness of the silicon oxide film 30 is, for example, 10 nm.
A polysilicon layer 31 is deposited as an electrode material using CVD (Chemical Vapor Deposition). As a result, the cavity 25 is filled with the polysilicon layer 31 as shown in FIGS. 7, 8A, and 8B. The polysilicon layer 31 filled up in the cavity 25 is used as a plate electrode.
The polysilicon layer 31 is etched back, thereby removing the polysilicon layer 31 located at higher level than the surface level of the silicon layer 26 as shown in FIGS. 10A and 10B. At this moment, the polysilicon layer 31 filled up in the cavity 25 and in the element-isolation formation areas IA is left unremoved. The exposed surface of the polysilicon layer 31 in the element-isolation formation areas IA is oxidized. As a result, a silicon oxide film 32 serving as an element-isolation layer is formed in the element-isolation formation areas IA as shown in FIGS. 9 and 10B.
A gate insulating film 35 is then formed on the silicon layer 26. Polysilicon is deposited subsequently to formation of the gate insulating film 35, and the polysilicon is patterned by the lithography and the RIE, thereby forming a gate electrode 36 as shown in FIGS. 11, 12A, and 12B.
Using the gate electrode 36 as a mask, impurity ions are implanted, thereby forming an LDD (Lightly Diffused Drain) in he silicon layer 26. A sidewall insulating film 37 is formed on the side surface of the gate electrode 36. Using the sidewall insulating film 37 as a mask, impurity ions are further implanted, thereby forming source/drain diffusion layers 38 in the silicon layer 26.
Metal (e.g., nickel) is deposited on the source/drain diffusion layers 38 and the gate electrode 36 so as to react silicon with the metal. By doing so, a silicide layer 39 is formed on the source/drain diffusion layers 38 and a silicide layer 40 is formed on the gate electrode 36.
Thereafter, using a well-known method, an interlayer insulating film 42, contacts 43, source lines SL, and bit lines BL are formed as shown in FIGS. 13 and 14. Simultaneously with formation of the source lines SL and the bit lines BL, wirings are formed in the logic region, as shown in FIG. 14B. As a consequence, the FBC memory is formed. It is to be noted that the gate electrode 36 acts as a word line WL and that the polysilicon layer 31 acts as the plate electrode.
A floating body FB present under the word line WL (gate electrode 36) is surrounded by the source/drain diffusion layers 38, the gate insulating film 35, the silicon oxide film 30, and the element isolation layer 32. The floating body FB is, therefore, in an electrically floating state.
Impact ionization occurs to the boundary between the drain diffusion layer and the floating body FB when potential is applied to the word line WL and the bit line BL. Charges generated by the impact ionization are accumulated in the floating body FB. If the FBC is, for example, an n-type FET, holes are accumulated in the floating body FB. Electrons generated by the impact ionization are discharged to the drain diffusion layer 38.
The FBC stores therein data “0” or “1” according to the number of majority carriers accumulated in the floating body FB.
By applying the potential to the polysilicon layer 31 serving as the plate electrode while the FBC is in a data holding state, data-holding characteristics of the FBC can be improved.
In the manufacturing method according to the first embodiment, the FBC memory having the SOI structure can be formed using the bulk-silicon substrate 10. Therefore, the FBC memory can be manufactured at low cost with the manufacturing method according to the first embodiment.
In the manufacturing method according to the first embodiment, the FBC memory can be formed on the SOI substrate whereas the LSI circuit in the logic region can be directly formed on the ordinary bulk-silicon substrate 10. Therefore, it is possible to improve only the characteristics of the FBC memory without influencing the surrounding logic region. As a consequence, the existing design environment can be applied to the logic region. This can enhance design-development efficiency for the semiconductor memory device.
In the first embodiment, the LSI circuit in the logic region is directly formed on the bulk-silicon substrate 10. The LSI circuit formed on the bulk-silicon substrate 10 is superior to that formed on the SOI substrate in breakdown characteristics and ESD characteristics. The semiconductor memory device according to the first embodiment can be applied as a device which requires high breakdown voltage such as an input/output circuit.
In the memory region, the thickness of the silicon oxide film 30 between the polysilicon layer 31 serving as the plate electrode and the floating body FB is 10 nm. If the silicon oxide film 30 is thinner, a signal difference (potential difference between the data “0” and the data “1”) is larger in data read operation. Furthermore, if the silicon oxide film 30 is thinner, then the charge-retention characteristics in the floating body FB are improved and more stable operation of the FBC memory can be ensured. If a charge-retention time is longer, the frequency of refresh operations can be made lower, thereby realizing high-rate operation and low power consumption. In view of the characteristics of the FBC memory, therefore, it is preferable that the silicon oxide film 30 is thinner. If a BOX (Buried Oxide) layer in the logic region is made thinner while the SOI substrate, for example, is used, parasitic capacity between the substrate and a channel region becomes higher. This may possibly deteriorate the performance of the FBC. In the first embodiment, however, the plate electrode is formed only in the memory region, and the surrounding logic circuit is formed on the bulk-silicon substrate 10. It is, therefore, possible to stabilize the operation of the FBC memory without influencing the surrounding logic circuit according to the first embodiment.
Second Embodiment
In the first embodiment, the entire memory region has the SOI structure. Alternatively, even if the source region of the memory cell is provided on the bulk-silicon substrate, the characteristics of the FBC memory are not deteriorated. In a second embodiment of the present invention, therefore, a source diffusion layer is formed on a bulk-silicon substrate.
FIGS. 15 to 28 are cross-sections or plan views showing a method of manufacturing an FBC memory device according to the second embodiment. A structure shown in FIGS. 15 to 28 is the memory cell structure of the FBC memory in a memory region, and a logic region other than the memory region is not shown in FIGS. 15 to 28. The SOI structure is not provided in the logic region, and an LSI circuit in a logic region is formed on an ordinary bulk-silicon substrate. FIGS. 15, 17, 19, 21, 23, 25 and 27 are plan views showing steps of the method of manufacturing the FBC memory device according to the second embodiment. FIGS. 16A, 18A, 20A, 22A, 24A, 26A, and 28 are cross-sections taken along lines A-A of FIGS. 15, 17, 19, 21, 23, 25, and 27, respectively. FIGS. 16B, 18B, 20B, 22B, 24B, and 26B are cross-sections taken along lines B-B of FIGS. 15, 17, 19, 21, 23, and 25, respectively.
A silicon nitride film used as a hard mask 21 is first deposited on a bulk-silicon substrate 10 serving as a semiconductor substrate. A plurality of openings is formed in the hard mask 21 using the lithography and the RIE. At this moment, the openings are formed equidistantly in a matrix in the first embodiment. However, no openings are formed in a source formation region of the memory region in the second embodiment. Using the hard mask 21 as a mask, the bulk-silicon substrate 10 is etched by the RIE. As a result, a plurality of trenches 22 is formed in the bulk-silicon substrate 10 as shown in FIGS. 15, 16A, and 16B.
Each of the trenches 22 has an opening diameter of, for example, 0.5 μm and a depth of, for example, 1.0 μm. In regions other than the source formation region, the distance between the two adjacent trenches 22 is, for example, 0.5 μm. In the source formation region, the distance between the two adjacent trenches 22 is twice or more as large as the opening diameter. In the second embodiment, the distance between the two adjacent trenches 22 in the source formation region is, for example, equal to or larger than 1 μm.
After removing the hard mask 21, the bulk-silicon substrate 10 is subjected to a heat treatment in hydrogen atmosphere. The heat treatment is performed, for example, at an atmospheric pressure of 300 Torr for about three minutes under the hydrogen atmosphere at 1100° C. As a result, upper openings of the respective trenches 22 are closed as shown in FIG. 17. Furthermore, as shown in FIGS. 18A and 18B, lower spaces of the trenches 22 are connected to one another. Accordingly, a cavity 25 is provided on the bulk-silicon substrate 10, and a silicon layer 26 serving as a semiconductor layer is formed on the cavity 25.
On the other hand, since no trenches are formed in the source formation region, the state of the bulk-silicon substrate 10 is maintained similarly to the logic region. A supporting column 50 made of silicon is formed in the source formation region. Parts of the memory region other than the source formation region are formed to have the SON structure. The silicon layer 26 is supported not only by the boundary between the memory region and the logic region but also by the supporting column 50. It is, therefore, possible to maintain the mechanical strength of the silicon layer 26, and prevent the silicon layer 26 from being caved in the cavity 25.
As shown in FIGS. 19 and 20A, a silicon nitride film to be used as a hard mask 27 is deposited. The silicon nitride film is patterned into a line-space shape by the lithography and the RIE so as to cover up active areas AA. Using the hard mask 27 thus formed, the silicon layer 26 in isolation formation areas IA is etched into the line-space shape by the RIE. As a result, the cavity 25 is communicated with the outside in the isolation formation areas IA as shown in FIG. 20B.
The bulk-silicon substrate 10 is then oxidized. During the oxidization, the cavity 25 is communicated with the outside through the isolation formation areas IA. Due to this, as shown in FIGS. 22A and 22B, the interior of the cavity 25 and the surface of the silicon layer 26 are oxidized. Accordingly, a silicon oxide film 30 is formed on the side surface of the silicon layer 26, the bottom of the silicon layer 26, and the bottom of the cavity 25. The thickness of the silicon oxide film 30 is, for example, 10 nm.
A polysilicon layer 31 is deposited as an electrode material using the CVD. As a result, the cavity 25 is filled with the polysilicon layer 31 as shown in FIGS. 21, 22A, and 22B. The polysilicon layer 31 filled up in the cavity 25 is used as a plate electrode.
The polysilicon layer 31 is etched back, thereby removing the polysilicon layer 31 located at higher level than the surface level of the silicon layer 26 as shown in FIGS. 24A and 24B. At this moment, the polysilicon layer 31 filled up in the cavity 25 and in the isolation formation areas IA is left unremoved. The exposed surface of the polysilicon layer 31 in the isolation formation areas IA is oxidized. As a result, a silicon oxide film 32 serving as an element-isolation layer is formed in the isolation formation areas IA as shown in FIGS. 23 and 24B.
A gate insulating film 35 is then formed on the silicon layer 26. Polysilicon is deposited subsequently to formation of the gate insulating film 35, and the polysilicon is patterned by the lithography and the RIE, thereby forming a gate electrode 36 as shown in FIGS. 25, 26A, and 26B.
Using the gate electrode 36 as a mask, impurity ions are implanted, thereby forming an LDD in the silicon layer 26. A sidewall insulating film 37 is formed on the side surface of the gate electrode 36. Using the sidewall insulating film 37 as a mask, impurity ions are further implanted, thereby forming a source diffusion layer 51 and a drain diffusion layer 52 in the silicon layer 26.
Metal (e.g., nickel) is deposited on the source layer 51, the drain layer 52, and the gate electrode 36 so as to react silicon with the metal. By doing so, a silicide layer 39 is formed on the source diffusion layer 51 and the drain diffusion layers 52 and a silicide layer 40 is formed on the gate electrode 36.
Thereafter, using a well-known method, an interlayer insulating film 42, contacts 43, source lines SL, and bit lines BL are formed as shown in FIGS. 27 and 28. Simultaneously with formation of the source lines SL and the bit lines BL, wirings are formed in the logic region. As a consequence, the FBC memory is formed. It is to be noted that the gate electrode 36 acts as a word line WL and that the polysilicon layer 31 acts as the plate electrode.
The source diffusion layer 51 is opposite in conduction type to the bulk-silicon substrate 10. Due to this, a pn junction is present between the source diffusion layer 51 and the bulk-silicon substrate 10. A bias in forward direction is not applied to the pn junction. Accordingly, even if the source of the memory element is connected to the bulk-silicon substrate 10, the characteristics of the memory cell are not deteriorated. In addition, no problems related to the operation of the memory cell occur.
The support column 50 made of silicon is formed in the source formation region in the second embodiment. Parts of the memory region other than the source formation region are formed to have the SOI structure. The silicon layer 26 is supported by not only the boundary between the memory region and the logic region but also by the support column 50. Due to this, the silicon layer 26 is stress-resistant at a subsequent oxidation step and not caved in the cavity 25. The second embodiment has the same effect as that of the first embodiment.
In the FBC memory according to the second embodiment, the plate electrode 31 is provided only below the drain layer 52 and the floating body FB and not provided below the source layer 51. The source layer 51 is electrically connected to the bulk-silicon substrate 10 through the support column 50. The support column 50 can be made of any one of a conductive material and an insulating material. The plate electrode 31 is electrically isolated from the drain layer 52, the floating body FB, and the bulk-silicon substrate 10. Furthermore, the drain layer 52 and the floating body FB are electrically isolated from the bulk-silicon substrate 10 by the plate electrode 31.
As described so far, even if the source of the memory element is connected to the bulk-silicon substrate 10, the characteristics of the memory element are not deteriorated. Moreover, the silicon layer 26 is supported not only by the boundary between the memory region and the logic region but also by the support 50. The silicon layer 26 is, therefore, resistant against mechanical stress. The FBC memory according to the second embodiment is advantageously easy to manufacture.

Claims (7)

1. A semiconductor memory device comprising:
a semiconductor substrate;
a source and a drain formed in a surface region of the semiconductor substrate;
a support column provided below the source and intervening between the source and the semiconductor substrate;
a floating body provided between the source and the drain and accumulating or releasing charges to store data;
a gate insulating film provided on the floating body;
a gate electrode provided on the gate insulating film;
a plate electrode provided below the drain and the floating body, and electrically isolated from the floating body and the semiconductor substrate,
a source line electrically connected to the source;
a bit line electrically connected to the drain;
a source line contact connecting between the source line and the source;
a bit line contact connecting between the bit line and the drain, wherein
the drain and the floating body are electrically isolated from the semiconductor substrate by the plate electrode; and
the plate electrode is provided under a whole of the drain and a whole of the floating body, but not provided under the source.
2. The semiconductor memory device according to claim 1, wherein
the support column includes an insulation material.
3. The semiconductor memory device according to claim 1, wherein
the support column includes a conductive material.
4. The semiconductor memory device according to claim 1, wherein
the support column electrically connects the source to the semiconductor substrate.
5. The semiconductor memory device according to claim 1 further comprising:
a memory region in which memory cells respectively including the floating body are provided; and
a logic region in which a logic circuit controlling the memory cell is provided, wherein
a plurality of support columns are provided equidistantly in the memory region other than a boundary between the memory region and the logic region.
6. The semiconductor memory device according to claim 1, wherein the plate electrode is provided right under the bit line contact.
7. The semiconductor memory device according to claim 5, wherein the plate electrode is provided only in the memory region, but is not provided in the logic region and
the logic region is directly formed on the semiconductor substrate.
US11/687,131 2006-07-11 2007-03-16 Semiconductor memory device having a floating body and a plate electrode Active 2027-07-12 US7719056B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2006-190585 2006-07-11
JP2006190585A JP4755946B2 (en) 2006-07-11 2006-07-11 Semiconductor memory device and manufacturing method thereof

Publications (2)

Publication Number Publication Date
US20080032474A1 US20080032474A1 (en) 2008-02-07
US7719056B2 true US7719056B2 (en) 2010-05-18

Family

ID=39029715

Family Applications (1)

Application Number Title Priority Date Filing Date
US11/687,131 Active 2027-07-12 US7719056B2 (en) 2006-07-11 2007-03-16 Semiconductor memory device having a floating body and a plate electrode

Country Status (2)

Country Link
US (1) US7719056B2 (en)
JP (1) JP4755946B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110049619A1 (en) * 2009-08-28 2011-03-03 Hynix Semiconductor Inc. Semiconductor device and method for manufacturing the same
US20120313151A1 (en) * 2011-06-07 2012-12-13 Young-Kyu Lee Semiconductor device including contact structure, method of fabricating the same, and electronic system including the same
US20160163730A1 (en) * 2014-12-09 2016-06-09 Joon-Sung LIM Semiconductor device
US10170304B1 (en) 2017-10-25 2019-01-01 Globalfoundries Inc. Self-aligned nanotube structures

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5891597B2 (en) * 2011-04-07 2016-03-23 富士電機株式会社 Manufacturing method of semiconductor substrate or semiconductor device
US11016055B2 (en) * 2019-07-09 2021-05-25 Globalfoundries Singapore Pte. Ltd. Sensors with a front-end-of-line solution-receiving cavity
US20230171944A1 (en) * 2020-05-28 2023-06-01 Zeno Semiconductor, Inc. A Memory Device Comprising an Electrically Floating Body Transistor

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5943581A (en) * 1997-11-05 1999-08-24 Vanguard International Semiconductor Corporation Method of fabricating a buried reservoir capacitor structure for high-density dynamic random access memory (DRAM) circuits
JP2001144276A (en) 1999-08-31 2001-05-25 Toshiba Corp Semiconductor substrate and method of production
US20020043692A1 (en) * 1998-10-26 2002-04-18 Shigenobu Maeda Semiconductor storage device
JP2002246571A (en) 2001-02-15 2002-08-30 Toshiba Corp Semiconductor memory device
US6919238B2 (en) * 2002-07-29 2005-07-19 Intel Corporation Silicon on insulator (SOI) transistor and methods of fabrication
US6965147B2 (en) * 2003-11-25 2005-11-15 Kabushiki Kaisha Toshiba Semiconductor device including transistors formed in semiconductor layer having single-crystal structure isolated from substrate

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4064607B2 (en) * 2000-09-08 2008-03-19 株式会社東芝 Semiconductor memory device
JP4104836B2 (en) * 2001-05-17 2008-06-18 株式会社東芝 Semiconductor memory device and manufacturing method thereof
JP3934507B2 (en) * 2002-08-08 2007-06-20 株式会社東芝 Semiconductor memory device and manufacturing method of semiconductor memory device
JP4028499B2 (en) * 2004-03-01 2007-12-26 株式会社東芝 Semiconductor memory device
JP3898715B2 (en) * 2004-09-09 2007-03-28 株式会社東芝 Semiconductor device and manufacturing method thereof

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5943581A (en) * 1997-11-05 1999-08-24 Vanguard International Semiconductor Corporation Method of fabricating a buried reservoir capacitor structure for high-density dynamic random access memory (DRAM) circuits
US20020043692A1 (en) * 1998-10-26 2002-04-18 Shigenobu Maeda Semiconductor storage device
JP2001144276A (en) 1999-08-31 2001-05-25 Toshiba Corp Semiconductor substrate and method of production
JP2002246571A (en) 2001-02-15 2002-08-30 Toshiba Corp Semiconductor memory device
US6919238B2 (en) * 2002-07-29 2005-07-19 Intel Corporation Silicon on insulator (SOI) transistor and methods of fabrication
US6965147B2 (en) * 2003-11-25 2005-11-15 Kabushiki Kaisha Toshiba Semiconductor device including transistors formed in semiconductor layer having single-crystal structure isolated from substrate

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
Tsutomu Sato, et al., "A new Substrate Engineering for the Formation of Empty Space in Silicon (ESS) induced by Silicon Surface Migration", IEDM Tech. Dig., 1999, 4 pages.
Tsutomu Sato, et al., "Trench Transformation Technology using Hydrogen Annealing for Realizing Highly Reliable Device Structure with Thin Dielectric Films", VLSI Tech. Dig., 1998, 2 pages.

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110049619A1 (en) * 2009-08-28 2011-03-03 Hynix Semiconductor Inc. Semiconductor device and method for manufacturing the same
US8357578B2 (en) * 2009-08-28 2013-01-22 Hynix Semiconductor Inc. Semiconductor device and method for manufacturing the same
US20120313151A1 (en) * 2011-06-07 2012-12-13 Young-Kyu Lee Semiconductor device including contact structure, method of fabricating the same, and electronic system including the same
US8791510B2 (en) * 2011-06-07 2014-07-29 Samsung Electronics Co., Ltd. Semiconductor device including contact structure, method of fabricating the same, and electronic system including the same
US20160163730A1 (en) * 2014-12-09 2016-06-09 Joon-Sung LIM Semiconductor device
US9548316B2 (en) * 2014-12-09 2017-01-17 Samsung Electronics Co., Ltd. Semiconductor device
US10170304B1 (en) 2017-10-25 2019-01-01 Globalfoundries Inc. Self-aligned nanotube structures

Also Published As

Publication number Publication date
JP4755946B2 (en) 2011-08-24
JP2008021727A (en) 2008-01-31
US20080032474A1 (en) 2008-02-07

Similar Documents

Publication Publication Date Title
US9786667B2 (en) Floating body memory cell having gates favoring different conductivity type regions
US7170126B2 (en) Structure of vertical strained silicon devices
US6977404B2 (en) Trench DRAM with double-gated transistor and method of manufacturing the same
US7129130B2 (en) Out of the box vertical transistor for eDRAM on SOI
US7566620B2 (en) DRAM including a vertical surround gate transistor
JP3934507B2 (en) Semiconductor memory device and manufacturing method of semiconductor memory device
US7449382B2 (en) Memory device and fabrication method thereof
US8263460B2 (en) Method for manufacturing semiconductor device with buried gates
US20010025973A1 (en) Semiconductor integrated circuit device and process for manufacturing the same
US7719056B2 (en) Semiconductor memory device having a floating body and a plate electrode
US11315928B2 (en) Semiconductor structure with buried power line and buried signal line and method for manufacturing the same
KR20040111151A (en) Trench capacitor dram cell using buried oxide as array top oxide
JP2009246383A (en) Semiconductor device
US20070215916A1 (en) Semiconductor device and manufacturing method thereof
US6902982B2 (en) Trench capacitor and process for preventing parasitic leakage
JP2007281199A (en) Semiconductor device
JP4315943B2 (en) Manufacturing method of semiconductor device
JP4369405B2 (en) Semiconductor device
US7091546B2 (en) Semiconductor memory with trench capacitor and method of fabricating the same
US20080277741A1 (en) Semiconductor device and method for manufacturing the same
CN117082855A (en) Method for embedding a conductor line in a semiconductor structure and semiconductor structure
JP2007180570A (en) Semiconductor device and method of manufacturing the same

Legal Events

Date Code Title Description
AS Assignment

Owner name: KABUSHIKI KAISHA TOSHIBA, JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HAMAMOTO, TAKESHI;REEL/FRAME:019024/0527

Effective date: 20070308

Owner name: KABUSHIKI KAISHA TOSHIBA,JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HAMAMOTO, TAKESHI;REEL/FRAME:019024/0527

Effective date: 20070308

STCF Information on status: patent grant

Free format text: PATENTED CASE

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

FPAY Fee payment

Year of fee payment: 4

AS Assignment

Owner name: TOSHIBA MEMORY CORPORATION, JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:KABUSHIKI KAISHA TOSHIBA;REEL/FRAME:043709/0035

Effective date: 20170706

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552)

Year of fee payment: 8

AS Assignment

Owner name: K.K. PANGEA, JAPAN

Free format text: MERGER;ASSIGNOR:TOSHIBA MEMORY CORPORATION;REEL/FRAME:055659/0471

Effective date: 20180801

Owner name: KIOXIA CORPORATION, JAPAN

Free format text: CHANGE OF NAME AND ADDRESS;ASSIGNOR:TOSHIBA MEMORY CORPORATION;REEL/FRAME:055669/0001

Effective date: 20191001

Owner name: TOSHIBA MEMORY CORPORATION, JAPAN

Free format text: CHANGE OF NAME AND ADDRESS;ASSIGNOR:K.K. PANGEA;REEL/FRAME:055669/0401

Effective date: 20180801

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 12TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1553); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 12