JP2008071861A - Semiconductor memory and manufacturing method thereof - Google Patents

Semiconductor memory and manufacturing method thereof Download PDF

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JP2008071861A
JP2008071861A JP2006247760A JP2006247760A JP2008071861A JP 2008071861 A JP2008071861 A JP 2008071861A JP 2006247760 A JP2006247760 A JP 2006247760A JP 2006247760 A JP2006247760 A JP 2006247760A JP 2008071861 A JP2008071861 A JP 2008071861A
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memory device
semiconductor memory
formed
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Yukikazu Inoue
幸多 井上
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Renesas Technology Corp
株式会社ルネサステクノロジ
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Abstract

An object of the present invention is to increase the integration density of memory cells and increase the capacitance of memory cell capacitors.
An N-type conductive film 4n serving as a field shield electrode is formed in an isolation trench 2 that defines an active region 40 of a semiconductor substrate. In each active region 40, two DRAM cells including capacitors formed at both ends thereof and two transistors having the gate electrode 12 are formed. The capacitors at both ends of the active region 40 use the impurity diffusion layer on the inner wall of the isolation trench 2 (side wall of the active region 40) as a storage electrode and the N-type conductive film 4n in the isolation trench 2 as a cell plate electrode. The N-type conductive films 4 n that are the cell plate electrodes of the capacitor at both ends of the active region 40 are connected to each other in the isolation trench 2.
[Selection] Figure 2

Description

  The present invention relates to a semiconductor memory device and a method for manufacturing the same, and relates to a structure of a memory cell having a capacitor, such as a DRAM (Dynamic Random Access Memory).

  As a conventional semiconductor memory device, a DRAM is known that includes a MOS (Metal-Oxide Semiconductor) transistor and a capacitor having an impurity diffusion layer connected to the source / drain region of the MOS transistor as a lower electrode (storage electrode). (For example, Patent Document 1).

  In the DRAM cell capacitor of Patent Document 1, the upper electrode (cell plate electrode) is formed using the same layer as the gate electrode of the MOS transistor. The active region in which the DRAM cell is formed is defined by an isolation trench formed in the semiconductor substrate, and the active regions are separated from each other by an isolation insulating film (field insulating film) embedded in the isolation trench. Then, a recess (cavity) is formed above the isolation insulating film in the capacitor formation region of the memory cell, and the capacitor is extended into the recess, thereby increasing the effective area of the capacitor and increasing the capacitance. .

  On the other hand, as a technique for isolating active regions as in the case of the isolation insulating film, there is a “field shield” that isolates elements by the action of an electric field using an electrode having a MOS structure. In this technique, an isolation trench defining an active region in a semiconductor substrate has a conductive film (field shield electrode) via a thin insulating film (inner wall insulating film) formed on the inner wall (side wall of the active region) of the isolation trench. Is embedded (for example, Patent Document 2).

  As a semiconductor memory device using this field shield structure, a DRAM cell is also proposed in which the field shield electrode in the isolation trench is used as the cell plate electrode of the capacitor of the memory cell, and the impurity diffusion layer formed on the inner wall of the isolation trench is used as the storage electrode. (For example, Patent Documents 3 and 4). According to this method, the formation process of the field shield structure and the capacitor structure can be integrated, and the DRAM cell can be increased in density (high integration). In particular, Patent Document 3 proposes a technique for increasing the effective area of the capacitor and increasing the capacitance by providing minute irregularities on the inner wall of the trench.

JP-T-2004-527901 International Publication No. WO2006 / 046442 Pamphlet JP-A-10-163450 Japanese Patent Laid-Open No. 11-40777

  As seen in the examples of Patent Documents 1 to 3 described above, increasing the density of DRAM cells and increasing the capacitance of the capacitors are important issues in promoting downsizing and higher performance of DRAM devices. Yes.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to increase the density of memory cells and increase the capacity of capacitors in a semiconductor memory device.

  A semiconductor substrate; a trench defining an active region in the semiconductor substrate; an inner wall insulating film formed on an inner wall of the trench; a conductive film embedded in the trench through the inner wall insulating film; and a memory cell The first active region, which is the active region formed with the first active region, and the impurity diffusion layer formed on the inner wall of the trench as the first electrode and the inner wall insulating film as the dielectric, respectively, are formed at both ends of the first active region. A first capacitor and a second capacitor having the conductive film as a second electrode, wherein the second electrode of the first capacitor and the second electrode of the second capacitor are connected in the trench. It is.

  A method of manufacturing a semiconductor memory device including a memory cell having a capacitor and a transistor, wherein: (a) forming a trench defining an active region in the semiconductor substrate above the semiconductor substrate; and (b) the memory Forming an impurity diffusion layer on the inner wall of the trench corresponding to the side wall of the first active region, which is the active region for forming a cell, by ion implantation; and (c) providing an inner wall insulating film on the inner wall of the trench. (D) a step of burying non-doped polysilicon in the trench after the step (c); and (e) introducing a dopant into the first active region and the non-doped polysilicon by ion implantation. As a result, a well is formed in the first active region, and the non-doped polysilicon is made a conductive film, whereby the non-doped polysilicon is formed. Things diffusion layer of the first electrode, the dielectric layer the inner wall insulating film, the conductive film in which and a step of forming the capacitor to the second electrode.

  According to the semiconductor memory device of the present invention, the second electrode of the first capacitor at one end of the first active region and the second electrode of the second capacitor at the other end are connected to each other in the trench. In addition, one cell plate contact can be shared by the second capacitor, and the required number of cell plate contacts can be reduced to increase the density of DRAM cells. If the conductive film as the second capacitor surrounds the first active region, the effective areas of the first and second capacitors are increased, and the capacitance can be increased.

  According to the method for manufacturing a semiconductor memory device of the present invention, the dopant is introduced into the non-doped polysilicon in the trench by ion implantation for forming a well in the first active region, so that the conductive film The conductive film has the same conductivity type as the well. Therefore, the polarities of the bottom and inner walls of the trench are not easily reversed, the element isolation capability of the field shield structure is improved, and the leakage current between the memory cells is suppressed.

<Embodiment 1>
FIG. 1A is a basic circuit diagram of a 1-transistor 1-capacitor DRAM cell. The DRAM cell 100 includes an access transistor T that performs data writing, refreshing, reading, and the like, and a capacitor C that accumulates charges corresponding to the data. In this example, the access transistor T is a P-channel MOS transistor. The gate electrode of the access transistor T is connected to the word line WL, one of the source / drain electrodes is connected to the bit line BL, and the other is connected to one electrode (storage electrode) of the capacitor C. The other electrode (cell plate electrode) of the capacitor C is fixed to a predetermined voltage Vcp.

  FIG. 1B is a basic circuit diagram of a complementary DRAM cell 200 having the DRAM cell 100 shown in FIG. 1A as a memory unit. As shown in FIG. 1B, one complementary DRAM cell 200 is composed of two DRAM cells 100 sharing a word line WL (for this reason, the complementary DRAM cell is a twin cell RAM (TCRAM)). Also called). The two DRAM cells 100 constituting the complementary DRAM cell 200 operate so as to read and write data signals complementary to each other. That is, complementary data signals are input / output to / from the pair of bit lines BL, / BL to which the complementary DRAM cell 200 is connected. According to the complementary DRAM cell 200, the amplitude of the read signal can be doubled that of the normal DRAM cell of FIG. 1A, and noise is canceled by the two DRAM cells 100 performing complementary operations. Therefore, high speed operation becomes possible.

  2 to 5 are diagrams showing the configuration of the semiconductor memory device according to the first embodiment. More specifically, FIG. 2 is a top view of a DRAM cell array included in the semiconductor memory device. 3 is a cross-sectional view taken along the line AA shown in FIG. 2, and shows a cross section of the active region 40 in the direction of the bit line 8b (not shown in FIG. 2). FIG. 4 is a cross-sectional view taken along line BB shown in FIG. 2, and shows a cross section of the isolation region between the active regions 40 adjacent to each other in the extending direction of the word line (corresponding to the gate electrode 12). . FIG. 5 shows a cross-sectional perspective view of the region E shown in FIG. In these drawings, the same symbols are assigned to the same elements.

  In the region (memory cell region) where the DRAM cell array is formed, a plurality of active regions 40 defined by the isolation trenches 2 are arranged in a matrix as shown in FIG. In each of the active regions 40 of the memory cell region, two DRAM cells arranged in the bit line extending direction (the direction along the line AA) are formed. That is, as shown in FIG. 3, each active region 40 in the memory cell region is formed at the other end with a DRAM cell comprising a capacitor C1 formed at one end thereof and an access transistor T1 (PMOS transistor) connected thereto. The capacitor C2 and the DRAM cell comprising the access transistor T2 (PMOS transistor) connected to the capacitor C2 are formed.

  As shown in FIGS. 3 and 4, the active region 40 is defined by the isolation trench 2 formed in the upper part of the silicon substrate 1. An inner wall oxide film 3 (inner wall insulating film) is formed on the inner wall of the isolation trench 2 (side wall of the active region 40), and the conductive film 4n is embedded in the isolation trench 2 via the inner wall oxide film 3. It is. That is, the isolation structure between the active regions 40 is a field shield structure. In the present embodiment, the active region 40 of the memory cell region is formed in the N well region 10, and the conductive film 4n, which is a field shield electrode, is a polysilicon film into which an N-type dopant has been introduced (hereinafter referred to as “N”). Type conductive film).

  As shown in FIG. 3, each of the access transistors T1, T2 includes a gate oxide film 11, a polysilicon gate electrode 12 formed thereon, a silicon nitride film sidewall 13 formed on the side surface of the gate electrode 12, The source / drain regions 14 and 15 are formed on both sides of the gate electrode 12 above the N well region 10.

  Silicides 12s, 14s, and 15s are formed on the gate electrode 12 and the source / drain regions 14 and 15, respectively, for the purpose of reducing resistance. The source / drain region 14 is connected to a contact (bit line contact) 7b connected to the bit line 8b formed on the interlayer insulating film 6 through the silicide 14s. Further, a contact (word line contact) formed in a portion (not shown) is also connected to the gate electrode 12 functioning as a word line via the gate electrode 12. On the other hand, no contact is formed on the source / drain region 15, but the silicide 15s reduces the connection resistance between the access transistors (access transistors T1, T2) and the capacitors (capacitors C1, C2), thereby reducing the DRAM. This contributes to the high-speed operation of the cell.

  Each of capacitors C1 and C2 includes a P-type impurity diffusion layer 16 (hereinafter referred to as “capacitor electrode diffusion layer 16”) formed on the inner wall of isolation trench 2 corresponding to the side wall near the end of active region 40, and a field shield. The inner wall oxide film 3 and the N-type conductive film 4n are structured. That is, the capacitor electrode diffusion layer 16 is connected to the source / drain region 15 and functions as a storage electrode (first electrode) of the capacitors C1 and C2, and the inner wall oxide film 3 functions as a dielectric layer of the capacitors C1 and C2. The N-type conductive film 4n functions as the capacitor C1, C2 cell plate electrode (second electrode). A cap oxide film 5 made of a silicon oxide film is formed on the upper surface of the N-type conductive film 4n.

  In this embodiment, as shown in FIGS. 4 and 5, the isolation trench 2 between the active regions 40 adjacent to the extending direction of the gate electrode 12 (the isolation trench 2 running perpendicular to the gate electrode 12) is also oxidized on the inner wall. It has a field shield structure in which an N-type conductive film 4n is embedded through a film 3. That is, the N-type conductive film 4n that is the second electrode of the capacitor C1 formed at one end of the active region 40 shown in FIG. 3 and the N-type conductive film that is the second electrode of the capacitor C2 formed at the other end. 4n is connected in the isolation trench 2.

  Although not shown in FIGS. 2 to 5, a contact (cell plate contact) connected to the second electrode (N-type conductive film 4n) of the capacitors C1 and C2 is formed on the second electrode (N-type conductive film 4n). A cell plate voltage Vcp is applied thereto. Since the second electrodes of the capacitors C1 and C2 at both ends of the active region 40 are connected in the isolation trench 2, one cell plate contact can be shared by the capacitors C1 and C2, and the required number of cell plate contacts can be reduced. There is an advantage that the density of the cell can be increased. A specific example of the cell plate contact layout will be described later (FIGS. 22 to 24).

  As shown in FIG. 2, in the present embodiment, each of the plurality of active regions 40 in which the DRAM cell is formed is surrounded by an N-type conductive film 4n, and all of the N-type conductive film 4n is They are integrally connected (that is, the N-type conductive film 4n is formed in a mesh shape in plan view). That is, all the second electrodes (N-type conductive film 4n) of the capacitors C1 and C2 formed in each active region 40 in the memory cell region are connected in the isolation trench 2.

  Since each active region 40 in which the DRAM cell is formed is surrounded by the N-type conductive film 4n, the active region 40 is surrounded by a sidewall on the outer side of the gate electrode 12 (in FIG. All the parts shown) contribute to the effective area of the capacitors C1, C2. Thereby, the capacitance of the capacitors C1 and C2 can be increased.

  Further, according to the present embodiment, the cell plate electrodes (N-type conductive film 4n) of the capacitors C1 and C2 are embedded in the isolation trench 2. For example, when the cell plate electrode is formed using the same layer as the gate electrode of the access transistor as in Patent Document 1 described above, the cell plate electrode needs to be wider than the isolation trench 2. Since this is not necessary in the embodiment, the density of DRAM cells can be increased. For example, the distance between the gate electrodes 12 of the DRAM cells adjacent to each other with the isolation trench 2 interposed therebetween (distance D shown in FIG. 2) can be reduced to about 0.54 μm (the cell plate electrode and the access transistor gate electrode). In the case of forming the same layer, about 0.74 μm was necessary).

  Further, when the cell plate electrode is formed in the same layer as the gate electrode of the access transistor, the source / drain region of the access transistor is covered with the sidewall of the cell plate electrode when the distance between both electrodes is reduced (for example, Patent Document 1). FIG. 3-R). In that case, it becomes difficult to silicide the source / drain region in the subsequent process, and a high resistance region with a low impurity concentration is formed under the side wall of the cell plate electrode. Arise. On the other hand, in this embodiment, since the cell plate electrode is embedded in the isolation trench 2, a space is formed on the source / drain region 15 connected to the capacitor electrode diffusion layer 16 which is a storage electrode, and silicidation and impurity ion implantation are performed. These problems are solved because they can be done easily.

  In general, a semiconductor memory device includes not only a memory cell but also a peripheral circuit for driving it. FIG. 6 is a cross-sectional view of the vicinity of the boundary between the memory cell region in which the array of DRAM cells is formed and the peripheral circuit region in which the peripheral circuit is formed in the semiconductor memory device according to the first embodiment. In the left memory area in FIG. 6, DRAM cells are shown, and in the right peripheral circuit area, peripheral circuit transistors (peripheral transistors) are shown. In FIG. 6, elements corresponding to those shown in FIG. 3 are denoted by the same reference numerals. Further, the DRAM cell shown in the memory cell region of FIG. 6 is the same as that shown in FIG. 6, and therefore detailed description thereof is omitted here.

  On the other hand, the peripheral circuit region of FIG. 6 shows an NMOS transistor (hereinafter “peripheral NMOS transistor”) Tn and a PMOS transistor (hereinafter “peripheral PMOS transistor”) Tp of the peripheral circuit. The peripheral NMOS transistor Tn and the peripheral PMOS transistor Tp are also formed in the active region 40 defined by the isolation trench 2 having a field shield structure, like the DRAM cell in the memory cell region. The active region 40 in which the peripheral PMOS transistor Tp is formed is formed in the N well region 20, and the active region 40 in which the peripheral NMOS transistor Tn is formed is formed in the P well region 30.

  In the present embodiment, the conductive film embedded in the isolation trench 2 in the N well region 20 is polysilicon (N type conductive film 4 n) into which an N type dopant is introduced, and the P well region 30. The conductive film embedded in the isolation trench 2 is polysilicon (P-type conductive film 4p) into which a P-type dopant is introduced. The N-type conductive film 4n and the P-type conductive film 4p in the peripheral circuit region are connected to the wiring 8 on the interlayer insulating film 6 through the contact 7n and the contact 7p, respectively, through which the N-type conductive film 4n The P-type conductive film 4p can be set to a predetermined voltage.

  The peripheral PMOS transistor Tp includes a silicon oxide gate oxide film 21, a polysilicon gate electrode 22 formed thereon, a silicon nitride film sidewall 23 formed on the side surface of the gate electrode 22, and an N well region 20. Are formed by P-type source / drain regions 24 formed on both sides of the gate electrode 22 in the surface portion of the gate electrode 22. Silicides 22s and 24s are formed on the gate electrode 22 and the source / drain region 24, respectively. The gate electrode 22 and the source / drain region 24 are connected to a contact 7 connected to a predetermined wiring 8 formed on the interlayer insulating film 6 through silicides 22s and 24s, respectively.

  The peripheral NMOS transistor Tn has a conductivity type opposite to that of the peripheral PMOS transistor Tp, but its configuration is substantially the same as that of the peripheral PMOS transistor Tp. That is, the peripheral NMOS transistor Tn includes a gate oxide film 31 of a silicon oxide film, a polysilicon gate electrode 32 formed thereon, a side wall 33 of a silicon nitride film formed on the side surface of the gate electrode 32, and a P well. An N-type source / drain region 34 is formed on both sides of the gate electrode 32 in the surface portion of the region 30. Silicides 32s and 34s are formed on the gate electrode 32 and the source / drain region 34, respectively. The gate electrode 32 and the source / drain region 34 are connected to a contact 7 connected to a predetermined wiring 8 formed on the interlayer insulating film 6 through silicides 32s and 34s, respectively.

  Here, as shown in FIG. 6, the N-type conductive film 4n, which is the field shield electrode in the N well region 20, has a top surface that is higher than the bottom of the source / drain region 24 of the peripheral PMOS transistor Tp. It is formed to be higher. Similarly, the P-type conductive film 4p is formed so that the height of the upper surface thereof is higher than the bottom of the source / drain region 34 of the adjacent peripheral NMOS transistor Tn. As a result, when the potentials of the two source / drain regions sandwiching the field shield electrode are different from each other, the electric field generated in one of the source / drain regions is prevented from affecting the other source / drain region and causing potential variation. Is done.

  In the present embodiment, as shown in FIG. 6, an active region 41 is formed at the boundary between the memory cell region and the peripheral circuit region. The active region 41 is defined by the isolation trench 2 as in the other active regions 40, but no circuit element is formed in the active region 41, and exclusively serves to separate the memory cell region from the peripheral circuit region. I'm in charge. Hereinafter, the active region 41 is referred to as “isolation active region”. FIG. 7 is a schematic diagram of a chip layout of the semiconductor memory device according to the first embodiment. As shown in the figure, the isolation active region 41 is formed in a frame shape surrounding the memory cell region.

  By forming the isolation active region 41 at the boundary between the memory cell region and the peripheral circuit region, the field shield electrode in the memory cell region (the N-type conductive film 4n in the N well region 10 for the memory cell) and The field shield electrodes in the peripheral circuit region (N-type conductive films 4n and 4p in the peripheral well N-well region 20 and P-well region 30) are electrically isolated. As a result, the field shield electrode in the memory cell region and the field shield electrode in the peripheral circuit region can be set to different voltages as required (can be made floating) to improve the performance of the semiconductor memory device. Can contribute.

  For example, the voltage of the field shield electrode in the peripheral circuit region is 0 V (ground potential) or in a floating state, and the voltage of the field shield electrode in the memory cell region is about half of the power supply voltage Vcc (for example, 1.5 V) (for example, 0. 6 to 0.75). Since the field shield electrode in the memory cell region functions as the second electrode (cell plate electrode) of the capacitors C1 and C2 of the DRAM cell, the voltage Vcc is applied to the first electrode (storage electrode) by setting it as such. When storing any of 0V, the voltage applied to the dielectric layer (inner wall oxide film 3) can be minimized, and the capacitance of the capacitors C1 and C2 can be increased by reducing the thickness of the dielectric layer. Further, since the N-type conductive film 4n is fixed at a positive potential, the parasitic PMOS transistor formed thereunder is hardly turned on, and there is an advantage that charge leakage can be prevented.

  Next, a method for manufacturing the semiconductor memory device according to the present embodiment shown in FIG. 6 will be described. 8 to 21 are process diagrams for explaining the manufacturing method of the semiconductor memory device. Hereinafter, the manufacturing method will be described with reference to these drawings.

  First, a silicon substrate 1 is prepared, and a silicon oxide film (pad oxide film) 81 having a film thickness of about 5 nm to 30 nm is formed on the upper surface thereof. Next, a silicon nitride film having a thickness of about 50 nm to 200 nm is deposited and patterned using a photolithography technique to form a silicon nitride film hard mask 82 having an opening over the formation region of the isolation trench 2. . Then, an isolation trench 2 having a depth of about 150 nm to 500 nm is formed on the silicon substrate 1 by etching using the hard mask 82 as a mask. Thereby, an active region 40 and an isolation active region 41 in the silicon substrate 1 are defined. Thereafter, an inner wall oxide film 3 having a film thickness of about 5 nm to 30 nm is formed on the inner wall of the isolation trench 2 by a thermal oxidation method (FIG. 8).

Next, using a photolithography technique, a resist mask 83 having openings in the formation areas of the capacitors C1 and C2 of the DRAM cell is formed. For example, boron as a P-type dopant under conditions of energy 10 keV and dose amount 5E14 / cm 2 or more. Ions are implanted. At this time, since the hard mask 82 or the resist mask 83 serves as a mask, boron ions are not implanted into the silicon substrate 1 other than the formation regions of the capacitors C1 and C2. As a result, boron ions are implanted only into the inner wall and bottom of isolation trench 2 in the formation region of capacitors C1 and C2, and P-type capacitor electrode diffusion layer 16 is formed there (FIG. 9).

  Subsequently, a polysilicon film (non-doped polysilicon film) 4 not doped with impurities is deposited. In the present embodiment, the thickness of depositing the non-doped polysilicon film 4 is set to the depth of the isolation trench 2 and the hard mask 82 so that all the isolation trenches 2 are completely filled with the non-doped polysilicon film 4. The thickness is made thicker than the sum of the thickness of the pad oxide film 81 (FIG. 10).

  Then, using a CMP (Chemical Mechanical Polishing) technique, the non-doped polysilicon film 4 on the hard mask 82 is removed (FIG. 11). Further, by performing etch back by anisotropic etching, the height of the upper surface of the non-doped polysilicon film 4 is made lower than the surface of the silicon substrate 1 (FIG. 12).

  Thereafter, a silicon oxide film 85 is deposited by a high density plasma chemical vapor deposition (HDP-CVD) method (FIG. 13). Next, the cap oxide film 5 is formed on the non-doped polysilicon film 4 in the isolation trench 2 by removing the silicon oxide film 85 on the hard mask 82 by CMP using the hard mask 82 as a stopper (FIG. 14). ). Then, after adjusting the height of the upper surface of the cap oxide film 5 by etching using hydrofluoric acid, the hard mask 82 is removed by etching using hot phosphoric acid, and the pad oxide film 81 is further etched by using hydrofluoric acid. Is removed (FIG. 15).

Next, a resist mask 86 having an opening on the formation region of the P well region 30 is formed by using a photolithography technique, and boron, which is a P-type dopant, is ion-implanted using the resist mask 86 as a mask. Region 30 is formed (FIG. 16). This boron ion implantation is performed in multiple stages by changing the implantation conditions. More specifically, for example, implantation with an energy of 300 keV and a dose of 1E13 / cm 2 , implantation with an energy of 100 keV and a dose of 6E12 / cm 2 , and implantation with an energy of 10 keV and a dose of 1E13 / cm 2. Perform by combination. By this ion implantation, boron is also implanted into the non-doped polysilicon film 4 in the P well region 30, so that the non-doped polysilicon film 4 in the P well region 30 becomes a P-type conductive film 4p.

Subsequently, using a photolithography technique, a resist mask 87 having openings on the formation regions of the N well regions 10 and 20 is formed, and phosphorus as an N-type dopant is ion-implanted using the resist mask 87 as a mask. As a result, an N well region 10 is formed in the memory cell region of the silicon substrate 1, and an N well region 20 is formed in the peripheral circuit region (FIG. 17). This phosphorus ion implantation is also performed in multiple stages by changing the implantation conditions. More specifically, for example, energy 600 keV, and implantation of a dose of 1E13 / cm 2, energy 300 keV, and implantation at a dose of 6E12 / cm 2, energy 30 keV, the injection of a dose of 1E13 / cm 2 Perform by combination. Also, by this ion implantation, phosphorus is also implanted into the non-doped polysilicon film 4 in the N well regions 10 and 20, so that the non-doped polysilicon film 4 in the N well regions 10 and 20 is formed of an N-type conductive film 4n. Become.

  Further, at the time of this phosphorus implantation, a high concentration is implanted at a depth near the bottom of the isolation trench 2. By doing so, the bottom portion of the isolation trench 2 in the capacitor electrode diffusion layer 16 is canceled out, and the capacitor electrode diffusion layer 16 remains only in the side wall portion of the isolation trench 2 as shown in FIG. As a result, in the completed semiconductor memory device, leakage current between adjacent DRAM cells with the isolation trench 2 interposed therebetween is prevented.

  Thereafter, a silicon oxide film and polysilicon as an electrode material are sequentially deposited on the upper surface of the silicon substrate 1 and patterned by using a photolithography technique, whereby the gate oxide films 11, 21, 31 and the gate electrodes 12, 22 are deposited. , 32 are formed (FIG. 18).

  Subsequently, after forming LDD (Lightly Doped Drain) layers of the access transistors T1, T2, the peripheral PMOS transistor Tp, and the peripheral NMOS transistor Tn by ion implantation, a silicon nitride film is deposited on the entire surface and etched back. Side walls 13, 23, 33 are formed on the side surfaces of the gate electrodes 12, 22, 32, respectively. Further, source / drain regions 14, 15, 24, and 34 of the access transistors T1 and T2, the peripheral PMOS transistor Tp, and the peripheral NMOS transistor Tn are formed by ion implantation (FIG. 19). When performing these ion implantations, it is necessary to change the conductivity type of ions to be implanted between the formation region of the NMOS transistor (peripheral NMOS transistor Tn) and the formation region of the PMOS transistor (access transistors T1, T2 and peripheral PMOS transistor Tp). However, this is possible by using photolithography technology. That is, at the time of ion implantation into the formation region of the NMOS transistor, a photoresist covering the formation region of the PMOS transistor is formed and used as an implantation mask, and conversely at the time of ion implantation into the formation region of the PMOS transistor. In this case, a photoresist covering the formation region of the PMOS transistor may be used as a mask.

  Through the above steps, capacitors C1 and C2 and access transistors T1 and T2 connected thereto are formed in the memory cell region, and a peripheral PMOS transistor Tp and a peripheral NMOS transistor Tn are formed in the peripheral circuit region.

  Thereafter, a metal film such as cobalt is deposited on the region to be silicidized and subjected to heat treatment, and the unreacted metal film is removed, whereby the gate electrodes 12, 22, 32 and the source / drain regions 14, 15, 24 are removed. , 34, silicides 12s, 22s, 32s, 14s, 15s, 24s, 34s are formed in a self-aligning manner (FIG. 20).

  Then, an interlayer insulating film 6 is formed from a silicon oxide film, and the upper surface thereof is flattened. Then, a contact hole is formed in the interlayer insulating film 6 by etching using a photolithography technique (FIG. 21). Then, contacts 7 (including contacts 7b, 7n, 7p, etc.) are formed therein, and wiring 8 (including bit line 8b) is formed thereon, thereby forming the semiconductor memory device shown in FIG. The

  Here, in element isolation using the field shield structure, the field shield electrode in the P well region has P-type conductivity, and the field shield electrode in the N well region has N-type conductivity. Then, it has been found that the polarities of the bottom and inner walls of the isolation trench 2 are not easily reversed, and the element isolation capability of the field shield structure is improved (for example, see Patent Document 2). In the above manufacturing method, an N-type dopant is introduced into the non-doped polysilicon film 4 in each of the N well regions 10 and 20 by ion implantation for forming the N well regions 10 and 20 (FIG. 17). P-type dopant is introduced into the non-doped polysilicon film 4 in the P well region 30 by ion implantation for forming (FIG. 16). Therefore, the field shield electrode in the N well regions 10 and 20 becomes the N-type conductive film 4n, and the field shield electrode in the P well region 30 becomes the P-type conductive film 4p, which satisfies the above conditions.

  FIG. 22 is a diagram showing an example of the contact layout in the memory cell region of the semiconductor memory device according to the first embodiment, and is a top view of the outer peripheral portion of the memory cell region. In the figure, elements corresponding to those shown in FIG. 6 are denoted by the same reference numerals. As described above, in the present embodiment, the isolation active region 41 is formed around the memory cell region (boundary with the peripheral circuit region) so as to surround the memory cell region (FIG. 7). .

  As shown in FIG. 22, in this embodiment, the contact 7 w (word line contact) connected to the gate electrode 12 that is a word line is laid out on the end portion in the longitudinal direction of the gate electrode 12. The contact 7c (cell plate contact) connected to the N-type conductive film 4n, which is a cell plate electrode, is N-type conductive at the end along the side perpendicular to the extending direction of the gate electrode 12 in the memory cell region. It is laid out on the film 4n. By laying out the cell plate contact 7c at the end of the memory cell region in this way, an increase in area penalty due to the cell plate contact 7c can be suppressed, and it is possible to contribute to higher density of DRAM cells in the memory cell region.

  FIGS. 23 and 24 are diagrams showing other examples of contact layouts in the memory cell region of the semiconductor memory device according to the first embodiment. As described above, in the semiconductor memory device according to the present embodiment, the N-type conductive film 4n is embedded in the isolation trench 2 that runs perpendicular to the gate electrode 12, and therefore runs parallel to the gate electrode 12. The isolation trenches 2 are electrically connected to each other. Therefore, it is not necessary to provide the cell plate contact 7c corresponding to each of the isolation trenches 2 that run parallel to the gate electrode 12 as shown in FIG. Therefore, for example, as shown in FIG. 23, the cell plate contact 7 c can be disposed in every other isolation trench 2 that runs parallel to the gate electrode 12. Further, if the conditions are set, theoretically, the cell plate contact 7c can be provided only at the corners of the memory cell region (for example, the four corners of the memory cell region) as shown in FIG. Thereby, the area penalty due to the cell plate contact 7c can be further reduced, which can greatly contribute to the high density of DRAM cells in the memory cell region.

  In the above description, the description of the connection between the DRAM cells formed in the plurality of active regions 40 is omitted. However, the present invention also applies to the normal DRAM cell shown in FIG. The present invention can also be applied to the complementary DRAM cell shown in FIG.

<Embodiment 2>
FIG. 25 is a diagram showing the configuration of the semiconductor memory device according to the second embodiment, and is a cross-sectional view of the vicinity of the boundary between the memory cell region and the peripheral circuit region in the semiconductor memory device. In this figure, the same elements as those shown in FIG. 6 are denoted by the same reference numerals, so detailed description thereof will be omitted here, and parts of features different from those of the apparatus of FIG. 6 will be mainly described here. Explained.

  First, in the semiconductor memory device according to the second embodiment, the isolation active region 41 formed at the boundary between the memory cell region and the peripheral circuit region of the device of FIG. 6 is not formed. The isolation trench 2 at the boundary is formed wider than the isolation trench 2 in the memory cell region (the leftmost isolation trench 2 in FIG. 25). In the peripheral circuit region, the isolation trench 2 at the boundary between the N well region 20 and the P well region 30 is the isolation trench 2 in the N well region 20 (the rightmost isolation trench 2 in FIG. 25) and the P well. The width is wider than the isolation trench 2 (not shown) in the region 30.

  Hereinafter, for convenience of explanation, the isolation trench 2 at the boundary between the memory cell region and the peripheral circuit region, which is a wide portion (first trench portion) in the isolation trench 2, and the N well region 20 and the P well region in the peripheral circuit region The isolation trench 2 at the boundary with 30 is generically referred to as a “wide isolation trench 2”, and the other narrow trench (second trench portion) isolation trench 2 (in the memory cell region, in the N well region 20) And those in the P-well region 30) may be collectively referred to as “narrow isolation trench 2”.

  Inside these wide isolation trenches 2, the conductive film as the field shield electrode is separated into one inner wall side and the other inner wall side of the isolation trench 2. That is, as shown in FIG. 25, in the isolation trench 2 at the boundary between the memory cell region and the peripheral circuit region, the field shield electrode includes the N-type conductive film 4n on the memory cell region side and the P-type on the peripheral circuit region side. It is separated from the conductive film 4p. Similarly, in the isolation trench 2 at the boundary between the N well region 20 and the P well region 30 in the peripheral circuit region, the N type conductive film 4n on the N well region 20 side and the P type conductive film on the P well region 30 side. It is separated into 4p. Accordingly, in these wide isolation trenches 2, the cap oxide film 5 reaches the bottom of the isolation trench 2 at the center of the isolation trench 2.

  Narrow isolation trenches 2 (in the memory cell region, in the N well region 20 and in the P well region 30) are each integrally filled with a conductive film as in the first embodiment. ing.

  According to the present embodiment, the field shield electrode in the memory cell region, the field shield electrode in the P well region 30 in the peripheral circuit region, and the field shield electrode in the N well region 20 are separated from each other. Different voltages can be set as necessary (can be set in a floating state), which can contribute to improving the performance of the semiconductor memory device. For example, the field shield electrode in the N well region 20 in the peripheral circuit region is set to about −1V to 0V, the field shield electrode in the P well region 30 is set to about 0V to 1V, and the memory cell region The voltage of the field shield electrode can be set to about half (for example, 0.6 to 0.75) of the power supply voltage Vcc (for example, 1.5 V).

  As shown in FIG. 25, in the present embodiment, the N-type conductive film 4n and the P-type conductive film 4p in the wide isolation trench 2 each have a rounded surface. The contacts 7n (cell plate contacts 7c in the memory cell region) and the contacts 7p connected to them are laid out so as to be connected to the N-type conductive film 4n and the P-type conductive film 4p in the wide isolation trench 2. The Since the surfaces of the N-type conductive film 4n and the P-type conductive film 4p in the wide isolation trench 2 are rounded, as schematically shown in FIG. 26, the N-type conductive film 4n and the contacts 7n connected thereto are provided. The contact area with (or the cell plate contact 7c) and the contact area between the P-type conductive film 4p and the contact 7p connected thereto are increased. Therefore, those connection resistances can be reduced, and a stable connection (connection with little variation in connection resistance) can be achieved.

  In FIG. 26, for convenience of explanation, the contacts 7p and 7n are illustrated as facing each other. However, in the actual layout, the contacts are formed in the isolation trench 2 as shown in the top view of FIG. 7p and 7n may be laid out so as to be displaced from each other in the direction in which the isolation trench 2 extends. In that case, even when the distance between the N-type conductive film 4n and the P-type conductive film 4p separated from each other is small, the distance between the contacts 7p and 7n can be kept large, and the contacts 7p and 7n can be formed. It can be done easily.

  Next, a manufacturing method of the semiconductor memory device according to the present embodiment shown in FIG. 25 will be described. 28 to 39 are process diagrams for explaining the method of manufacturing the semiconductor memory device. Hereinafter, the manufacturing method will be described with reference to these drawings.

  First, the isolation trench 2 is formed in the silicon substrate 1 by the same method as in the first embodiment. That is, the pad oxide film 81 and the hard mask 82 are formed on the upper surface of the silicon substrate 1, and the isolation trench 2 is formed by etching using the pad oxide film 81 and the hard mask 82 as a mask. However, in the present embodiment, it is not necessary to form the isolation active region 41 at the boundary between the memory cell region and the peripheral circuit region. Further, the isolation trench 2 at the boundary between the memory cell region and the peripheral circuit region and at the boundary between the N well region 20 and the P well region 30 in the peripheral circuit region is formed wider than the isolation trench 2 in other portions. . Thereafter, an inner wall oxide film 3 is formed on the inner wall of the isolation trench 2 (FIG. 28).

  Next, a resist mask 83 having openings in the formation regions of the capacitors C1 and C2 of the DRAM cell is formed by using a photolithography technique, and ions of boron as a P-type dopant are implanted. Thereby, P type capacitor electrode diffusion layer 16 is formed on the inner wall and bottom of isolation trench 2 in the formation region of capacitors C1 and C2 (FIG. 29).

  Subsequently, a non-doped polysilicon film 4 is deposited. In the present embodiment, the deposited film thickness of the non-doped polysilicon film 4 is set to 1/2 or more of the width of the narrow isolation trench 2 and less than 1/2 of the width of the wide isolation trench 2. As a result, the narrow isolation trench 2 is completely filled with the non-doped polysilicon film 4, and the wide isolation trench 2 is not completely filled with the non-doped polysilicon film 4, leaving a deep dent at the center (FIG. 30).

  Then, using the CMP technique, the non-doped polysilicon film 4 on the hard mask 82 is removed (FIG. 31). Further, etch back is performed by anisotropic etching, so that the height of the upper surface of the non-doped polysilicon film 4 is made lower than the surface of the silicon substrate 1. However, in this embodiment, this etch back is performed until the bottom reaches the center of the wide isolation trench 2. Since the non-doped polysilicon film 4 in the wide isolation trench 2 has a deep recess at the center, even if the etch back reaches the bottom at the center of the isolation trench 2, the non-doped polysilicon film 4 is formed on the inner wall of the isolation trench 2. Will remain. The remaining non-doped polysilicon film 4 has a rounded surface like a sidewall (for example, the sidewall 13 in FIG. 25) formed on the side surface of the electrode (FIG. 32). As a result, the effect described with reference to FIG. 26 is obtained.

  Thereafter, a silicon oxide film 85 is deposited by a high-density plasma CVD method (FIG. 33), and the silicon oxide film 85 on the hard mask 82 is removed by a CMP method, so that the non-doped polysilicon film 4 in the isolation trench 2 is formed. A cap oxide film 5 is formed (FIG. 34). Then, after adjusting the height of the upper surface of the cap oxide film 5 by etching using hydrofluoric acid, the hard mask 82 is removed by etching using hot phosphoric acid, and the pad oxide film 81 is further etched by using hydrofluoric acid. Is removed (FIG. 35).

  Then, a resist mask 86 having an opening on the formation region of the P well region 30 is formed, and boron, which is a P-type dopant, is ion-implanted using the resist mask 86 as a mask, thereby forming the P well region 30 in the silicon substrate 1 ( FIG. 36). Further, by this ion implantation, the non-doped polysilicon film 4 in the P well region 30 becomes a P-type conductive film 4p.

  Subsequently, a resist mask 87 having an opening on the formation region of the N well regions 10 and 20 is formed, and phosphorus, which is an N-type dopant, is ion-implanted using the resist mask 87 as a mask, thereby simultaneously forming the N well regions 10 and 20. (FIG. 37). By this ion implantation, the non-doped polysilicon film 4 in the N well regions 10 and 20 becomes the N-type conductive film 4n. In this phosphorus implantation, a high concentration is implanted at a depth near the bottom of the isolation trench 2. Thereby, the bottom portion of the isolation trench 2 in the capacitor electrode diffusion layer 16 is canceled out, and the capacitor electrode diffusion layer 16 remains only on the side wall portion of the isolation trench 2 as shown in FIG.

  After that, gate oxide films 11, 21, 31 and gate electrodes 12, 22, 32 are formed by the same method as in the first embodiment, LDD implantation is performed, and sidewalls 13, 23, 33 are formed. Source / drain regions 14, 15, 24, 34 are formed. Further, silicide 12s, 22s, 32s, 14s, 15s, 24s, and 34s are formed on the gate electrodes 12, 22, and 32 and the source / drain regions 14, 15, 24, and 34 (FIG. 38).

  Then, an interlayer insulating film 6 is formed, contact holes are formed therein (FIG. 39), contacts 7 including bit line contacts 7b (including contacts 7b, 7n, 7p, 7c, 7w, etc.) are formed, By forming wiring 8 (including bit line 8b) thereon, the semiconductor memory device shown in FIG. 25 is formed.

  FIG. 40 is a diagram showing an example of the layout of contacts in the memory cell region of the semiconductor memory device according to the second embodiment, and is a top view of the outer periphery of the memory cell region. In the figure, elements corresponding to those shown in FIG. 25 are denoted by the same reference numerals. As described above, in the present embodiment, as shown in FIG. 40, a wide isolation trench 2 is formed at the outer periphery of the memory cell region (boundary with the peripheral circuit region), and the field shield electrode inside the memory cell region The n-type conductive film 4n on the side and the p-type conductive film 4p on the peripheral circuit region side are separated (FIG. 7).

  As shown in FIG. 40, the cell plate contact 7c connected to the N-type conductive film 4n is laid out in the end portion along the side perpendicular to the extending direction of the gate electrode 12 in the memory cell region, that is, in the wide isolation trench 2. The The contact 7p connected to the P-type conductive film 4p is also laid out in the wide isolation trench 2. Since the N-type conductive film 4n and the P-type conductive film 4p in the wide isolation trench 2 have rounded surfaces, as described with reference to FIG. 26, the N-type conductive film 4n and the cell in the memory cell region The contact area with the plate contact 7c and the contact area between the P-type conductive film 4p in the peripheral circuit region and the contact 7p connected thereto are increased. Therefore, those connection resistances can be reduced, and a stable connection (connection with little variation in connection resistance) can be achieved.

  Also in the second embodiment, since the N-type conductive film 4n is embedded in the isolation trench 2 in the memory cell region that runs perpendicular to the gate electrode 12, the isolation trenches 2 that run parallel to the gate electrode 12 Are electrically connected to each other. Therefore, it is not necessary to provide the cell plate contact 7 c in all the isolation trenches 2 that run parallel to the gate electrode 12. For example, as shown in FIG. 40, every other cell plate contact 7c may be disposed only at the corners of the memory cell region (for example, the four corners of the memory cell region). .

<Embodiment 3>
FIG. 41 is a diagram showing the configuration of the semiconductor memory device according to the third embodiment, and is a cross-sectional view in the vicinity of the boundary between the memory cell region and the peripheral circuit region in the semiconductor memory device. In this figure, the same elements as those shown in FIG. 6 are denoted by the same reference numerals, so detailed description thereof will be omitted here, and parts of features different from those of the apparatus of FIG. 6 will be mainly described here. Explained.

  First, in the semiconductor memory device according to the third embodiment, the inner wall oxide film 3 (the portion to be a dielectric layer of the capacitors C1 and C2 in the inner wall oxide film 3) is thin in the formation region of the capacitors C1 and C2 of the DRAM cell. The inner wall oxide film 3 in this region is formed thick. That is, as shown in FIG. 41, a thin inner wall oxide film 3a is formed in the isolation trench 2 in the formation region of the capacitors C1 and C2 of the DRAM cell, and the isolation trench 2 in other regions (for example, peripheral circuit region). Inside, a thick inner wall oxide film 3b is formed. Except for this, the semiconductor memory device has the same configuration as that of the first embodiment. The film thickness of the thin inner wall oxide film 3a is, for example, about 1 to 2 nm, and the film thickness of the thick inner wall oxide film 3b is, for example, 5 to 30 nm.

  According to the present embodiment, since the dielectric layers of the capacitors C1 and C2 of the DRAM cell are the thin inner wall oxide films 3a, the capacitances of the capacitors C1 and C2 are increased, and the reliability of the DRAM cell is improved. Further, since the field shield electrode (N-type conductive film 4n or P-type conductive film 4p) is buried in the isolation trenches 2 other than the peripheral circuit region through the thick inner wall oxide film 3b, the active region and Leakage current between the field shield electrodes can be prevented, and the effect of improving the element isolation capability of the field shield structure can be obtained.

  Next, a method for manufacturing the semiconductor memory device according to the present embodiment shown in FIG. 41 will be described. 42 to 45 are process diagrams for explaining the method of manufacturing the semiconductor memory device. Hereinafter, the manufacturing method will be described with reference to these drawings.

  First, the isolation trench 2 is formed in the silicon substrate 1 by the same method as in the first embodiment. That is, the pad oxide film 81 and the hard mask 82 are formed on the upper surface of the silicon substrate 1, and the isolation trench 2 is formed by etching using the pad oxide film 81 and the hard mask 82 as a mask. Thereafter, a first inner wall oxidation process for forming an inner wall oxide film 3 on the inner wall of the isolation trench 2 is performed (FIG. 42). In this first inner wall oxidation treatment, the inner wall oxide film 3 to be formed has a thickness of 5 to 30 nm.

  Next, a resist mask 83 having openings in the formation regions of the capacitors C1 and C2 of the DRAM cell is formed by photolithography, and the inner wall oxide film 3 in the formation regions of the capacitors C1 and C2 is formed by etching using the resist mask 83 as a mask. It is removed (FIG. 43). Similarly, ions of boron as a P-type dopant are implanted using the resist mask 83 as a mask. Thereby, P-type capacitor electrode diffusion layer 16 is formed on the inner wall and bottom of isolation trench 2 in the formation region of capacitors C1 and C2 (FIG. 44).

  After removing the resist mask 83, a second inner wall oxidation process is performed to form the inner wall oxide film 3 on the inner wall of the isolation trench 2 again. In the second inner wall oxidation treatment, the inner wall oxide film 3 to be formed is made as thin as about 1 to 2 nm. As a result, the inner wall oxide film 3 in the formation region of the capacitors C1 and C2 becomes a thin inner wall oxide film 3a formed by the second inner wall oxidation process, and the inner wall oxide film 3 in the other regions is the first and first inner wall oxide films 3a. This results in a thick inner wall oxide film 3b formed by both of the inner wall oxidation processes (FIG. 45).

  Thereafter, DRAM cells (access transistors T1, T2 and capacitors C1, C2) are formed in the memory cell region by the same procedure as that described in the first embodiment with reference to FIGS. The peripheral PMOS transistor Tp and the peripheral NMOS transistor Tn are formed in the region, and the contact 7 and the wiring 8 connected to them are formed, whereby the semiconductor memory device shown in FIG. 41 is formed.

  As described above, the semiconductor memory device according to the present embodiment is implemented except that the thickness of the inner wall oxide film 3 is different between the portions serving as the dielectric layers of the capacitors C1 and C2 and the other portions. This is the same as the first embodiment. That is, also in this embodiment, the isolation trenches 2 that run parallel to the gate electrode 12 are electrically connected to each other. Therefore, the layout of the cell plate contact 7c may be the same as that of the first embodiment (FIGS. 22 to 24).

  Further, in the above description, the thickness of inner wall oxide film 3 is made different between the portions serving as the dielectric layers of capacitors C1 and C2 and the other portions as compared with the semiconductor memory device of the first embodiment (FIG. 6). However, the present embodiment can also be applied to the semiconductor memory device of the second embodiment (FIG. 25).

<Embodiment 4>
FIG. 46 is a diagram showing the configuration of the semiconductor memory device according to the fourth embodiment, and is a cross-sectional view in the vicinity of the boundary between the memory cell region and the peripheral circuit region in the semiconductor memory device. In this figure, the same elements as those shown in FIG. 6 are denoted by the same reference numerals, so detailed description thereof will be omitted here, and parts of features different from those of the apparatus of FIG. 6 will be mainly described here. Explained.

  First, in the semiconductor memory device according to the fourth embodiment, the inner surface (inner wall and bottom) of isolation trench 2 that defines active region 40 is roughened and has minute irregularities. Except for this, the semiconductor memory device has the same configuration as that of the first embodiment.

  According to the present embodiment, since the side wall of the active region 40 is roughened, the effective area of the capacitors C1 and C2 having the capacitor electrode diffusion layer 16 formed on the side wall as a storage electrode is increased. Therefore, the capacitances of the capacitors C1 and C2 can be increased, and the effect of improving the reliability of the DRAM cell can be obtained. In the present embodiment, the inner surface of the isolation trench 2 in the peripheral circuit region is also roughened, but normally the silicon substrate 1 and the field shield electrode (N-type conductive film 4n and P-type conductive material in the peripheral circuit region). And the potential of the leakage current between the silicon substrate 1 and the field shield electrode does not occur.

  Next, a manufacturing method of the semiconductor memory device according to the present embodiment shown in FIG. 46 will be described. 47 to 52 are process diagrams for explaining the manufacturing method of the semiconductor memory device. Hereinafter, the manufacturing method will be described with reference to these drawings.

  First, the isolation trench 2 is formed in the silicon substrate 1 by the same method as in the first embodiment. That is, the pad oxide film 81 and the hard mask 82 are formed on the upper surface of the silicon substrate 1, and the isolation trench 2 is formed by etching using the same as a mask (FIG. 47).

  Then, polysilicon fine particles 88 (hereinafter referred to as “roughened polysilicon”) are formed on the entire surface of the silicon substrate 1 (FIG. 48). At this time, the roughened polysilicon 88 is also formed on the inner surface of the isolation trench 2 to form fine irregularities on the inner surface. Thereby, the inner surface of the isolation trench 2 is roughened. The roughened polysilicon 88 is described in, for example, Reference Documents (Applied Physics, Vol. 61, No. 11, 1992, pp 1147-1151, “Mechanism for forming hemispherical grain polysilicon”, Toru Toru, etc.) This method can be used.

  Thereafter, an inner wall oxide film 3 is formed on the inner wall of the roughened isolation trench 2 (FIG. 49). At this time, since the roughened polysilicon 88 is formed on the upper surface of the hard mask 82, a silicon oxide film integrated with the inner wall oxide film 3 is also formed on the hard mask 82 as shown in FIG. The

  Next, a resist mask 83 having openings in the formation areas of the capacitors C1 and C2 of the DRAM cell is formed, and boron as a P-type dopant is implanted using the resist mask 83 as a mask. Thereby, P-type capacitor electrode diffusion layer 16 is formed on the inner wall and bottom of isolation trench 2 in the formation region of capacitors C1 and C2 (FIG. 50).

  Subsequently, a non-doped polysilicon film 4 is deposited, and the inside of the isolation trench 2 is filled with the non-doped polysilicon film 4 (FIG. 51). Then, the CMP technique is used to remove the non-doped polysilicon film 4, the roughened polysilicon 88 and the silicon oxide film (formed simultaneously with the inner wall oxide film 3) on the hard mask 82 (FIG. 52).

  Thereafter, DRAM cells (access transistors T1 and T2 and capacitors C1 and C2) are formed in the memory cell region by the same procedure as that described in the first embodiment with reference to FIGS. The peripheral PMOS transistor Tp and the peripheral NMOS transistor Tn are formed in the region, and the contact 7 and the wiring 8 connected to them are formed, whereby the semiconductor memory device shown in FIG. 46 is formed.

  As described above, the semiconductor memory device according to the present embodiment is the same as that of the first embodiment except that the inner surface of isolation trench 2 is roughened by roughened polysilicon 88. . That is, also in this embodiment, the isolation trenches 2 that run parallel to the gate electrode 12 are electrically connected to each other. Therefore, the layout of the cell plate contact 7c may be the same as that of the first embodiment (FIGS. 22 to 24).

  In the above description, the configuration in which the inner surface of the isolation trench 2 is roughened in the semiconductor memory device of the first embodiment (FIG. 6) is shown. However, the present embodiment is a semiconductor memory device of the second embodiment. (FIG. 25) is applicable.

<Embodiment 5>
In the fifth embodiment, a modification of the above-described fourth embodiment is shown. FIG. 53 is a diagram showing the configuration of the semiconductor memory device according to the fifth embodiment, and is a cross-sectional view in the vicinity of the boundary between the memory cell region and the peripheral circuit region in the semiconductor memory device. In this figure, the same elements as those shown in FIGS. 6 and 46 are denoted by the same reference numerals, and detailed description thereof will be omitted here.

  In the fourth embodiment, the entire inner surface (inner wall and bottom) of the isolation trench 2 is roughened. However, in the fifth embodiment, only the inner wall of the isolation trench 2 is rough as shown in FIG. And the bottom is not roughened. Except for this, it has the same configuration as the semiconductor memory device of the fourth embodiment.

  Also in the present embodiment, since the side wall of the active region 40 is roughened, an effect of increasing the capacitance of the capacitors C1 and C2 using the capacitor electrode diffusion layer 16 formed on the side wall as a storage electrode is obtained. It is done. In addition, since the bottom surface of the isolation trench 2 is not roughened, an effect of suppressing leakage current between adjacent DRAM cells across the isolation trench 2 can be obtained.

  Next, a manufacturing method of the semiconductor memory device according to the present embodiment shown in FIG. 53 will be described. 54 to 59 are process diagrams for explaining the manufacturing method of the semiconductor memory device. Hereinafter, the manufacturing method will be described with reference to these drawings.

  First, as in the fourth embodiment, the pad oxide film 81 and the hard mask 82 are formed on the upper surface of the silicon substrate 1, and the isolation trench 2 is formed by etching using the pad oxide film 81 and the hard mask 82 as a mask. Then, roughened polysilicon 88 is formed on the entire surface of the silicon substrate 1 (FIG. 54). At this time, the roughened polysilicon 88 is formed on the inner surface (inner wall and bottom) of the isolation trench 2, so that the inner surface is roughened.

  In the present embodiment, here, etch back by dry etching is performed on the entire surface of the silicon substrate 1. As a result, the roughened polysilicon 88 on the upper surface of the hard mask 82 and the bottom of the isolation trench 2 is removed, but the roughened polysilicon 88 on the inner wall of the isolation trench 2 remains without being removed (FIG. 55).

  Thereafter, the inner wall oxide film 3 is formed on the inner wall of the roughened isolation trench 2 (FIG. 56). Since the roughened polysilicon 88 on the upper surface of the hard mask 82 is removed, a silicon oxide film integral with the inner wall oxide film 3 is not formed on the hard mask 82 as shown in FIG.

  Next, a resist mask 83 having openings in the formation areas of the capacitors C1 and C2 of the DRAM cell is formed, and boron as a P-type dopant is implanted using the resist mask 83 as a mask. Thereby, P-type capacitor electrode diffusion layer 16 is formed on the inner wall and bottom of isolation trench 2 in the formation region of capacitors C1 and C2 (FIG. 57).

  Subsequently, as in the fourth embodiment, a non-doped polysilicon film 4 is deposited and filled in the isolation trench 2 with the non-doped polysilicon film 4 (FIG. 58). Then, using the CMP technique, the non-doped polysilicon film 4 on the hard mask 82 is removed (FIG. 59).

  Thereafter, DRAM cells (access transistors T1 and T2 and capacitors C1 and C2) are formed in the memory cell region by the same procedure as that described in the first embodiment with reference to FIGS. The peripheral PMOS transistor Tp and the peripheral NMOS transistor Tn are formed in the region, and the contact 7 and the wiring 8 connected to them are formed, whereby the semiconductor memory device shown in FIG. 53 is formed.

  Here, in the fourth embodiment, as described with reference to FIGS. 51 and 52, in the CMP process for removing the non-doped polysilicon film 4 on the hard mask 82, the roughened polysilicon 88 and the (inner wall oxide film). The silicon oxide film formed at the same time as 3 is also required to be removed from the hard mask 82. The CMP process at this time is performed under conditions suitable for polishing the silicon oxide film. Therefore, when polishing is performed with the roughened polysilicon 88 remaining on the hard mask 82 serving as a CMP stopper, There is a concern that the roughened polysilicon 88 and the silicon oxide film and the slurry remaining entangled with the fine unevenness caused by the roughened polysilicon 88 and the remaining slurry cannot be removed without completely removing the surfaced polysilicon 88. In the CMP process, scratches may occur due to the removed roughened polysilicon 88, which is a problem.

  In contrast, in this embodiment, prior to the CMP process (FIG. 59) for removing the non-doped polysilicon film 4 on the hard mask 82, etch back by dry etching for removing the roughened polysilicon 88 on the hard mask 82. A process (FIG. 55) is performed. Therefore, at the stage of the CMP process, the roughened polysilicon 88 and the silicon oxide film formed simultaneously with the inner wall oxide film 3 are not on the hard mask 82. Therefore, the above-described problem of the fourth embodiment is not accompanied.

<Embodiment 6>
In the sixth embodiment, a modification of the above-described fourth or fifth embodiment is shown. As described above, in the fourth and fifth embodiments, the inner wall of the isolation trench 2 in the memory cell region is roughened, so that the capacitance of the capacitors C1 and C2 of the DRAM cell is increased. Although the inner wall of isolation trench 2 in the peripheral circuit region is also roughened, depending on the voltage conditions of silicon substrate 1 and field shield electrodes (N-type conductive film 4n and P-type conductive film 4p), isolation trench 2 May cause leakage current between the field shield electrode in the peripheral circuit region and the silicon substrate 1 (as described above, the field shield electrode in the peripheral circuit region and the field shield electrode in the peripheral circuit region). Is not a problem if is set to approximately the same potential).

  In other words, it may be desirable that the inner wall of the isolation trench 2 in the peripheral circuit region is not roughened. Therefore, in the present embodiment, a technique is proposed in which only the inner wall of the isolation trench 2 in the memory cell region is roughened and the inner wall of the isolation trench 2 in the peripheral circuit region is not roughened.

  FIG. 60 is a diagram showing the configuration of the semiconductor memory device according to the sixth embodiment, and is a cross-sectional view near the boundary between the memory cell region and the peripheral circuit region in the semiconductor memory device. In this figure, the same elements as those shown in FIGS. 6 and 46 are denoted by the same reference numerals, and detailed description thereof will be omitted here.

  As shown in FIG. 60, in this embodiment, the inner wall of isolation trench 2 in the memory cell region is roughened, whereas the inner wall of isolation trench 2 in the peripheral circuit region is not roughened. . Except for this, it has the same configuration as the semiconductor memory device of the fifth embodiment.

  In the memory cell region, since the inner wall of the isolation trench 2 (side wall of the active region 40) is roughened, an effect of increasing the capacitance of the capacitors C1 and C2 can be obtained. Similarly to the fifth embodiment, the bottom of the isolation trench 2 is not roughened, and the leakage current between adjacent DRAM cells with the isolation trench 2 interposed therebetween is also suppressed. On the other hand, since the inner wall of isolation trench 2 is not roughened in the peripheral circuit region, the field shield electrodes (N-type conductive film 4n and P-type conductive film 4p) in isolation trench 2 and silicon substrate 1 Even when a large potential difference is set between the two, a leakage current between the silicon substrate 1 and the silicon substrate 1 can be suppressed.

  Next, a method for manufacturing the semiconductor memory device according to the present embodiment shown in FIG. 60 will be described. 61 to 68 are process diagrams for explaining the method of manufacturing the semiconductor memory device. Hereinafter, the manufacturing method will be described with reference to these drawings.

  First, as in the first embodiment, the pad oxide film 81 and the hard mask 82 are formed on the upper surface of the silicon substrate 1, and the isolation trench 2 is formed by etching using the mask as a mask (FIG. 61).

  Thereafter, a silicon oxide film 90 is deposited on the entire surface of the silicon substrate 1, filling the isolation trench 2 (FIG. 62), and the silicon oxide film 90 on the hard mask 82 is removed by CMP (FIG. 63). Then, a resist mask 91 covering the peripheral circuit region is formed, and the silicon oxide film 90 in the isolation trench 2 in the memory cell region is removed by etching using the resist mask 91 as a mask (FIG. 64).

  Then, roughened polysilicon 88 is formed on the entire surface of the silicon substrate 1. The inner surface (inner wall and bottom) of the isolation trench 2 in the memory cell region is roughened by forming a roughened polysilicon 88. The isolation trench 2 in the peripheral circuit region is filled with the silicon oxide film 90, and the roughened polysilicon 88 is not formed on the inner surface thereof, so that it is not roughened (FIG. 65).

  Then, etch back is performed on the entire surface of the silicon substrate 1 by dry etching. As a result, the roughened polysilicon 88 on the upper surface of the hard mask 82 and the bottom of the isolation trench 2 is removed, but the roughened polysilicon 88 on the inner wall of the isolation trench 2 remains without being removed (FIG. 66). This etch back step can be omitted when the bottom of the isolation trench 2 is also roughened as in the fourth embodiment.

  Thereafter, a resist mask 92 covering the memory cell region is formed, and the silicon oxide film 90 in the isolation trench 2 in the peripheral circuit region is removed by etching using the resist mask 92 as a mask (FIG. 67). Then, by removing the resist mask 92, an isolation trench structure in which only the inner wall of the isolation trench 2 in the memory cell region is roughened is obtained (FIG. 68).

  Thereafter, DRAM cells (access transistors T1 and T2 and capacitors C1 and C2) are formed in the memory cell region by the same procedure as that described in the first embodiment with reference to FIGS. The peripheral PMOS transistor Tp and the peripheral NMOS transistor Tn are formed in the region, and the contact 7 and the wiring 8 connected to them are formed, whereby the semiconductor memory device shown in FIG. 60 is formed.

FIG. 3 is a circuit diagram of a general DRAM cell and a complementary DRAM cell. 1 is a layout diagram of a DRAM cell of a semiconductor memory device according to a first embodiment. 1 is a cross-sectional view of a DRAM cell of a semiconductor memory device according to a first embodiment. FIG. 3 is a cross-sectional view of an isolation region between DRAM cells adjacent in the word line direction in the semiconductor memory device according to the first embodiment. 1 is a cross-sectional perspective view of a DRAM cell of a semiconductor memory device according to a first embodiment. 2 is a cross-sectional view of a memory cell region and a peripheral circuit region in the semiconductor memory device according to the first embodiment. FIG. 1 is a schematic diagram of a chip layout of a semiconductor memory device according to a first embodiment. FIG. 6 is a process diagram illustrating the method of manufacturing the semiconductor memory device according to the first embodiment. FIG. 6 is a process diagram illustrating the method of manufacturing the semiconductor memory device according to the first embodiment. FIG. 6 is a process diagram illustrating the method of manufacturing the semiconductor memory device according to the first embodiment. FIG. 6 is a process diagram illustrating the method of manufacturing the semiconductor memory device according to the first embodiment. FIG. 6 is a process diagram illustrating the method of manufacturing the semiconductor memory device according to the first embodiment. FIG. 6 is a process diagram illustrating the method of manufacturing the semiconductor memory device according to the first embodiment. FIG. 6 is a process diagram illustrating the method of manufacturing the semiconductor memory device according to the first embodiment. FIG. 6 is a process diagram illustrating the method of manufacturing the semiconductor memory device according to the first embodiment. FIG. 6 is a process diagram illustrating the method of manufacturing the semiconductor memory device according to the first embodiment. FIG. 6 is a process diagram illustrating the method of manufacturing the semiconductor memory device according to the first embodiment. FIG. 6 is a process diagram illustrating the method of manufacturing the semiconductor memory device according to the first embodiment. FIG. 6 is a process diagram illustrating the method of manufacturing the semiconductor memory device according to the first embodiment. FIG. 6 is a process diagram illustrating the method of manufacturing the semiconductor memory device according to the first embodiment. FIG. 6 is a process diagram illustrating the method of manufacturing the semiconductor memory device according to the first embodiment. FIG. 3 is a diagram showing an example of a contact layout in the memory cell region of the semiconductor memory device according to the first embodiment. FIG. 3 is a diagram showing an example of a contact layout in the memory cell region of the semiconductor memory device according to the first embodiment. FIG. 3 is a diagram showing an example of a contact layout in the memory cell region of the semiconductor memory device according to the first embodiment. FIG. 6 is a cross-sectional view of a memory cell region and a peripheral circuit region in a semiconductor memory device according to a second embodiment. FIG. 10 is a diagram for explaining an effect of the second embodiment. It is a figure which shows the modification of Embodiment 2. FIG. FIG. 10 is a process diagram illustrating the method of manufacturing the semiconductor memory device according to the second embodiment. FIG. 10 is a process diagram illustrating the method of manufacturing the semiconductor memory device according to the second embodiment. FIG. 10 is a process diagram illustrating the method of manufacturing the semiconductor memory device according to the second embodiment. FIG. 10 is a process diagram illustrating the method of manufacturing the semiconductor memory device according to the second embodiment. FIG. 10 is a process diagram illustrating the method of manufacturing the semiconductor memory device according to the second embodiment. FIG. 10 is a process diagram illustrating the method of manufacturing the semiconductor memory device according to the second embodiment. FIG. 10 is a process diagram illustrating the method of manufacturing the semiconductor memory device according to the second embodiment. FIG. 10 is a process diagram illustrating the method of manufacturing the semiconductor memory device according to the second embodiment. FIG. 10 is a process diagram illustrating the method of manufacturing the semiconductor memory device according to the second embodiment. FIG. 10 is a process diagram illustrating the method of manufacturing the semiconductor memory device according to the second embodiment. FIG. 10 is a process diagram illustrating the method of manufacturing the semiconductor memory device according to the second embodiment. FIG. 10 is a process diagram illustrating the method of manufacturing the semiconductor memory device according to the second embodiment. FIG. 6 is a top view of an outer peripheral portion of a memory cell area of a semiconductor memory device according to a second embodiment. FIG. 6 is a cross-sectional view of a memory cell region and a peripheral circuit region in a semiconductor memory device according to a third embodiment. FIG. 10 is a process diagram illustrating the method for manufacturing the semiconductor memory device according to the third embodiment. FIG. 10 is a process diagram illustrating the method for manufacturing the semiconductor memory device according to the third embodiment. FIG. 10 is a process diagram illustrating the method for manufacturing the semiconductor memory device according to the third embodiment. FIG. 10 is a process diagram illustrating the method for manufacturing the semiconductor memory device according to the third embodiment. FIG. 6 is a cross-sectional view of a memory cell region and a peripheral circuit region in a semiconductor memory device according to a fourth embodiment. FIG. 10 is a process diagram illustrating the method of manufacturing the semiconductor memory device according to the fourth embodiment. FIG. 10 is a process diagram illustrating the method of manufacturing the semiconductor memory device according to the fourth embodiment. FIG. 10 is a process diagram illustrating the method of manufacturing the semiconductor memory device according to the fourth embodiment. FIG. 10 is a process diagram illustrating the method of manufacturing the semiconductor memory device according to the fourth embodiment. FIG. 10 is a process diagram illustrating the method of manufacturing the semiconductor memory device according to the fourth embodiment. FIG. 10 is a process diagram illustrating the method of manufacturing the semiconductor memory device according to the fourth embodiment. FIG. 10 is a cross-sectional view of a memory cell region and a peripheral circuit region in a semiconductor memory device according to a fifth embodiment. FIG. 10 is a process diagram illustrating the method of manufacturing the semiconductor memory device according to the fifth embodiment. FIG. 10 is a process diagram illustrating the method of manufacturing the semiconductor memory device according to the fifth embodiment. FIG. 10 is a process diagram illustrating the method of manufacturing the semiconductor memory device according to the fifth embodiment. FIG. 10 is a process diagram illustrating the method of manufacturing the semiconductor memory device according to the fifth embodiment. FIG. 10 is a process diagram illustrating the method of manufacturing the semiconductor memory device according to the fifth embodiment. FIG. 10 is a process diagram illustrating the method of manufacturing the semiconductor memory device according to the fifth embodiment. FIG. 10 is a cross-sectional view of a memory cell region and a peripheral circuit region in a semiconductor memory device according to a sixth embodiment. FIG. 10 is a process diagram illustrating the method of manufacturing the semiconductor memory device according to the sixth embodiment. FIG. 10 is a process diagram illustrating the method of manufacturing the semiconductor memory device according to the sixth embodiment. FIG. 10 is a process diagram illustrating the method of manufacturing the semiconductor memory device according to the sixth embodiment. FIG. 10 is a process diagram illustrating the method of manufacturing the semiconductor memory device according to the sixth embodiment. FIG. 10 is a process diagram illustrating the method of manufacturing the semiconductor memory device according to the sixth embodiment. FIG. 10 is a process diagram illustrating the method of manufacturing the semiconductor memory device according to the sixth embodiment. FIG. 10 is a process diagram illustrating the method of manufacturing the semiconductor memory device according to the sixth embodiment. FIG. 10 is a process diagram illustrating the method of manufacturing the semiconductor memory device according to the sixth embodiment.

Explanation of symbols

  T1, T2 access transistor, C1, C2 capacitor, Tn, Tp peripheral circuit transistor, 1 silicon substrate, 2 isolation trench, 3, 3a, 3b inner wall oxide film, 4 non-doped polysilicon film, 4p P-type conductive film, 4n N-type conductive film, 5 cap oxide film, 6 interlayer insulating film, 7 contact, 8 wiring, 10, 20 N well region, 11, 21, 31 gate oxide film, 12, 22, 32 gate electrode, 13, 23, 33 Side wall, 14, 15, 24, 34 Source / drain region, 16 Capacitor electrode diffusion layer, 30 P well region 30, 40 Active region, 41 Isolation active region 41, 88 Roughened polysilicon.

Claims (23)

  1. A semiconductor substrate;
    A trench defining an active region in the semiconductor substrate;
    An inner wall insulating film formed on the inner wall of the trench;
    A conductive film embedded in the trench through the inner wall insulating film;
    A first active region that is the active region in which a memory cell is formed;
    First and second impurity diffusion layers formed on both ends of the first active region, the impurity diffusion layer formed on the inner wall of the trench as a first electrode, the inner wall insulating film as a dielectric layer, and the conductive film as a second electrode, A second capacitor;
    The semiconductor memory device, wherein the second electrode of the first capacitor and the second electrode of the second capacitor are connected in the trench.
  2. The semiconductor memory device according to claim 1,
    The semiconductor memory device, wherein the first active region is surrounded by the conductive film.
  3. The semiconductor memory device according to claim 1, wherein:
    A plurality of the first active regions;
    2. A semiconductor memory device, wherein the second electrodes of the first and second capacitors formed in each of the plurality of first active regions are connected to each other in the trench.
  4. The semiconductor memory device according to claim 1, wherein:
    In the first active region,
    A first transistor connected to the first electrode of the first capacitor and a second transistor connected to the first electrode of the second capacitor;
    The gate electrodes of the first and second transistors are
    A semiconductor memory device, wherein the semiconductor memory device is formed using a layer different from the conductive film.
  5. 5. The semiconductor memory device according to claim 1, wherein:
    A second active region, which is the active region in which no circuit element is formed, is formed at a boundary between a memory cell region in which the array of memory cells is formed and a peripheral circuit region in which a peripheral circuit is formed. A semiconductor memory device.
  6. 6. The semiconductor memory device according to claim 5, wherein
    The semiconductor memory device, wherein the second active region is formed in a frame shape surrounding the memory cell region.
  7. The semiconductor memory device according to claim 1, wherein:
    In the trench at the boundary between the memory cell region in which the memory cell array is formed and the peripheral circuit region in which the peripheral circuit is formed, the conductive film is separated into the memory cell region side and the peripheral circuit side. A semiconductor memory device.
  8. The semiconductor memory device according to claim 7,
    A semiconductor memory device, further comprising a contact plug connected to the conductive film in the trench at a boundary between the memory cell region and the peripheral circuit region.
  9. The semiconductor memory device according to claim 1, wherein:
    In the trench at the boundary between the P well region and the N well region in the semiconductor substrate, the conductive film is separated into the P well region side and the N well region side. apparatus.
  10. The semiconductor memory device according to claim 9,
    A semiconductor memory device, further comprising a contact plug connected to the conductive film in the trench at a boundary between the P well region and the N well region.
  11. The semiconductor memory device according to claim 1, wherein:
    The inner wall insulating film is
    A semiconductor memory device characterized in that a thickness of a portion of the first and second capacitors serving as a dielectric layer is formed to be thinner than other portions.
  12. 12. A semiconductor memory device according to claim 1, wherein
    A semiconductor memory device, wherein an inner wall of the trench is roughened.
  13. The semiconductor memory device according to claim 12,
    2. The semiconductor memory device according to claim 1, wherein the bottom of the trench whose inner wall is roughened is not roughened.
  14. 14. The semiconductor memory device according to claim 12, wherein:
    The semiconductor memory device according to claim 1, wherein the trench having the roughened inner wall is disposed only in a memory cell region in which the array of memory cells is formed.
  15. 15. The semiconductor memory device according to claim 1, wherein:
    The conductive film in the P well region of the semiconductor substrate is polysilicon introduced with a P-type dopant, and the conductive film in the N well region is polysilicon introduced with an N-type dopant. A semiconductor memory device.
  16. A method of manufacturing a semiconductor memory device including a memory cell having a capacitor and a transistor,
    (A) forming a trench defining an active region in the semiconductor substrate on the semiconductor substrate;
    (B) forming an impurity diffusion layer by ion implantation on the inner wall of the trench corresponding to the side wall of the first active region which is the active region for forming the memory cell;
    (C) forming an inner wall insulating film on the inner wall of the trench;
    (D) after the step (c), burying non-doped polysilicon in the trench;
    (E) A dopant is introduced into the first active region and the non-doped polysilicon by ion implantation to form a well in the first active region, and the non-doped polysilicon is made a conductive film, so that the impurity diffusion is performed. Forming the capacitor with a layer as a first electrode, the inner wall insulating film as a dielectric layer, and the conductive film as a second electrode.
  17. A method of manufacturing a semiconductor memory device according to claim 16,
    (F) forming a gate electrode on the well of the first active region, and forming a source / drain region on both sides of the gate electrode in the well by ion implantation, thereby forming the transistor in the first active region; A method of manufacturing a semiconductor memory device, further comprising a forming step.
  18. A method of manufacturing a semiconductor memory device according to claim 16 or 17,
    The ion implantation of the step (e)
    A method of manufacturing a semiconductor memory device, wherein a well is simultaneously formed in a second active region which is the active region for forming a peripheral circuit of the memory cell.
  19. 19. A method of manufacturing a semiconductor memory device according to claim 16, comprising:
    The active region formed in the step (a) is:
    A method of manufacturing a semiconductor memory device, comprising: a third active region surrounding a memory cell region in which the array of memory cells is formed.
  20. A method of manufacturing a semiconductor memory device according to any one of claims 16 to 19,
    The trench formed in the step (a) is:
    Including a narrow first trench part and a second trench part wider than the first trench part,
    The step (d)
    (D-1) depositing the non-doped polysilicon with a film thickness of less than half the width of the second trench portion;
    (D-2) A method of manufacturing a semiconductor memory device, comprising: etching back the non-doped polysilicon until reaching the bottom of the first trench portion.
  21. A method of manufacturing a semiconductor memory device according to claim 20,
    In the step (a),
    The first trench part is formed inside a memory cell region where the array of memory cells is formed,
    A method of manufacturing a semiconductor memory device, wherein the second trench portion is formed on an outer periphery of the memory cell region.
  22. A method of manufacturing a semiconductor memory device according to claim 20 or claim 21,
    In the step (a),
    The first trench part is formed in the P well region and the N well region in the semiconductor substrate,
    A method of manufacturing a semiconductor memory device, wherein the second trench portion is formed at a boundary between the P well region and the N well region.
  23. A method of manufacturing a semiconductor memory device according to any one of claims 20 to 22,
    (G) The method of manufacturing a semiconductor memory device, further comprising a step of forming a contact connected to the conductive film in the second trench portion.
JP2006247760A 2006-09-13 2006-09-13 Semiconductor memory and manufacturing method thereof Pending JP2008071861A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010045344A (en) * 2008-07-18 2010-02-25 Nec Electronics Corp Manufacturing method of semiconductor device, and semiconductor device
JP2010050202A (en) * 2008-08-20 2010-03-04 Renesas Technology Corp Semiconductor device and its manufacturing method
JP2012256856A (en) * 2011-04-15 2012-12-27 Semiconductor Energy Lab Co Ltd Semiconductor memory

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010045344A (en) * 2008-07-18 2010-02-25 Nec Electronics Corp Manufacturing method of semiconductor device, and semiconductor device
JP2010050202A (en) * 2008-08-20 2010-03-04 Renesas Technology Corp Semiconductor device and its manufacturing method
JP2012256856A (en) * 2011-04-15 2012-12-27 Semiconductor Energy Lab Co Ltd Semiconductor memory

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