JPH0621388A - Semiconductor memory and manufacture thereof - Google Patents

Abstract

PURPOSE:To manufacture a semiconductor memory having excellent data holding characteristics by reducing a leakage current from a trench part. CONSTITUTION:An SiO2 film 12 is pattern-formed on a P-type Si substrate 11, and with the film 12 as a mask a P-type epitaxial layer 13 having a thickness larger than that of the film 12 is selectively grown on the substrate 11, thereby forming a trench 14 relatively on the film 12. An impurity is obliquely ion implanted to form an N-type layer 23 of one electrode of a capacitor 27 on an inner wall of the trench 14, a polycrystalline Si film 25 is further formed through an ONO film 24, and used as an opposite electrode of the capacitor 27. Accordingly, it is not necessary to etch in order to form the trench 14, and crystal defects are reduced on the layer 13 around the trench 14. Thus, a leakage current scarcely flows from the part of the trench 14 to the layer 13.

Description

Detailed Description of the Invention

[0001]

This invention relates to a DRAM (Dynamic
The present invention relates to a semiconductor memory device such as a Random Access Memory) and a manufacturing method thereof.

[0002]

2. Description of the Related Art A memory cell of a DRAM is usually composed of one MOS (or MIS) transistor and one capacitor, and the capacity of the memory cell is secured by the amount of charges accumulated in the capacitor. Therefore, in order to reduce the memory cell area of the DRAM and secure a sufficient capacitor area, a capacitor is recently formed in a groove called a trench dug in a semiconductor substrate. Pillars (pillar: pill) left unetched on the semiconductor substrate surface
It has also been proposed to form a capacitor around (ar).

A memory cell utilizing this trench includes
A trench capacitor structure in which a portion of the semiconductor substrate on the inner surface of the trench is used as a charge storage node (storage node), and polysilicon is embedded in the trench via an insulating film as a counter electrode, and a charge storage electrode which is a storage node is used as a trench There is a so-called stack trench structure in which an insulating film is formed inside, and a counter electrode is formed thereon with a dielectric film therebetween. Further, a structure has also been proposed in which a polysilicon film formed in a trench via an insulating film is used as a charge storage electrode which is a storage node, and a portion of the semiconductor substrate on the inner surface of the trench is used as a counter electrode.

For example, an improved stacked trench structure is known as "Double Stacked Capacitor with Self-aligned".
Poly Source / Drain Transistor (DSP) Cell for Mega
bitDRAM "(Tsukamoto et.al., pp328-331 IEDM 87 IEE
E 1987).

A method of manufacturing a memory cell having a trench structure is disclosed in, for example, Japanese Patent Application Laid-Open No. 63-253660 or Japanese Patent Application Laid-Open No. 2-111062.

Further, a method of forming a trench for a trench capacitor is disclosed in, for example, Japanese Patent Laid-Open No. 1-105567.
It is disclosed in the publication.

[0007]

The trench described above is
Conventionally, it is formed by etching a semiconductor substrate.

However, when a trench is formed in a semiconductor substrate by etching, many crystal defects occur in the semiconductor substrate around the trench due to damage due to etching.
In the trench capacitor structure in which the inner surface of the trench is used as a charge storage node, a leak current easily flows and the data retention characteristic deteriorates.

Further, since there are such problems of etching damage and leakage current, the trenches cannot be formed close to each other, and as a result, the degree of integration of the device cannot be increased beyond a certain level. There was also a problem.

Further, if an etching method with high processing accuracy is adopted to form a fine pattern, there is a problem that etching damage is rather increased because high energy ion assist is usually required.

Therefore, an object of the present invention is to provide a semiconductor memory device having a trench with few crystal defects, in which leak current does not easily flow, and which can be highly integrated, and a manufacturing method thereof.

[0012]

In order to solve the above-mentioned problems, a semiconductor memory device of the present invention is a semiconductor having a memory cell in which one transistor and one capacitor cooperate to record information. In a memory device, a semiconductor single crystal formed on a semiconductor substrate, an insulating film patterned on the semiconductor substrate, and on the semiconductor substrate around the insulating film with a film thickness larger than the insulating film. And layers.

At this time, it is preferable that the semiconductor single crystal layer has the same conductivity type as that of the semiconductor substrate.

At this time, the semiconductor single crystal layer may have the same crystal axis direction as the semiconductor substrate.

In another aspect, the semiconductor memory device of the present invention is a semiconductor memory device having a memory cell in which one transistor and one capacitor cooperate to record information. A bottom made of a patterned insulating film, and a sidewall made of a substantially vertical side surface of an epitaxial semiconductor layer epitaxially grown on the semiconductor substrate around the insulating film, and
The transistor may be formed on the epitaxial semiconductor layer while having a trench in which the capacitor is formed.

Further, at this time, the capacitor has a charge storage node formed by introducing impurities into a sidewall portion of the trench, a second insulating film covering an inner surface of the trench, and the second insulating film. And a counter electrode formed on the top surface.

The method of manufacturing a semiconductor memory device according to the present invention is the method of manufacturing a semiconductor memory device having a memory cell in which one transistor and one capacitor cooperate to record information. A step of patterning an insulating film thereon, and using this insulating film as a growth mask, a semiconductor material is selectively epitaxially grown on the semiconductor substrate, whereby an upper portion of the insulating film constitutes a relative trench. Forming a layer, and forming the capacitor on the sidewall of the trench.

Furthermore, in another aspect of the method for manufacturing a semiconductor memory device of the present invention, a method for manufacturing a semiconductor memory device having a memory cell in which one transistor and one capacitor cooperate to record information. In the step of patterning a first insulating film on a semiconductor substrate, and using the first insulating film as a growth mask, a semiconductor material is selectively epitaxially grown on the semiconductor substrate, whereby the first insulating film is formed.
A step of forming an epitaxial layer in which a portion above the insulating film relatively constitutes a trench; a step of introducing an impurity into a side wall portion of the trench to form a charge storage node of the capacitor; The method includes a step of covering the side wall with a second insulating film, and a step of forming a conductive film to be a counter electrode of the capacitor on the second insulating film.

[0019]

In the semiconductor memory device of the present invention, the semiconductor single crystal layer having a larger film thickness than the insulating film is formed on the semiconductor substrate around the insulating film. Trenches are formed. Since this trench is not damaged by etching, there are few crystal defects in the peripheral portion of the trench, and as a result, the leak current from the trench portion is reduced.

In the method of manufacturing the semiconductor memory device of the present invention,
By selectively epitaxially growing an epitaxial layer on this semiconductor substrate using a patterned insulating film on the semiconductor substrate as a mask, it is possible to relatively form a trench in the portion above the insulating film without etching. ing. Therefore, as compared with the conventional etching method, crystal defects particularly in the peripheral portion of the trench are reduced, and as a result, it is possible to provide a semiconductor memory device having a small leak current from the trench portion.

Further, since the crystal defects in the peripheral portion of the trench are reduced, the memory cell area can be reduced and the trenches can be formed close to each other, so that the device can be highly integrated.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment in which the present invention is applied to a DRAM having a memory cell in which one MOS transistor and one capacitor cooperate to store information will be described with reference to FIGS.
Will be described with reference to.

FIG. 1 is an enlarged sectional view of an essential part showing a semiconductor memory device in which two memory cells of a DRAM are formed by omitting a cover part such as a bit line and a passivation film. As shown in FIG. 1, a thickness of 20 is formed on the P-type semiconductor substrate 11.
Insulating film 12 of about 00Å to 5000Å and this insulating film 1
2 is thicker than the insulating film 12 adjacent to 2 (5-10 μm
The semiconductor single crystal layer 13 is formed, and as a result, the trench 14 having the insulating film 12 as the bottom and the semiconductor single crystal layer 13 as the side is formed.

One memory cell of DRAM is one M
It is composed of an OS transistor 35 and one capacitor 27. Here, the MOS transistor 35 is formed on the epitaxial layer 13 which is a semiconductor single crystal layer, and the gate electrode 34, the gate insulating film 33 formed under the gate electrode 34, and both sides of the gate electrode 34. And source / drain 31, 32 arranged in the. still,
The gate electrode 34 is polycrystalline silicon, source / drain 3
Reference numerals 1 and 32 are N ⁺ type semiconductor crystals, and gate insulating film and interlayer insulating film 33 are made of SiO ₂ .

The capacitor 27 is formed inside the trench 14. The capacitor 27 includes a storage node (charge storage node) 23 in which an N-type impurity is introduced into the inner wall portion of the trench 14, an ONO film 24 covering the inner surface of the trench 14, and a polycrystalline film formed on the ONO film 24. It is provided with a cell plate (counter electrode) which is the Si films 25 and 26.

The source 31 of each transistor 35
Are electrically connected to the storage node 23 of each capacitor 27.

Next, a method of manufacturing the memory cell of the DRAM shown in FIG. 1 will be described.

First, as shown in FIG. 2, a P-type single crystal S
By the CVD method or the thermal oxidation method on the entire surface of the i substrate 11,
A SiO ₂ film 12 having a film thickness of about 2000 to 5000 Å is formed, and this SiO ₂ film 12 is patterned to leave the SiO ₂ film 12 only in the region on the Si substrate 11 where the trench is to be formed. In addition, the insulating film to be the growth mask,
A Si ₃ N ₄ film may be used instead of the SiO ₂ film 12.

Next, as shown in FIG. 3, the SiO ₂ film 12 is used as a mask to thermally decompose silane at a temperature of about 1000 to 1200 ° C., so that a film thickness of 5 to 10 μm is formed on the Si substrate 11. The P-type epitaxial layer 13 having a certain degree is selectively grown. As a result, as shown in FIG. 3, the portion on the SiO ₂ film 12 where the epitaxial layer has not grown becomes the trench 14 relatively.

Next, as shown in FIG.
4 on the entire surface of the epitaxial layer 13 including the inner surface of
₂ film 15 and the Si ₃ N ₄ film 16 is oxidation resistant film is formed respectively, of the photolithography Si ₃ N ₄
The film 16 and the SiO ₂ film 15 are patterned to leave the Si ₃ N ₄ film 16 and the SiO ₂ film 15 only on the portion of the epitaxial layer 13 to be the device active region.

Then, the field oxide film 17 is formed in the element isolation region of the epitaxial layer 13 by selective oxidation using the Si ₃ N ₄ film 16 as a mask. At this time, the element isolation region is formed so that each trench 14 is completely included in the element active region.

Next, as shown in FIG. 5, Si is treated with hot phosphoric acid.
_After removing the ₃ N ₄ film 16 and further removing the SiO ₂ film 15, a resist 21 is patterned so as to expose only the trench 14 and its vicinity. Then, by the oblique ion implantation method using the resist 21 as a mask,
Impurities 22 are added to the side wall of the trench 14 and the vicinity thereof.
The N-type layer 23 is formed on the side wall of the trench 14 by introducing it at a dose of about 0 ¹³ to 10 ¹⁴ cm ⁻² . The introduction of impurities may be performed by a method such as solid phase diffusion.

Next, as shown in FIG. 6, after removing the resist 21 by ashing with oxygen plasma, an ONO film 24 is formed on the entire surface including the inner surface of the trench 14, and a polycrystalline Si film is further formed thereon. 25 is formed. And this polycrystalline S
After forming the i film 25, the concave portion remaining in the trench 14 is filled with a polycrystalline Si film 26 by a low pressure CVD method or the like.
The polycrystalline Si film 26 is used to fill the trench.
Alternatively, a SiO ₂ film may be used.

After that, as shown in the figure, the polycrystalline S film 25 and the ONO film 24 are formed so as to remove only the portion of the region where the MOS transistor is to be formed.
The i film 25 and the ONO film 24 are patterned respectively. As a result, a capacitor 27 is formed in which the N-type layer 23 serves as a charge storage node serving as a storage node, the ONO film 24 serves as a capacitor dielectric film, and the polycrystalline Si films 25 and 26 serve as cell plates serving as counter electrodes.

Next, as shown in FIG. 1, the polycrystalline Si film 2
The uncovered epitaxial layer 13 to 5, to form the N ⁺ layer 32 spaced from the N ⁺ layer 31 Toko of N ⁺ layer 31 connected to the N-type layer 23. And the epitaxial layer 1
3. A SiO ₂ film 33 is formed on the surfaces of the polycrystalline Si films 25 and 26 by thermal oxidation. At this time, since the polycrystalline Si films 25 and 26 have a higher oxidation rate than the epitaxial layer 13, the SiO on the surfaces of the polycrystalline Si films 25 and 26 are
_{2 The} film thickness of the film 33 is the same as the Si on the surface of the epitaxial layer 13.
It becomes thicker than the film thickness of the O ₂ film 33. Epitaxial layer 1
The SiO ₂ film 33 on 3 serves as a gate oxide film of the MOS transistor. The gate oxide film may be formed separately from the SiO ₂ film 33 which is the interlayer insulating film.

After that, a polycrystalline Si film 34 is deposited on the entire surface, and the polycrystalline Si film 34 is patterned to leave the polycrystalline Si film 34 between the N ⁺ layers 31 and 32. Thus, a MOS transistor 35 having the N ⁺ layers 31 and 32 as sources and drains, the SiO ₂ film 33 on the surface of the epitaxial layer 13 as a gate oxide film, and the polycrystalline Si film 34 as a gate electrode is formed. The SiO ₂ film 33 on the polycrystalline Si films 25 and 26 becomes an interlayer insulating film.

After that, although not shown, the polycrystalline Si film 34 is covered with an interlayer insulating film, and the N ⁺ layer 32 is formed on the interlayer insulating film.
Open the contact hole reaching up to. Then, a bit line that contacts the N ⁺ layer 32 through the contact hole is formed, the bit line is covered with a passivation film, and a DR having a memory cell having a trench capacitor structure is formed.
Complete the AM.

In the illustrated example, two memory cells each having a pair of MOS transistors 35 sharing the drain as access transistors of the corresponding capacitors 27 are formed in one element active region.

According to the manufacturing method described above, since it is not necessary to perform etching to form the trench 14, the epitaxial layer 13 in which the trench 14 is formed has relatively few crystal defects. Therefore, a leak current is unlikely to flow in the epitaxial layer 13, the leak current from the N-type layer 23 which is the storage node of the capacitor is reduced, and the data retention characteristic thereof is improved.

Further, since it is difficult for a leak current to flow in the epitaxial layer 13, the memory cell area can be reduced and the trenches can be formed in close proximity to each other, so that the DRAM can be highly integrated.

The embodiment in which the present invention is applied to the method of manufacturing the memory cell having the trench capacitor structure has been described above.
The present invention can be applied to a method of manufacturing a memory cell having another structure using a trench.

Furthermore, the present invention can be applied to a semiconductor memory device having a pillar structure in which a capacitor is formed on the wall surface of a convex semiconductor single crystal layer.

[0043]

In the semiconductor memory device of the present invention, the semiconductor single crystal layer having a larger film thickness than the insulating film is formed on the semiconductor substrate around the insulating film. A trench is formed relatively to. Since this trench is not damaged by etching, there are few crystal defects around the trench. Therefore, the semiconductor memory device of the present invention has a small leak current from the trench portion and is excellent in data retention characteristics.

In the method of manufacturing the semiconductor memory device of the present invention,
By selectively epitaxially growing an epitaxial layer on this semiconductor substrate using a patterned insulating film on the semiconductor substrate as a mask, it is possible to relatively form a trench in the portion above the insulating film without etching. ing. Therefore, it is possible to obtain a semiconductor memory device with less crystal defects particularly in the peripheral portion of the trench as compared with the conventional etching method. Therefore, according to the method of manufacturing a semiconductor memory device of the present invention, it is possible to provide a semiconductor memory device having a small leak current from the trench portion and excellent data retention characteristics.

Further, according to the method of manufacturing a semiconductor memory device of the present invention, since the crystal defects in the peripheral portion of the trench are reduced, the memory cell area can be reduced and the trench can be formed close to each other. Therefore, high integration of the device can be achieved.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a method of manufacturing a memory cell having a trench capacitor structure according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a method of manufacturing a memory cell having a trench capacitor structure according to an embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a method of manufacturing a memory cell having a trench capacitor structure according to an embodiment of the present invention.

FIG. 4 is a cross-sectional view showing a method of manufacturing a memory cell having a trench capacitor structure according to an embodiment of the present invention.

FIG. 5 is a cross-sectional view showing a method of manufacturing a memory cell having a trench capacitor structure according to an embodiment of the present invention.

FIG. 6 is a cross-sectional view showing a method of manufacturing a memory cell having a trench capacitor structure according to an embodiment of the present invention.

[Explanation of symbols]

11 Si substrate 12 SiO ₂ film 13 Epitaxial layer 14 Trench 23 N-type layer 24 ONO film 25 Polycrystalline Si film 27 Capacitor 35 MOS transistor

Claims (7)

[Claims] 1. A semiconductor memory device having a memory cell in which one transistor and one capacitor cooperate to record information, a semiconductor substrate, and an insulating film patterned on the semiconductor substrate. A semiconductor memory device comprising: a semiconductor single crystal layer formed to have a larger film thickness than the insulating film, on the semiconductor substrate around the insulating film. 2. The semiconductor memory device according to claim 1, wherein the semiconductor single crystal layer has the same conductivity type as that of the semiconductor substrate. 3. The semiconductor memory device according to claim 1, wherein the semiconductor single crystal layer has the same crystal axis direction as the semiconductor substrate. 4. A semiconductor memory device having a memory cell in which one transistor and one capacitor cooperate to record information, and a bottom portion formed of an insulating film patterned on a semiconductor substrate, An epitaxial semiconductor layer epitaxially grown on the semiconductor substrate around an insulating film, and a sidewall having substantially vertical side surfaces, and a trench in which the capacitor is formed. A semiconductor memory device, wherein the transistor is formed on a layer. 5. The capacitor comprises: a charge storage node formed by introducing impurities into a sidewall portion of the trench; a second insulating film covering an inner surface of the trench; and a second insulating film on the second insulating film. The semiconductor memory device according to claim 4, further comprising a formed counter electrode. 6. A method of manufacturing a semiconductor memory device having a memory cell in which one transistor and one capacitor cooperate to record information, the method comprising: patterning an insulating film on a semiconductor substrate; Using this insulating film as a growth mask, a semiconductor material is selectively epitaxially grown on the semiconductor substrate.
A method of manufacturing a semiconductor memory device, comprising: a step of forming an epitaxial layer in which a portion above the insulating film relatively forms a trench; and a step of forming the capacitor on a sidewall of the trench. 7. A method of manufacturing a semiconductor memory device having a memory cell in which one transistor and one capacitor cooperate to record information, wherein a first insulating film is patterned on a semiconductor substrate. A step of selectively epitaxially growing a semiconductor material on the semiconductor substrate by using the first insulating film as a growth mask, thereby forming an epitaxial layer in which a portion above the first insulating film relatively forms a trench. Forming a charge storage node of the capacitor by introducing impurities into the side wall of the trench; covering the side wall of the trench with a second insulating film; and a counter electrode of the capacitor. Forming a conductive film formed on the second insulating film, the method for manufacturing a semiconductor memory device.