JPH0793371B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a dynamic random access memory.

With the development of large monolithic dynamic random access memory (dRAM), some problems have arisen. One of the most important of these problems is 1
In order to implement more cells on a chip, there is a way to reduce the cell size of dRAM without increasing the soft error rate. Large dRAMs are based on silicon and typically each cell contains a MOS field-effect transistor with its source connected to a storage capacitor, its drain connected to a bit line, and its gate connected to a word line. There is. The cell operates to store charge on the capacitor to represent a logic "1" and not to store a charge to represent a logic "0". Traditionally, this cell capacitor has been formed with inversion layers separated from the electrodes above it by a thin oxide layer and from the substrate by a depletion layer. However, for stable circuit operation, the capacitance of this capacitor must be large enough to obtain a sufficiently large signal-to-noise ratio, which means that a large substrate area is used for the capacitor. . In addition, such MOS capacitors are not
One alpha particle can generate more than 200 femto coulombs (fC) of interfering electrons in the substrate, noise injected from the substrate, pn junction leakage across the capacitor, cell transistor Weak against any of the Subthreshold Creeks. 1 dR
The amount of charge stored in AM is typically 250 fC. If the power supply voltage is 3 volts, 50fF is required for this charge amount.
(Femto-Flat) capacitor capacity is required, and if the storage oxide thickness is 150Å, a capacitor area of about 20 square microns is required. If the conventional two-dimensional technique is used, this will set the lower limit of the cell size.

One method to solve these problems is IE 1983.
Joll (Joll, published on page 8 of EE Elec. Dev. Lett
y) et al., “A Dynamic RAM Cell in Recry
stallized Polysilicon), in which all elements of the cell, including access transistors and charge storage capacitors, are beam recrystallized from polycrystalline silicon deposited through an oxide layer on a silicon substrate. Formed in the layer. The bit line is contained in the recrystallized polycrystalline silicon layer, and when the transistor is turned on, charges flow into the storage region. The storage area is
It is made of heavily doped recrystallized polycrystalline silicon with top, bottom and three sides encased in thermal oxide. Since the upper and lower electrodes are separated from the storage region in recrystallized polycrystalline silicon by a thin oxide, the storage capacity of this capacitor is about twice that of conventional capacitors for the same storage area. is there. In addition, the underlying oxide separates the storage region from any charges injected into the substrate from the peripheral circuits that cause soft errors, and charges injected by alpha particles and other radiation. Further, the capacitance of the bit line is reduced by the thick oxide below the bit line and the oxide isolation that completely covers the sides. However, 2 of the conventional design
It cannot be said that the area occupied by the cell capacitor could be made sufficiently small enough to obtain the double capacity.

The second method for reducing dRAM cell size is to use capacitors with plates extending into the substrate. This capacitor is called a corrugated capacitor,
H. Sunami et al., Published on page 806 of the IEEE's IEDM Digest collection (1982), "Morbit-bit dynamic MOS memory corrugated capacitor cell (CC
C) (A Corrugated Capacifor Cell (CCC) for Megabit
Dynamic MOS Memories) ''; 1983 IEEE Elec. Dev. Lett
A paper by H. Sunami et al. On page 80 "A Corrugated Capacifor Cell for Megabit Dynamic MOS Memory (CCC)"
(CCC) for Megabit Dynamic MOS Memories); 1984
K. See on page 282 of the IEEE ISSCC digester collection.
Itoh et al., "An Experimental 1 Mb DRAM with O with the same chip voltage limiter"
n-Chip Voltage Limiter) ”. The corrugated capacitor extends about 2.5 microns into the silicon substrate. The manufacturing process is as follows. Trenches are formed by ordinary reactive sputtering etching with CCl ₄ gas with a CVD silicon dioxide film as a mask.
Wet etching removes all damage and contamination from this dry etching. After the formation of the trench, a silicon dioxide / silicon nitride / silicon dioxide triple storage layer is formed on the trench wall. Finally, the groove is filled with LPCVD polycrystalline silicon. If a corrugated capacitor is used, it is possible to obtain more than 3 times the capacity of the conventional cell, and a storage capacity of 60 fF can be obtained with a cell having a length of 3 microns and a width of 7 microns.

A third method for reducing the area occupied by a cell capacitor is similar to the method described in the previous section, where the capacitor is formed in the groove. For example, in 1983 IEEE
E. Arai (Ara, published on page 19 of the IEDM Digest)
i) "Submicron MOS VLSI process technology (Submi
cron MOS VLSI Process Technologies) "; 1983 IEEE
K. Minegishi et al., "A Submicron CMOS Megabit Dynamic RAM with Doped-faced Groove Capacitor Cell," published on page 319 of the IEDM Digest Collection.
Technology using Doped Face Trench Capacitor Cel
l) "; 1983 IEEE Elec. Dev. Lett., page 411, by T. Morie et al.," Depletion Groove Capacitor Technology for Megabit-Level MOS dRAM (Depletion
Trench Capacitor Technology for Megabit Level MOS
dRAM) "; these papers describe cells of conventional design, except for capacitors. Regarding the capacitor, the conventional electrode plate parallel to the substrate surface is changed to an electrode plate on the wall surface of the groove in the substrate. In such a groove capacitor, the capacitance per unit area of the substrate can be increased by simply using the deep groove. The capacitors described in these papers are manufactured as follows. Starting from a P-type (100) plane silicon substrate having a specific resistance of 4-5 Ωcm, a groove pattern having a width of 0.4-1.0 micron is formed by electron beam direct writing. Then, under a pressure of about 14 mTorr, a groove having a depth of 1-3 microns is dug by reactive ion etching with CBrF ₃ . By etching in a mixed solution of nitric acid, acetic acid and hydrofluoric acid,
The damage caused by reactive ion etching (RIE) is removed from the surface of the groove. PSG is deposited by CVD using a PH ₃ / SiH ₄ / O ₂ gas system, and phosphorus is diffused into the groove surface layer. Next, PSG is removed by etching with hydrofluoric acid. A 150-500Å SiO ₂ film is grown or 500Å Si ₃ N ₄ is CVD deposited on the trench walls in dry oxygen.
Finally, the groove is filled with LPCVD polycrystalline silicon. The capacitance per unit area of the groove side surface is about the same as the capacitance per unit area of the conventional capacitor. Therefore, in the capacitor of the deep groove, the storage capacitor area per unit substrate area is increased to increase the cell substrate capacity. The area can be reduced.

It is also well known to use grooves for separation,
Has been widely studied. For example, R. Rung et al., "Deep Trench Isolated C
MOS Devices) ;; 1983, IEEE Elec. Dev. Lett. 303, K. Cham, et al., "A Study of the Trench Invers.
ion Problem in the Trench CMOS Technology) "; 1982
A. Hayasaka et al., Published on page 62 of the IEDM Digest of IEEE in "U-Groove Isolation Technique for High Speed Bipolar VLSI
"Speed Bipolar VLSI's)"; 1982, IEEE IEDM Digest, page 58, H. Goto et al., "Separation Technology for High Performance Bipolar Memories IOP-II (An Is Is
olation Technology for High Performance Bipolar Me
mories−−IOP−II) ”; T. Yamaguchi et al., 1983, IEEE IEDM Digest version, 522,“ High-speed ratchet-free 0.5-micron long-channel CMOS using self-aligned TiSi ₂ and deep groove separation technology. (Hish-Speed L
atchup−Free 0.5μm Channel CMOS Using Self−Aligne
d TiSi ₂ and Deep−Trench Isolation Technologie
s) "; 1983 IEEE IEDM Digest version, page 151
S. Kohyama et al., “CMOS Technology Trends (Dir
Sections in CMOS Technology); 1983 IEEE IEDM Digest, page 23, K. Cham, et al., "Characterization and Modeling of the Trench for Trench Isolation CMOS Technology." Surf
ace Inversion Problem for the Trench Isolated CMOS
Technology) ”etc. These separating grooves are
It is formed by a method similar to that described for the groove and the corrugated capacitor. That is, patterning (typically using an oxide mask), CBrF ₃ , CCl ₄ , Cl ₂ −
It is formed by RIE digging with H ₂ , CCl ₄ —O _2, etc., thermal oxidation of the sidewalls (and LPCVD nitriding), and burying with polycrystalline silicon.

However, the use of trench capacitors does not completely solve the problem of reducing dRAM cell size. That is, in both the horizontally arranged field effect transistor and the vertically arranged groove capacitor, the cells still occupy a large area of the substrate.

[Summary of Invention]

The present invention provides a one-transistor dRAM cell structure, in which the cell transistor is formed on the side surface of the substrate trench containing the cell capacitor. This allows the transistors to be stacked directly above the capacitors, resulting in a minimum substrate area cell to solve the problem of high density packaging of the cell. In a preferred embodiment, one electrode plate of the capacitor and a channel of the transistor are formed in one layer of polycrystalline silicon deposited in the trench such that the gate oxide and the oxide that is the insulator of the capacitor are simultaneously formed. Will be formed.

[Description of the preferred embodiment]

The preferred embodiment dRAM cell is a 1 transistor / 1 capacitor cell connected to the bit and word lines as shown in FIG. 1A and operates as follows. Capacitor
12 stores an electric charge in order to express bit information (for example, when there is no stored electric charge, a logic "0" is set, and an electric charge corresponding to a voltage of 5 V is applied between the capacitor electrodes is stored. Can be taken as logic "1"). This bit information can be accessed (read or write new bit) as follows: Word line 14 connected to gate 16
To turn on transistor 18. The turned-on transistor 18 connects the capacitor 12 to the bit line 20 for reading and writing. Since the electric charge on the capacitor 12 is attenuated by the leak current and other factors, it is necessary to periodically regenerate (reflect) the electric charge. This has given rise to the name of dynamic RAM (dRAM).

FIG. 1B shows the preferred embodiment cell 30 with bit line 20 and word line 14
FIG. 7 is a plan view of a part of the dRAM array of bit lines and word lines arranged at the intersection point of FIG. Where bit line 20 is the word line
It passes above 14. These cells extend into the substrate below the line to provide maximum packing density memory. When the minimum dimension is f and the positioning accuracy is R, the cell area is [2 (f + R)] ² . For example, the minimum dimension is 1.
With 0 micron and positioning accuracy of 0.25 micron, the cell area is 6.25 square microns.

FIG. 2 illustrates a first preferred embodiment dRAM, indicated generally at 30.
It is sectional drawing of a cell. The cell 30 is formed in a P ⁺ silicon substrate 32 and includes a P-type epitaxial layer 34, a field oxide 36, a P ⁺ channel stop region 38, a buried n ^+.
Gate region 40, word line oxide 42, P ⁺ capacitor electrode region 44, capacitor insulator / gate oxide 46, P-type polycrystalline silicon capacitor electrode plate / channel region 48, P ⁺ or silicided polycrystalline silicon bit line 20. , Containing 50 oxides. FIG. 2 is a vertical line (2)-(2) in FIG. 1B.
It corresponds to the cross section. Region 40 extends in a direction perpendicular to the plane of the drawing in FIG. 2 to form word line 14, and the square cross-section of the groove in substrate 32 / epitaxial layer 34 / embedded region 40 containing capacitor 12 and transistor 18 is It can be seen in Figure 1B.

In the cell 30, the capacitor 12 is formed by using a region 44 and a region 48 facing the region 44 as an electrode plate. The insulator is the portion of layer 46 sandwiched between the two electrode plates.
Charge is stored in region 48 and is separated from the substrate by oxide layer 46. For a groove having a width of 1 micron and a length of 1 micron and a depth of 6 microns, the capacitor electrode plate area is about 21 square microns if the gate region 40 is about 1 micron deep. Becomes

In cell 30, transistor 18 is a P-channel depletion mode field effect transistor whose source is in the capacitor plate portion of layer 48 and whose channel is layer 48.
The rest of it, its drain is the part of bit line 20 adjacent to the channel, and its gate is the word line.
It is in area 40, which is united with 14. Since the transistor operates in depletion mode, the gate voltage is normally at a high level, which causes the junction between gate region 40 and capacitor plate region 44 to be reverse biased.

The dimensions and materials of the cell 30 are best understood from the following description of the process of making the first preferred embodiment illustrated in the cross-sectional views showing the sequence of steps shown in FIGS. 3A-3C. Let's do it.

1. A P ⁺ type (100) plane silicon substrate 32 having a P type epitaxial layer 34 having a specific resistance of 5-10 Ω · cm contains a field oxide 36 including a channel stop region 38 formed by a conventional method. ing. An oxide layer is grown on the epitaxial layer 34 for stress relaxation, and LP is deposited on the oxide layer.
Nitride is deposited by the CVD method. Patterning of the active area is performed and nitride and oxide outside the active area are removed by plasma etching. Channel stop (stop) region by boron ion implantation using nitride as a mask
38 is formed. 1.0 micron field oxide 3
6 growth takes place. Nitride is patterned for word lines 14 / region 40, stress relief oxide is etched, and arsenic implantation causes word lines 14 and regions 40 to have a carrier density of 10 ¹⁸ per cubic centimeter n ^+. Dope the mold. Region 40 is about 2.0 microns wide and 0.7 microns thick, and region 40 is located with a 2.5 micron pitch. See Figure 3A.

2. Grow 2000Å oxide over region 40. The oxide is patterned into 1.0 micron square grooves and plasma etched. Next reactive ion etching of HCl ₄ (RI
E) to a total depth of 3.5 microns with an oxide mask. After digging the trenches, a wet acid etch removes RIE damage and contamination. Next, by vapor phase diffusion of boron, P ⁺ with a carrier density of 1 × 10 ¹⁷ / cm ^{3 at} a depth of about 1000 Å
A region 44 is formed. See Figure 3B.

3. Grow 150Å oxide by thermal oxidation on the sides of the trench, over regions 40 and 44, forming the gate oxide of transistor 18 and the insulator of capacitor 12. Carrier density 1 × 10 ¹⁶
1000 Å polycrystalline silicon 48 doped P-type at / cm ³
A bit line 20 is formed by depositing by LPCVD and patterning. See Figure 3C. The portion of polycrystalline silicon 48 facing region 40 forms the channel of transistor 18 and the portion of polycrystalline silicon of facing region 44 forms the electrode plate of capacitor 12.

4. Fill the trenches with oxide 50, such as by a sidewall process, to silicide the horizontal portion of polycrystalline silicon 48 or
Bit line 20 is formed by doping P ⁺ . Completed cell 30
Is shown in FIG.

The cell 30 has the following characteristic values. The transistor 18 is a polycrystalline silicon transistor having a channel width of 4.0 microns, a channel length of 0.7 microns, a thickness of 1000Å, and a typical leak current value of 0.5 pA. Capacitor 12 has an electrode area of about 12 square microns and the oxide insulator thickness is
It has a capacity of about 22fF at 150Å. If the cell 30 is regenerated when the accumulated voltage is attenuated to 2 V, the maximum regeneration period is 90 ms from the value of 0.5 pA at 22 fF. Since cell 30 occupies 6.25 square microns of substrate area, a 64.5 mm ² (100,000 square mil) substrate could contain approximately 4 Mbits of memory for such a cell.

A cross-sectional view of the second preferred embodiment cell 60 is shown in FIG.
The difference is that they are separated from 12 by an oxide layer 36. Similar elements in cells 30 and 60 are given the same reference numbers.
In cell 60, word line 14 / gate region 40 is formed by patterning a doped polycrystalline silicon layer deposited on oxide layer 36. After patterning, the word line 14 / gate region 40 is silicided and a layer 41 of silicide is formed to reduce the resistance of the word line. As in cell 30, insulating oxide 42 on the word lines
Are patterned and patterned to form a trench mask. However, in the case of cell 60, the step created by region 40 must be covered with graded oxide 43 to avoid the formation of spurious devices at the ends of the word line away from the trench. Oxides 42 and 43 can be co-deposited using plasma enhanced CVD to provide planarization sputtering. Other than this, the creation of the cell 60 is similar to that of the cell 30, and so are the characteristics. Transistor
Control of the channel length of 18 is easier in cell 30 than in cell 60. This is because the channel length is determined by the thickness of the diffusion layer rather than the thickness of the polycrystalline silicon layer.

Modifications of the preferred embodiment cells, such as size changes, groove formation changes, doping level changes, material changes, etc., will be apparent. Similarly, modifications of the preferred embodiment method for fabrication, such as diffusion to ion implantation, wet and dry etching, and modification of the various halocarbons for RIE, are also apparent.

BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A and 1B show an equivalent circuit diagram of a preferred embodiment dRAM cell and a local memory array structure. FIG. 2 is a schematic cross-sectional view of the dRAM cell of the first preferred embodiment. 3A to 3C show the order of steps in the case of producing the cell of the first preferred embodiment by the method of the first preferred embodiment. FIG. 4 is a schematic cross-sectional view of the dRAM cell of the second preferred embodiment. (Reference numeral) 12 …… capacitor 14 …… word line 16 …… gate 18 …… transistor 20 …… bit line 30 …… cell 32 …… silicon substrate 34 …… epitaxy layer 36 …… field oxide 38 …… Channel stop region 40 …… Buried gate region 42 …… Word line oxide 44 …… Capacitor electrode region 46 …… Capacitor insulator / gate oxide 48 …… Capacitor plate / Channel region 50 …… Oxide 60 …… Cell

Claims (4)

[Claims] 1. A substrate having a groove, an insulating layer provided on a wall of the groove, and a semiconductor layer formed on the insulating layer, the semiconductor layer being for storing charges. Source, which acts as a node
A semiconductor layer including a drain and a channel, the transistor including a transistor formed in the groove; and a gate provided in the substrate adjacent to the insulating layer and controlling a current in the channel. A semiconductor device characterized in that. 2. A crystalline silicon substrate having a groove, a silicon dioxide layer provided on a wall of the groove, and a polycrystalline silicon layer formed on the silicon dioxide layer. A polycrystalline silicon layer comprising a source, a drain and a channel which serve as a node for storing charges, the transistor comprising a transistor formed in the trench; and a polysilicon layer adjacent to the silicon dioxide layer in the substrate. And a doped region that acts as a gate for controlling a current in the channel, the semiconductor device. 3. A substrate having a groove is prepared, an insulating layer is formed on a wall of the groove, and the insulating layer has a source, a drain and a channel serving as nodes for storing charges. A semiconductor device comprising: forming a semiconductor layer having a transistor formed in the groove, and forming a gate for controlling a current in the channel in the substrate adjacent to the insulating layer. Manufacturing method. 4. A crystalline silicon substrate having a groove is prepared, a silicon dioxide layer is formed on a wall of the groove, and a source, a drain and a channel functioning as a node for storing charges on the silicon dioxide layer. Forming a polycrystalline silicon layer comprising a transistor formed in the trench, the doped region serving as a gate controlling current in the channel adjacent to the silicon dioxide layer in the substrate. A method of manufacturing a semiconductor device, comprising: forming.