JPH0673368B2 - Semiconductor memory device and manufacturing method thereof - Google Patents
Semiconductor memory device and manufacturing method thereofInfo
- Publication number
- JPH0673368B2 JPH0673368B2 JP60016934A JP1693485A JPH0673368B2 JP H0673368 B2 JPH0673368 B2 JP H0673368B2 JP 60016934 A JP60016934 A JP 60016934A JP 1693485 A JP1693485 A JP 1693485A JP H0673368 B2 JPH0673368 B2 JP H0673368B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- capacitor
- film
- conductivity type
- opening window
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 12
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 239000003990 capacitor Substances 0.000 claims description 62
- 238000003860 storage Methods 0.000 claims description 20
- 239000000758 substrate Substances 0.000 claims description 16
- 238000005530 etching Methods 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 3
- 238000000034 method Methods 0.000 description 12
- 229910004298 SiO 2 Inorganic materials 0.000 description 9
- 238000005229 chemical vapour deposition Methods 0.000 description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 239000005360 phosphosilicate glass Substances 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 230000005260 alpha ray Effects 0.000 description 4
- 230000010354 integration Effects 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 230000010365 information processing Effects 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 108091006146 Channels Proteins 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- YXTPWUNVHCYOSP-UHFFFAOYSA-N bis($l^{2}-silanylidene)molybdenum Chemical compound [Si]=[Mo]=[Si] YXTPWUNVHCYOSP-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910021344 molybdenum silicide Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体記憶装置に係り、特にキャパシタ容量を
増大せしめた１トランジスタ・１キャパシタ構造のダイ
ナミック型ランダムアクセスメモリ（Ｄ−RAM）セルに
関する。The present invention relates to a semiconductor memory device, and more particularly to a dynamic random access memory (D-RAM) cell having a one-transistor / one-capacitor structure with an increased capacitor capacity.
情報処理装置の機能拡大に伴い、該情報処理装置に具備
せしめられるＤ−RAMも大規模化されて来ており、該情
報処理装置の拡大を抑止するために、該Ｄ−RAMの高密
度高集積化が急速に進められている。Along with the expansion of the functions of the information processing apparatus, the D-RAM included in the information processing apparatus has also been increased in scale, and in order to prevent the expansion of the information processing apparatus, the high density and high density of the D-RAM are provided. Integration is proceeding rapidly.
然しながら、該Ｄ−RAMの高密度高集積化を極度に進め
た際には、セル面積の縮小に伴うキャパシタ容量の大幅
な減少のために、該キャパシタに蓄積される情報電荷量
が大幅に減少して、情報読出し精度の低下や、α線によ
るソフトエラーに対する耐性等の低下等を生じて該Ｄ−
RAMの信頼度が低下するという問題を生じており、セル
面積が小さく且つキャパシタ容量の大きいＤ−RAMセル
が要望されている。However, when the high density and high integration of the D-RAM is extremely advanced, the amount of information charges accumulated in the capacitor is greatly reduced due to the large reduction of the capacitor capacitance accompanying the reduction of the cell area. As a result, the accuracy of information reading is decreased, the resistance to a soft error due to α-rays is decreased, and the like.
There is a problem that the reliability of RAM is lowered, and a D-RAM cell having a small cell area and a large capacitor capacity is desired.
上記１トランジスタ・１キャパシタ型Ｄ−RAMセルにお
いて、キャパシタ容量を増大せしめる構造として当初提
案されたのが第３図に側断面を模式的に示すスタックド
・キャパシタ型セルである。In the above-mentioned 1-transistor / 1-capacitor type D-RAM cell, a stacked-capacitor type cell whose side section is schematically shown in FIG. 3 was initially proposed as a structure for increasing the capacitance of the capacitor.
第３図において、１はp-型シリコン基板、２はｐ型チャ
ネル・カット領域、３はフィールド酸化膜、４はゲート
酸化膜、５はゲート電極、６はワード線（隣接する他セ
ルのトランスファ・トランジスタのゲート電極）、７は
第１の絶縁膜、８はn+型ドレイン領域、９は蓄積ノード
となるn+型領域、10は第１のキャパシタ電極、11は誘電
体膜、12は第２のキャパシタ電極、Trはトランスファ・
トランジスタ、Ｃはキャパシタを示す。In FIG. 3, 1 is a p - type silicon substrate, 2 is a p-type channel cut region, 3 is a field oxide film, 4 is a gate oxide film, 5 is a gate electrode, 6 is a word line (transfer of an adjacent other cell). -Transistor gate electrode), 7 is a first insulating film, 8 is an n + type drain region, 9 is an n + type region serving as a storage node, 10 is a first capacitor electrode, 11 is a dielectric film, and 12 is The second capacitor electrode, Tr is the transfer
A transistor and C are capacitors.
このセル構造によれば、電荷蓄積用の第１のキャパシタ
電極が自己セルのトランスファ・トランジスタTrのゲー
ト電極５と隣接するワード線６の上部にまで延在せしめ
られるので、上記第２のn+型領域８をキャパシタの一電
極とする通常のＤ−RAMセルに比べ、キャパシタ容量は
２〜３倍程度に増大される。According to this cell structure, since the first capacitor electrode for charge storage is extended to the upper part of the word line 6 adjacent to the gate electrode 5 of the transfer transistor Tr of the self cell, the second n + The capacitance of the capacitor is increased by a factor of 2 to 3 as compared with an ordinary D-RAM cell using the mold region 8 as one electrode of the capacitor.
然しながら高集積化が大幅に進んでいる状況においては
上記２〜３倍程度の容量増大では、蓄積情報の検出精度
及びα線ソフトエラー耐性の面で不充分であり、更にキ
ャパシタ容量を増大せしめる構造として従来提供された
のがトレンチ・キャパシタ型セルである。However, in a situation where the degree of high integration is significantly advanced, the capacitance increase of about 2 to 3 times is insufficient in terms of detection accuracy of stored information and α ray soft error resistance, and a structure that further increases the capacitance of the capacitor. Conventionally provided is a trench capacitor type cell.
第４図は上記トレンチ・キャパシタ型セルの側断面を模
式的に示したもので、図中、12a及び12bはトレンチ、13
a及び13bは電荷蓄積領域（空乏層）、14はキャパシタ電
極、その他の符号は第３図と同一対象物を示す。FIG. 4 is a schematic side sectional view of the above-mentioned trench capacitor type cell, in which 12a and 12b are trenches and 13
Reference numerals a and 13b denote charge storage regions (depletion layers), 14 denotes a capacitor electrode, and other reference numerals denote the same objects as in FIG.
このトレンチ・キャパシタ型セルは、トレンチの深さを
深くすることによって、同一セル面積を有する前記スタ
ックド・キャパシタ型セルに比べ、キャパシタ容量を更
に大幅に増大出来るという利点を持っている。This trench capacitor type cell has an advantage that by increasing the depth of the trench, the capacitance of the capacitor can be significantly increased as compared with the stacked capacitor type cell having the same cell area.
然し該トレンチ・キャパシタ型Ｄ−RAMセルにおいて
は、キャパシタ電極14に印加される電圧によってトレン
チ12a,12b等の周囲に形成される空乏層からなる電荷蓄
積領域13a,13b等が大きく拡がる（図のようにバックバ
イアスが強く機能するトレンチ先端部とチャネル・カッ
ト領域が機能するトレンチ基部との中間部で特に大きく
拡がる）ために、隣接するセルのトレンチ例えば12aと1
2bを接近して設けた場合、蓄積電荷のリークを生じて情
報が失われるという現象を生じる。However, in the trench capacitor type D-RAM cell, the charge storage regions 13a, 13b and the like formed of depletion layers formed around the trenches 12a, 12b and the like are greatly expanded by the voltage applied to the capacitor electrode 14 (see the figure). Such as 12a and 1 of the adjacent cell trenches, because the back bias is particularly wide at the middle between the trench tip and the channel cut region.
When 2b is provided close to each other, a phenomenon occurs in which accumulated charge leaks and information is lost.
そのため各セル間の分離領域幅即ちフィールド酸化膜３
が配設される領域の幅を広くとる必要があり、これによ
って集積度の向上が妨げられるという問題があった。Therefore, the isolation region width between each cell, that is, the field oxide film 3
There is a problem in that it is necessary to widen the width of the region in which is provided, which hinders the improvement of the degree of integration.
上記問題点は、一導電型半導体基板上に形成されたMIS
型トランスファトランジスタと、該トランジスタを覆っ
て該一導電型半導体基板上に形成された絶縁膜と、 該絶縁膜に形成され、かつ該トランジスタの蓄積ノード
となる反対導電型領域を表出する開口窓と、 該開口窓の側壁面に形成され、下端部が該反対導電型領
域と電気的に接続し、かつ該絶縁膜表面には実質的に延
在しないように形成される筒状の第１のキャパシタ電極
と、 少なくとも前記開口窓の側壁面において該第１のキャパ
シタ電極を覆うように形成された誘電体膜と、 該誘電体膜表面に、該第１のキャパシタ電極と電気的に
接続しないように、且つ前記絶縁膜表面に延在するよう
に形成される第２のキャパシタ電極と を有してなることを特徴とする半導体記憶装置，あるい
は、一導電型半導体基板上に形成されたMIS型トランス
ファトランジスタを覆うように、該一導電型半導体基板
表面に絶縁膜を形成する工程と、 次いで、該絶縁膜を異方性エッチングして、選択的に該
トランスファトランジスタの反対導電型のソースまたは
ドレイン領域を露出する開口窓を形成する工程と、 次いで、該開口窓の底面および側壁面から該絶縁膜上面
に延在するように第１の導電膜を被着形成する工程と、 次いで、該第１の導電膜を、該絶縁膜上面から除去しか
つ該開口窓の少なくとも側壁面には残すように、異方性
エッチングする工程と、 次いで、該第１の導電膜表面を覆うように誘電体膜を形
成する工程と、 次いで、該誘電体膜表面に、前記第１の導電膜と電気的
に接続しないように、第２の導電膜を被着形成する工程
と を有する半導体記憶装置の製造方法によって解決され
る。The above problems are caused by the MIS formed on the one-conductivity type semiconductor substrate.
Type transfer transistor, an insulating film formed on the one conductivity type semiconductor substrate to cover the transistor, and an opening window exposing the opposite conductivity type region formed in the insulating film and serving as a storage node of the transistor A first cylindrical member formed on a side wall surface of the opening window so that a lower end portion thereof is electrically connected to the opposite conductivity type region and does not substantially extend to a surface of the insulating film. Capacitor electrode, a dielectric film formed so as to cover the first capacitor electrode at least on the side wall surface of the opening window, and the dielectric film surface is not electrically connected to the first capacitor electrode And a second capacitor electrode formed so as to extend on the surface of the insulating film, or a MIS formed on a semiconductor substrate of one conductivity type. Type tran A step of forming an insulating film on the surface of the semiconductor substrate of one conductivity type so as to cover the transfer transistor, and then anisotropically etching the insulating film to selectively form a source or drain of the opposite conductivity type of the transfer transistor. A step of forming an opening window exposing the region, a step of depositing and forming a first conductive film so as to extend from the bottom surface and side wall surface of the opening window to the insulating film upper surface, A step of anisotropically etching so that the first conductive film is removed from the upper surface of the insulating film and left on at least the side wall surface of the opening window; and then, a dielectric is formed so as to cover the surface of the first conductive film. Manufacture of a semiconductor memory device including a step of forming a film, and then a step of depositing and forming a second conductive film on the surface of the dielectric film so as not to be electrically connected to the first conductive film. Solved by the method It
即ち本発明のＤ−RAMセルにおいては、トランスファ・
トランジスタの上部に厚い絶縁膜を設け、該絶縁膜に該
絶縁膜を貫通して該トランスファ・トランジスタの蓄積
ノードとなる不純物拡散領域に接する筒状のキャパシタ
を形成するものであり、該絶縁膜を厚く形成することに
よってキャパシタ容量の大幅な増大が可能であるので、
情報の検出精度及びα線ソフトエラー耐性の向上が図
れ、且つ隣接するセルのキャパシタとの間が該絶縁膜に
よって完全に分離されるので、蓄積電荷のリークを生ず
ることがなく蓄積情報の信頼度は向上する。That is, in the D-RAM cell of the present invention, the transfer
A thick insulating film is provided on the upper part of the transistor, and a cylindrical capacitor is formed through the insulating film so as to come into contact with an impurity diffusion region serving as a storage node of the transfer transistor. By making it thick, it is possible to greatly increase the capacitance of the capacitor.
Since the information detection accuracy and the α-ray soft error resistance can be improved and the capacitor of the adjacent cell is completely separated by the insulating film, the stored information does not leak and the reliability of the stored information can be improved. Will improve.
以下本発明を図示実施例により、具体的に説明する。 Hereinafter, the present invention will be specifically described with reference to illustrated embodiments.
第１図は本発明に係わる１トランジスタ・１キャパシタ
構造のＤ−RAMセルの一実施例を示す模式平面図（ａ）
及び模式側断面図（ｂ）で、第２図はその製造方法を示
す工程断面図である。FIG. 1 is a schematic plan view showing an embodiment of a D-RAM cell having a one-transistor / one-capacitor structure according to the present invention (a).
FIG. 2 is a schematic cross-sectional view (b), and FIG. 2 is a process cross-sectional view showing the manufacturing method.
全図を通じ同一対象物は同一符号で示す。The same object is denoted by the same symbol throughout the drawings.
第１図において、１はp-型シリコン基板、２はｐ型チャ
ネル・カット領域、３はフィールド酸化膜、４はゲート
酸化膜、5a,5b,5cは第１の多結晶シリコン層PAよりなる
ゲート電極（ワード線）、８はn+型ドレイン領域、９は
蓄積ノードとなるn+型領域、21は化学気相成長（CVD）
法で形成した厚さ例えば１〜２μｍ程度の二酸化シリコ
ン（SiO2）絶縁膜、22は蓄積ノードとなるn+型領域を表
出する例えば1.5〜２μｍ□程度の第１のスルーホー
ル、23はn+型ドレイン領域を表出する例えば0.7〜１μ
ｍ□程度の第２のスルーホール、24は第２の多結晶シリ
コン層（PB）よりなる電荷蓄積用キャパシタ電極、25は
同じくPBよりなるドレイン電極、26は厚さ例えば100Å
程度のSiO2よりなる誘電体膜、27は第３の多結晶シリコ
ン層PCよりなる対向キャパシタ電極、28は燐珪酸ガラス
（PSG）絶縁膜、29はコンタクト窓、30はアルミニウム
等よりなるビット配線、Trはトランスファ・トランジス
タ、Ｃはキャパシタを示す。In FIG. 1, 1 is a p - type silicon substrate, 2 is a p-type channel cut region, 3 is a field oxide film, 4 is a gate oxide film, and 5a, 5b and 5c are the first polycrystalline silicon layer PA. Gate electrode (word line), 8 is an n + type drain region, 9 is an n + type region serving as a storage node, 21 is chemical vapor deposition (CVD)
A silicon dioxide (SiO 2 ) insulating film having a thickness of, for example, about 1 to 2 μm formed by the method, 22 denotes an n + -type region serving as a storage node, for example, a first through hole having a thickness of about 1.5 to 2 μm, and 23 denotes Exposing the n + type drain region, for example, 0.7 to 1 μm
A second through hole of about m square, 24 is a capacitor electrode for charge storage made of a second polycrystalline silicon layer (PB), 25 is a drain electrode also made of PB, 26 is a thickness of, for example, 100Å
Dielectric film made of SiO 2 to the extent, 27 is a counter capacitor electrode made of a third polycrystalline silicon layer PC, 28 is a phosphosilicate glass (PSG) insulating film, 29 is a contact window, 30 is a bit wiring made of aluminum or the like. , Tr is a transfer transistor, and C is a capacitor.
同図に示すように本発明に係わるＤ−RAMセルは、 トランスファ・トランジスタTrの上部に厚いSiO2絶縁膜
21を設け、このSiO2絶縁膜21にトランスファ・トランジ
スタTrの蓄積ノードとなるn+型領域９を表出するキャパ
スタ用の第１のスルーホール22とn+型ドレイン領域８を
表出する第２のスルーホール23を形成し、 上記第１のスルーホール22内にトランスファ・トランジ
スタTrの蓄積ノードとなるn+型領域９に下端部が接する
筒状の電荷蓄積用キャパシタ電極24と、 この電極24の内面と上面及びこの電極24の底部に表出す
るn+型領域９の表面に形成された誘電体膜26と、 この電荷蓄積用キャパシタ電極24内に上記誘電体膜26を
介して埋め込まれ、上部がSiO2絶縁膜21に延在する対向
キャパシタ電極27とよりなるキャパシタＣが設けられ、 トランスファ・トランジスタTrのn+型ドレイン領域８
が、上記第２のスルーホール23内に埋め込まれたドレイ
ン電極25及びコンタクト窓29を介しビット配線30に接続
されてなっている。As shown in the figure, the D-RAM cell according to the present invention has a thick SiO 2 insulating film on the transfer transistor Tr.
A first through hole 22 for a capacitor and a n + type drain region 8 which exposes an n + type region 9 serving as a storage node of the transfer transistor Tr are provided on the SiO 2 insulating film 21. And a cylindrical charge storage capacitor electrode 24 whose lower end is in contact with the n + -type region 9 which is the storage node of the transfer transistor Tr in the first through hole 22. A dielectric film 26 formed on the inner and upper surfaces of 24 and the surface of the n + type region 9 exposed on the bottom of the electrode 24, and embedded in the charge storage capacitor electrode 24 via the dielectric film 26. A capacitor C having an opposing capacitor electrode 27 whose upper portion extends to the SiO 2 insulating film 21 is provided, and the n + type drain region 8 of the transfer transistor Tr is provided.
However, it is connected to the bit line 30 through the drain electrode 25 and the contact window 29 embedded in the second through hole 23.
上記Ｄ−RAMセルは、例えば以下に第２図（ａ）乃至
（ｅ）に示す工程断面図を参照して説明する方法によっ
て形成される。The D-RAM cell is formed, for example, by the method described below with reference to process sectional views shown in FIGS.
第２図（ａ）参照 通常の方法によりp-型シリコン基板１上にトランスファ
・トランジスタTrを形成した後、CVD法により該基板上
に厚さ例えば１〜２μｍ程度のSiO2絶縁膜21を形成し、 次いで通常のリアクティブ・イオンエッチング（RIE）
法により上記SiO2絶縁膜21に蓄積ノードとなるn+型領域
９を表出する例えば1.5〜２μｍ□程度の第１のスルー
ホール22、及びn+型ドレイン領域８を表出する例えば0.
7〜１μｍ□程度の第２のスルーホール23を形成する。See FIG. 2 (a). After the transfer transistor Tr is formed on the p − type silicon substrate 1 by the usual method, the SiO 2 insulating film 21 having a thickness of, for example, about 1 to 2 μm is formed on the substrate by the CVD method. Then normal reactive ion etching (RIE)
The n + type region 9 to be the storage node is exposed in the SiO 2 insulating film 21 by the method, for example, the first through hole 22 of about 1.5 to 2 μm □ and the n + type drain region 8 are exposed, for example, 0.
A second through hole 23 of about 7 to 1 μm □ is formed.
第２図（ｂ）参照 次いで該基板上にCVD法により第２のスルーホール23を
埋める厚さ、例えば5000Å程度の第２の多結晶シリコン
層PBを形成する。この際第１のスルーホール22は埋まら
ず、その側壁面及び底面に上記厚さのPB層が形成され
る。See FIG. 2B. Then, a second polycrystalline silicon layer PB having a thickness of, for example, about 5000 Å to fill the second through hole 23 is formed on the substrate by the CVD method. At this time, the first through hole 22 is not filled, and the PB layer having the above thickness is formed on the side wall surface and the bottom surface thereof.
第２図（ｃ）参照 次いでRIE法で前面エッチングを行い、SiO2絶縁膜21の
上面及び第１のスルーホール22内の蓄積ノードとなるn+
型領域９面を表出させる。ここで、第１のスルーホール
22内には、その側壁面に沿って下端部が前記n+型領域９
に接する筒状のPB層が残留する。次いで熱酸化法により
PB層の表面及びn+型領域９の表出面に厚さ例えば100Å
程度のSiO2誘電体膜26を形成する。Next, as shown in FIG. 2 (c), front surface etching is performed by the RIE method, and n + becomes the storage node in the upper surface of the SiO 2 insulating film 21 and the first through hole 22.
The surface of the mold region 9 is exposed. Where the first through hole
The lower end of the n + -type region 9 is located along the side wall of the n-type region 9.
The cylindrical PB layer contacting with remains. Then by thermal oxidation method
The thickness of the surface of the PB layer and the exposed surface of the n + type region 9, for example, 100 Å
A SiO 2 dielectric film 26 is formed to a degree.
なお第１のスルーホール22内のPB層は筒状の電荷蓄積用
キャパシタ電極24となり、第２のスルーホール23内のPB
層はドレイン電極25となる。The PB layer in the first through hole 22 becomes a cylindrical charge storage capacitor electrode 24, and the PB layer in the second through hole 23 is formed.
The layer becomes the drain electrode 25.
第２図（ｄ）参照 次いで該基板上にCVD法により上記筒状の電荷蓄積用キ
ャパシタ電極24の内部を埋める例えば5000Å程度の第３
の多結晶シリコン層PCを形成し、次いでRIE法により該P
C層に前記ドレイン電極25の上面を表出する開孔31を形
成する。See FIG. 2 (d). Then, the inside of the cylindrical charge-storing capacitor electrode 24 is filled on the substrate by the CVD method, for example, the third capacitor of about 5000 Å.
Polycrystalline silicon layer PC is formed, and then the P layer is formed by the RIE method.
An opening 31 exposing the upper surface of the drain electrode 25 is formed in the C layer.
ここでPC層は対向キャパシタ電極27となる。Here, the PC layer becomes the counter capacitor electrode 27.
第２図（ｅ）参照 次いで該基板上にCVD法により厚さ１μｍ程度のPSG絶縁
膜28を形成し、 通常の方法により該PSG絶縁膜28にドレイン電極25の上
面を表出するコンタクト窓29を形成し、 通常の方法により該絶縁膜29上に上記コンタクト窓29部
においてドレイン電極25に接するビット配線30を形成す
る。Then, a PSG insulating film 28 having a thickness of about 1 μm is formed on the substrate by a CVD method, and a contact window 29 exposing the upper surface of the drain electrode 25 on the PSG insulating film 28 is formed by a usual method. And a bit line 30 in contact with the drain electrode 25 in the contact window 29 is formed on the insulating film 29 by a conventional method.
そして、以後図示しないカバー絶縁膜の形成等を行って
本発明に係わるＤ−RAMセルが完成する。Then, a cover insulating film (not shown) is formed thereafter to complete the D-RAM cell according to the present invention.
上記実施例の説明から明らかなように、本発明に係わる
Ｄ−RAMセルにおいては、原理的に、CVD法によって導電
層が底部まで成長出来る深さであれば筒型のキャパシタ
をいくらでも深く形成することが可能である。従ってキ
ャパシタ容量を従来に比べ大幅に増大させることが出来
る。As is clear from the description of the above embodiment, in the D-RAM cell according to the present invention, in principle, a cylindrical capacitor is formed as deep as possible so long as the conductive layer can grow to the bottom by the CVD method. It is possible. Therefore, the capacitance of the capacitor can be significantly increased as compared with the conventional one.
また該筒型のキャパシタは絶縁膜内に設けられるので、
隣接するセルの筒型キャパシタとの間が該絶縁膜で分離
されることになり、情報電荷のリークは完全に防止され
る。Further, since the cylindrical capacitor is provided in the insulating film,
The insulating film separates the cylindrical capacitors of adjacent cells from each other, and the leakage of information charges is completely prevented.
更に又、キャパシタが絶縁膜内に設けられることによ
り、α線の入射によりシリコン基板内に発生した電荷が
キャパシタに到達することがなく、α線ソフトエラー耐
性も増大する。Furthermore, since the capacitor is provided in the insulating film, the charge generated in the silicon substrate due to the incidence of α rays does not reach the capacitor, and the α-ray soft error resistance is increased.
なおキャパシタ電極は上記実施例に示す多結晶シリコン
に限られるものではなく、モリブデン・シリサイド等他
の導電物質であっても良い。The capacitor electrode is not limited to the polycrystalline silicon shown in the above embodiment, but may be another conductive material such as molybdenum silicide.
以上説明のように本発明によれば、１トランジスタ・１
キャパシタ構造のダイナミック型ランダムアクセスメモ
リ（Ｄ−RAM）セルの、キャパシタ容量を大幅に増大
し、隣接するキャパシタ間の情報電荷のリークを無く
し、且つα線ソフトエラー耐性を向上せしめることがで
きるので、その信頼度が向上する。As described above, according to the present invention, one transistor
Since the capacitance of a dynamic random access memory (D-RAM) cell having a capacitor structure can be significantly increased, the leakage of information charges between adjacent capacitors can be eliminated, and the α-ray soft error resistance can be improved. The reliability is improved.
第１図は本発明に係わる１トランジスタ・１キャパシタ
構造のＤ−RAMセルの一実施例を示す模式平面図（ａ）
及び模式側断面図（ｂ）、 第２図（ａ）乃至（ｅ）はその製造方法を示す工程断面
図、 第３図はスタックド・キャパシタ型Ｄ−RAMセルの側断
面図、 第４図はトレンチ・キャパシタ型セルの側断面図であ
る。 図において、 5a,5b,5cはゲート電極（ワード線） ８はn+型ドレイン領域、 ９は蓄積ノードとなるn+型領域、 21は二酸化シリコン絶縁膜、 22は第１のスルーホール、 23は第２のスルーホール、 24は電荷蓄積用キャパシタ電極、 25はドレイン電極、 26は誘電体膜、 27は対向キャパシタ電極、 28は燐珪酸ガラス絶縁膜、 29はコンタクト窓、 30はビット配線、 Trはトランスファ・トランジスタ、 Ｃはキャパシタ を示す。FIG. 1 is a schematic plan view showing an embodiment of a D-RAM cell having a one-transistor / one-capacitor structure according to the present invention (a).
And schematic side sectional views (b), FIGS. 2 (a) to (e) are process sectional views showing the manufacturing method, FIG. 3 is a side sectional view of a stacked capacitor type D-RAM cell, and FIG. It is a sectional side view of a trench capacitor type cell. In the figure, 5a, 5b and 5c are gate electrodes (word lines) 8 is an n + type drain region, 9 is an n + type region to be a storage node, 21 is a silicon dioxide insulating film, 22 is a first through hole, 23 Is a second through hole, 24 is a charge storage capacitor electrode, 25 is a drain electrode, 26 is a dielectric film, 27 is a counter capacitor electrode, 28 is a phosphosilicate glass insulating film, 29 is a contact window, 30 is a bit line, Tr is a transfer transistor and C is a capacitor.
Claims (2)
トランスファトランジスタと、 該トランジスタを覆って該一導電型半導体基板上に形成
された絶縁膜と、 該絶縁膜に形成され、かつ該トランジスタの蓄積ノード
となる反対導電型領域を表出する開口窓と、 該開口窓の側壁面に形成され、下端部が該反対導電型領
域と電気的に接続し、かつ該絶縁膜表面には実質的に延
在しないように形成される筒状の第１のキャパシタ電極
と、 少なくとも前記開口窓の側壁面において該第１のキャパ
シタ電極を覆うように形成された誘電体膜と、 該誘電体膜表面に、該第１のキャパシタ電極と電気的に
接続しないように、且つ前記絶縁膜表面に延在するよう
に形成される第２のキャパシタ電極と を有してなることを特徴とする半導体記憶装置。1. A MIS transfer transistor formed on a semiconductor substrate of one conductivity type, an insulating film formed on the semiconductor substrate of one conductivity type to cover the transistor, and formed on the insulating film. An opening window that exposes an opposite conductivity type region serving as a storage node of a transistor, a side wall surface of the opening window, a lower end portion of which is electrically connected to the opposite conductivity type region, and a surface of the insulating film is formed. A cylindrical first capacitor electrode formed so as not to extend substantially, a dielectric film formed so as to cover the first capacitor electrode at least on the side wall surface of the opening window, and the dielectric And a second capacitor electrode formed on the film surface so as not to be electrically connected to the first capacitor electrode and extending to the insulating film surface. Storage device.
トランスファトランジスタを覆うように、該一導電型半
導体基板表面に絶縁膜を形成する工程と、 次いで、該絶縁膜を異方性エッチングして、選択的に該
トランスファトランジスタの反対導電型のソースまたは
ドレイン領域を露出する開口窓を形成する工程と、 次いで、該開口窓の底面および側壁面から該絶縁膜上面
に延在するように第１の導電膜を被着形成する工程と、 次いで、該第１の導電膜を、該絶縁膜上面から除去しか
つ該開口窓の少なくとも側壁面には残すように、異方性
エッチングする工程と、 次いで、該第１の導電膜表面を覆うように誘電体膜を形
成する工程と、 次いで、該誘電体膜表面に、前記第１の導電膜と電気的
に接続しないように、第２の導電膜を被着形成する工程
と を有する半導体記憶装置の製造方法。2. A step of forming an insulating film on the surface of the one conductivity type semiconductor substrate so as to cover the MIS transfer transistor formed on the one conductivity type semiconductor substrate, and then anisotropically etching the insulating film. And selectively forming an opening window that exposes the source or drain region of the opposite conductivity type of the transfer transistor, and then extending from the bottom surface and side wall surface of the opening window to the upper surface of the insulating film. A step of depositing and forming a first conductive film, and a step of anisotropically etching the first conductive film so as to remove it from the upper surface of the insulating film and leave at least the side wall surface of the opening window. A step of forming a dielectric film so as to cover the surface of the first conductive film, and a second step of electrically connecting the surface of the dielectric film to the first conductive film. The conductive film of Method of manufacturing a semiconductor memory device having a step.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60016934A JPH0673368B2 (en) | 1985-01-31 | 1985-01-31 | Semiconductor memory device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60016934A JPH0673368B2 (en) | 1985-01-31 | 1985-01-31 | Semiconductor memory device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61176148A JPS61176148A (en) | 1986-08-07 |
| JPH0673368B2 true JPH0673368B2 (en) | 1994-09-14 |
Family
ID=11929950
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60016934A Expired - Lifetime JPH0673368B2 (en) | 1985-01-31 | 1985-01-31 | Semiconductor memory device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0673368B2 (en) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2741857B2 (en) * | 1987-05-11 | 1998-04-22 | 株式会社日立製作所 | Semiconductor storage device |
| JP2621181B2 (en) * | 1987-06-12 | 1997-06-18 | 日本電気株式会社 | MIS type semiconductor memory device |
| JP2613077B2 (en) * | 1988-03-25 | 1997-05-21 | 富士通株式会社 | Method for manufacturing semiconductor device |
| JP2723530B2 (en) * | 1988-04-13 | 1998-03-09 | 日本電気株式会社 | Method for manufacturing dynamic random access memory device |
| JPH0221652A (en) * | 1988-07-08 | 1990-01-24 | Mitsubishi Electric Corp | Semiconductor storage device |
| JPH03116965A (en) * | 1989-09-29 | 1991-05-17 | Mitsubishi Electric Corp | Memory cell structure |
| JP2996409B2 (en) * | 1990-02-06 | 1999-12-27 | 三菱電機株式会社 | Semiconductor device and manufacturing method thereof |
| US6744091B1 (en) | 1995-01-31 | 2004-06-01 | Fujitsu Limited | Semiconductor storage device with self-aligned opening and method for fabricating the same |
| JP3623834B2 (en) * | 1995-01-31 | 2005-02-23 | 富士通株式会社 | Semiconductor memory device and manufacturing method thereof |
| JP3941133B2 (en) | 1996-07-18 | 2007-07-04 | 富士通株式会社 | Semiconductor device and manufacturing method thereof |
| JP2007189008A (en) * | 2006-01-12 | 2007-07-26 | Elpida Memory Inc | Semiconductor memory device and method of fabricating same |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53108392A (en) * | 1977-03-04 | 1978-09-21 | Hitachi Ltd | Semiconductor device |
| JPS55154762A (en) * | 1979-05-22 | 1980-12-02 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Semiconductor memory |
-
1985
- 1985-01-31 JP JP60016934A patent/JPH0673368B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61176148A (en) | 1986-08-07 |
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