JPH0673368B2 - Semiconductor memory device and manufacturing method thereof - Google Patents

Semiconductor memory device and manufacturing method thereof

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Publication number
JPH0673368B2
JPH0673368B2 JP60016934A JP1693485A JPH0673368B2 JP H0673368 B2 JPH0673368 B2 JP H0673368B2 JP 60016934 A JP60016934 A JP 60016934A JP 1693485 A JP1693485 A JP 1693485A JP H0673368 B2 JPH0673368 B2 JP H0673368B2
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JP
Japan
Prior art keywords
insulating film
formed
surface
conductivity type
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP60016934A
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Japanese (ja)
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JPS61176148A (en
Inventor
泰示 江間
Original Assignee
富士通株式会社
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Publication date
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Priority to JP60016934A priority Critical patent/JPH0673368B2/en
Publication of JPS61176148A publication Critical patent/JPS61176148A/en
Publication of JPH0673368B2 publication Critical patent/JPH0673368B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/108Dynamic random access memory structures
    • H01L27/10844Multistep manufacturing methods
    • H01L27/10847Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells
    • H01L27/1085Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells with at least one step of making the capacitor or connections thereto
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/108Dynamic random access memory structures
    • H01L27/10805Dynamic random access memory structures with one-transistor one-capacitor memory cells
    • H01L27/10808Dynamic random access memory structures with one-transistor one-capacitor memory cells the storage electrode stacked over transistor

Description

The present invention relates to a semiconductor memory device, and more particularly to a dynamic random access memory (D-RAM) cell having a one-transistor / one-capacitor structure with an increased capacitor capacity.

Along with the expansion of the functions of the information processing apparatus, the D-RAM included in the information processing apparatus has also been increased in scale, and in order to prevent the expansion of the information processing apparatus, the high density and high density of the D-RAM are provided. Integration is proceeding rapidly.

However, when the high density and high integration of the D-RAM is extremely advanced, the amount of information charges accumulated in the capacitor is greatly reduced due to the large reduction of the capacitor capacitance accompanying the reduction of the cell area. As a result, the accuracy of information reading is decreased, the resistance to a soft error due to α-rays is decreased, and the like.
There is a problem that the reliability of RAM is lowered, and a D-RAM cell having a small cell area and a large capacitor capacity is desired.

[Conventional technology]

In the above-mentioned 1-transistor / 1-capacitor type D-RAM cell, a stacked-capacitor type cell whose side section is schematically shown in FIG. 3 was initially proposed as a structure for increasing the capacitance of the capacitor.

In FIG. 3, 1 is a p - type silicon substrate, 2 is a p-type channel cut region, 3 is a field oxide film, 4 is a gate oxide film, 5 is a gate electrode, 6 is a word line (transfer of an adjacent other cell). -Transistor gate electrode), 7 is a first insulating film, 8 is an n + type drain region, 9 is an n + type region serving as a storage node, 10 is a first capacitor electrode, 11 is a dielectric film, and 12 is The second capacitor electrode, Tr is the transfer
A transistor and C are capacitors.

According to this cell structure, since the first capacitor electrode for charge storage is extended to the upper part of the word line 6 adjacent to the gate electrode 5 of the transfer transistor Tr of the self cell, the second n + The capacitance of the capacitor is increased by a factor of 2 to 3 as compared with an ordinary D-RAM cell using the mold region 8 as one electrode of the capacitor.

However, in a situation where the degree of high integration is significantly advanced, the capacitance increase of about 2 to 3 times is insufficient in terms of detection accuracy of stored information and α ray soft error resistance, and a structure that further increases the capacitance of the capacitor. Conventionally provided is a trench capacitor type cell.

FIG. 4 is a schematic side sectional view of the above-mentioned trench capacitor type cell, in which 12a and 12b are trenches and 13
Reference numerals a and 13b denote charge storage regions (depletion layers), 14 denotes a capacitor electrode, and other reference numerals denote the same objects as in FIG.

This trench capacitor type cell has an advantage that by increasing the depth of the trench, the capacitance of the capacitor can be significantly increased as compared with the stacked capacitor type cell having the same cell area.

[Problems to be solved by the invention]

However, in the trench capacitor type D-RAM cell, the charge storage regions 13a, 13b and the like formed of depletion layers formed around the trenches 12a, 12b and the like are greatly expanded by the voltage applied to the capacitor electrode 14 (see the figure). Such as 12a and 1 of the adjacent cell trenches, because the back bias is particularly wide at the middle between the trench tip and the channel cut region.
When 2b is provided close to each other, a phenomenon occurs in which accumulated charge leaks and information is lost.

Therefore, the isolation region width between each cell, that is, the field oxide film 3
There is a problem in that it is necessary to widen the width of the region in which is provided, which hinders the improvement of the degree of integration.

[Means for solving problems]

The above problems are caused by the MIS formed on the one-conductivity type semiconductor substrate.
Type transfer transistor, an insulating film formed on the one conductivity type semiconductor substrate to cover the transistor, and an opening window exposing the opposite conductivity type region formed in the insulating film and serving as a storage node of the transistor A first cylindrical member formed on a side wall surface of the opening window so that a lower end portion thereof is electrically connected to the opposite conductivity type region and does not substantially extend to a surface of the insulating film. Capacitor electrode, a dielectric film formed so as to cover the first capacitor electrode at least on the side wall surface of the opening window, and the dielectric film surface is not electrically connected to the first capacitor electrode And a second capacitor electrode formed so as to extend on the surface of the insulating film, or a MIS formed on a semiconductor substrate of one conductivity type. Type tran A step of forming an insulating film on the surface of the semiconductor substrate of one conductivity type so as to cover the transfer transistor, and then anisotropically etching the insulating film to selectively form a source or drain of the opposite conductivity type of the transfer transistor. A step of forming an opening window exposing the region, a step of depositing and forming a first conductive film so as to extend from the bottom surface and side wall surface of the opening window to the insulating film upper surface, A step of anisotropically etching so that the first conductive film is removed from the upper surface of the insulating film and left on at least the side wall surface of the opening window; and then, a dielectric is formed so as to cover the surface of the first conductive film. Manufacture of a semiconductor memory device including a step of forming a film, and then a step of depositing and forming a second conductive film on the surface of the dielectric film so as not to be electrically connected to the first conductive film. Solved by the method It

[Action]

That is, in the D-RAM cell of the present invention, the transfer
A thick insulating film is provided on the upper part of the transistor, and a cylindrical capacitor is formed through the insulating film so as to come into contact with an impurity diffusion region serving as a storage node of the transfer transistor. By making it thick, it is possible to greatly increase the capacitance of the capacitor.
Since the information detection accuracy and the α-ray soft error resistance can be improved and the capacitor of the adjacent cell is completely separated by the insulating film, the stored information does not leak and the reliability of the stored information can be improved. Will improve.

〔Example〕

 Hereinafter, the present invention will be specifically described with reference to illustrated embodiments.

FIG. 1 is a schematic plan view showing an embodiment of a D-RAM cell having a one-transistor / one-capacitor structure according to the present invention (a).
FIG. 2 is a schematic cross-sectional view (b), and FIG. 2 is a process cross-sectional view showing the manufacturing method.

The same object is denoted by the same symbol throughout the drawings.

In FIG. 1, 1 is a p - type silicon substrate, 2 is a p-type channel cut region, 3 is a field oxide film, 4 is a gate oxide film, and 5a, 5b and 5c are the first polycrystalline silicon layer PA. Gate electrode (word line), 8 is an n + type drain region, 9 is an n + type region serving as a storage node, 21 is chemical vapor deposition (CVD)
A silicon dioxide (SiO 2 ) insulating film having a thickness of, for example, about 1 to 2 μm formed by the method, 22 denotes an n + -type region serving as a storage node, for example, a first through hole having a thickness of about 1.5 to 2 μm, and 23 denotes Exposing the n + type drain region, for example, 0.7 to 1 μm
A second through hole of about m square, 24 is a capacitor electrode for charge storage made of a second polycrystalline silicon layer (PB), 25 is a drain electrode also made of PB, 26 is a thickness of, for example, 100Å
Dielectric film made of SiO 2 to the extent, 27 is a counter capacitor electrode made of a third polycrystalline silicon layer PC, 28 is a phosphosilicate glass (PSG) insulating film, 29 is a contact window, 30 is a bit wiring made of aluminum or the like. , Tr is a transfer transistor, and C is a capacitor.

As shown in the figure, the D-RAM cell according to the present invention has a thick SiO 2 insulating film on the transfer transistor Tr.
A first through hole 22 for a capacitor and a n + type drain region 8 which exposes an n + type region 9 serving as a storage node of the transfer transistor Tr are provided on the SiO 2 insulating film 21. And a cylindrical charge storage capacitor electrode 24 whose lower end is in contact with the n + -type region 9 which is the storage node of the transfer transistor Tr in the first through hole 22. A dielectric film 26 formed on the inner and upper surfaces of 24 and the surface of the n + type region 9 exposed on the bottom of the electrode 24, and embedded in the charge storage capacitor electrode 24 via the dielectric film 26. A capacitor C having an opposing capacitor electrode 27 whose upper portion extends to the SiO 2 insulating film 21 is provided, and the n + type drain region 8 of the transfer transistor Tr is provided.
However, it is connected to the bit line 30 through the drain electrode 25 and the contact window 29 embedded in the second through hole 23.

The D-RAM cell is formed, for example, by the method described below with reference to process sectional views shown in FIGS.

See FIG. 2 (a). After the transfer transistor Tr is formed on the p type silicon substrate 1 by the usual method, the SiO 2 insulating film 21 having a thickness of, for example, about 1 to 2 μm is formed on the substrate by the CVD method. Then normal reactive ion etching (RIE)
The n + type region 9 to be the storage node is exposed in the SiO 2 insulating film 21 by the method, for example, the first through hole 22 of about 1.5 to 2 μm □ and the n + type drain region 8 are exposed, for example, 0.
A second through hole 23 of about 7 to 1 μm □ is formed.

See FIG. 2B. Then, a second polycrystalline silicon layer PB having a thickness of, for example, about 5000 Å to fill the second through hole 23 is formed on the substrate by the CVD method. At this time, the first through hole 22 is not filled, and the PB layer having the above thickness is formed on the side wall surface and the bottom surface thereof.

Next, as shown in FIG. 2 (c), front surface etching is performed by the RIE method, and n + becomes the storage node in the upper surface of the SiO 2 insulating film 21 and the first through hole 22.
The surface of the mold region 9 is exposed. Where the first through hole
The lower end of the n + -type region 9 is located along the side wall of the n-type region 9.
The cylindrical PB layer contacting with remains. Then by thermal oxidation method
The thickness of the surface of the PB layer and the exposed surface of the n + type region 9, for example, 100 Å
A SiO 2 dielectric film 26 is formed to a degree.

The PB layer in the first through hole 22 becomes a cylindrical charge storage capacitor electrode 24, and the PB layer in the second through hole 23 is formed.
The layer becomes the drain electrode 25.

See FIG. 2 (d). Then, the inside of the cylindrical charge-storing capacitor electrode 24 is filled on the substrate by the CVD method, for example, the third capacitor of about 5000 Å.
Polycrystalline silicon layer PC is formed, and then the P layer is formed by the RIE method.
An opening 31 exposing the upper surface of the drain electrode 25 is formed in the C layer.

Here, the PC layer becomes the counter capacitor electrode 27.

Then, a PSG insulating film 28 having a thickness of about 1 μm is formed on the substrate by a CVD method, and a contact window 29 exposing the upper surface of the drain electrode 25 on the PSG insulating film 28 is formed by a usual method. And a bit line 30 in contact with the drain electrode 25 in the contact window 29 is formed on the insulating film 29 by a conventional method.

Then, a cover insulating film (not shown) is formed thereafter to complete the D-RAM cell according to the present invention.

As is clear from the description of the above embodiment, in the D-RAM cell according to the present invention, in principle, a cylindrical capacitor is formed as deep as possible so long as the conductive layer can grow to the bottom by the CVD method. It is possible. Therefore, the capacitance of the capacitor can be significantly increased as compared with the conventional one.

Further, since the cylindrical capacitor is provided in the insulating film,
The insulating film separates the cylindrical capacitors of adjacent cells from each other, and the leakage of information charges is completely prevented.

Furthermore, since the capacitor is provided in the insulating film, the charge generated in the silicon substrate due to the incidence of α rays does not reach the capacitor, and the α-ray soft error resistance is increased.

The capacitor electrode is not limited to the polycrystalline silicon shown in the above embodiment, but may be another conductive material such as molybdenum silicide.

〔The invention's effect〕

As described above, according to the present invention, one transistor
Since the capacitance of a dynamic random access memory (D-RAM) cell having a capacitor structure can be significantly increased, the leakage of information charges between adjacent capacitors can be eliminated, and the α-ray soft error resistance can be improved. The reliability is improved.

[Brief description of drawings]

FIG. 1 is a schematic plan view showing an embodiment of a D-RAM cell having a one-transistor / one-capacitor structure according to the present invention (a).
And schematic side sectional views (b), FIGS. 2 (a) to (e) are process sectional views showing the manufacturing method, FIG. 3 is a side sectional view of a stacked capacitor type D-RAM cell, and FIG. It is a sectional side view of a trench capacitor type cell. In the figure, 5a, 5b and 5c are gate electrodes (word lines) 8 is an n + type drain region, 9 is an n + type region to be a storage node, 21 is a silicon dioxide insulating film, 22 is a first through hole, 23 Is a second through hole, 24 is a charge storage capacitor electrode, 25 is a drain electrode, 26 is a dielectric film, 27 is a counter capacitor electrode, 28 is a phosphosilicate glass insulating film, 29 is a contact window, 30 is a bit line, Tr is a transfer transistor and C is a capacitor.

Claims (2)

[Claims]
1. A MIS transfer transistor formed on a semiconductor substrate of one conductivity type, an insulating film formed on the semiconductor substrate of one conductivity type to cover the transistor, and formed on the insulating film. An opening window that exposes an opposite conductivity type region serving as a storage node of a transistor, a side wall surface of the opening window, a lower end portion of which is electrically connected to the opposite conductivity type region, and a surface of the insulating film is formed. A cylindrical first capacitor electrode formed so as not to extend substantially, a dielectric film formed so as to cover the first capacitor electrode at least on the side wall surface of the opening window, and the dielectric And a second capacitor electrode formed on the film surface so as not to be electrically connected to the first capacitor electrode and extending to the insulating film surface. Storage device.
2. A step of forming an insulating film on the surface of the one conductivity type semiconductor substrate so as to cover the MIS transfer transistor formed on the one conductivity type semiconductor substrate, and then anisotropically etching the insulating film. And selectively forming an opening window that exposes the source or drain region of the opposite conductivity type of the transfer transistor, and then extending from the bottom surface and side wall surface of the opening window to the upper surface of the insulating film. A step of depositing and forming a first conductive film, and a step of anisotropically etching the first conductive film so as to remove it from the upper surface of the insulating film and leave at least the side wall surface of the opening window. A step of forming a dielectric film so as to cover the surface of the first conductive film, and a second step of electrically connecting the surface of the dielectric film to the first conductive film. The conductive film of Method of manufacturing a semiconductor memory device having a step.
JP60016934A 1985-01-31 1985-01-31 Semiconductor memory device and manufacturing method thereof Expired - Lifetime JPH0673368B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60016934A JPH0673368B2 (en) 1985-01-31 1985-01-31 Semiconductor memory device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60016934A JPH0673368B2 (en) 1985-01-31 1985-01-31 Semiconductor memory device and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JPS61176148A JPS61176148A (en) 1986-08-07
JPH0673368B2 true JPH0673368B2 (en) 1994-09-14

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP60016934A Expired - Lifetime JPH0673368B2 (en) 1985-01-31 1985-01-31 Semiconductor memory device and manufacturing method thereof

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Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2741857B2 (en) * 1987-05-11 1998-04-22 日立超エル・エス・アイ・エンジニアリング株式会社 Semiconductor storage device
JP2621181B2 (en) * 1987-06-12 1997-06-18 日本電気株式会社 MIS type semiconductor memory device
JP2613077B2 (en) * 1988-03-25 1997-05-21 富士通株式会社 Method for manufacturing semiconductor device
JP2723530B2 (en) * 1988-04-13 1998-03-09 日本電気株式会社 Method for manufacturing dynamic random access memory device
JPH0221652A (en) * 1988-07-08 1990-01-24 Mitsubishi Electric Corp Semiconductor storage device
JPH03116965A (en) * 1989-09-29 1991-05-17 Mitsubishi Electric Corp Memory cell structure
JP2996409B2 (en) * 1990-02-06 1999-12-27 三菱電機株式会社 Semiconductor device and manufacturing method thereof
JP3623834B2 (en) * 1995-01-31 2005-02-23 富士通株式会社 Semiconductor memory device and manufacturing method thereof
US6744091B1 (en) 1995-01-31 2004-06-01 Fujitsu Limited Semiconductor storage device with self-aligned opening and method for fabricating the same
JP3941133B2 (en) 1996-07-18 2007-07-04 富士通株式会社 Semiconductor device and manufacturing method thereof
JP2007189008A (en) * 2006-01-12 2007-07-26 Elpida Memory Inc Semiconductor memory device and method of fabricating same

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6155258B2 (en) * 1977-03-04 1986-11-27 Hitachi Ltd
JPS55154762A (en) * 1979-05-22 1980-12-02 Chiyou Lsi Gijutsu Kenkyu Kumiai Semiconductor memory

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Publication number Publication date
JPS61176148A (en) 1986-08-07

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