JPS6155258B2 - - Google Patents
Info
- Publication number
- JPS6155258B2 JPS6155258B2 JP52022685A JP2268577A JPS6155258B2 JP S6155258 B2 JPS6155258 B2 JP S6155258B2 JP 52022685 A JP52022685 A JP 52022685A JP 2268577 A JP2268577 A JP 2268577A JP S6155258 B2 JPS6155258 B2 JP S6155258B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- film
- polycrystalline silicon
- impurity doped
- conductivity type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000003990 capacitor Substances 0.000 claims description 13
- 239000004065 semiconductor Substances 0.000 claims description 11
- 239000012535 impurity Substances 0.000 claims description 7
- 238000002955 isolation Methods 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 5
- 230000005669 field effect Effects 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 20
- 239000010410 layer Substances 0.000 description 16
- 238000009792 diffusion process Methods 0.000 description 7
- 229910004298 SiO 2 Inorganic materials 0.000 description 6
- 238000000034 method Methods 0.000 description 4
- 230000010354 integration Effects 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 230000014759 maintenance of location Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 241000293849 Cordylanthus Species 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
Description
【発明の詳細な説明】
(1) 発明の利用分野
本発明は、半導体装置の高集積化に関するもの
で、特に情報蓄積用の容量の一部がスイツチング
トランジスタの上方に重なるように形成された半
導体記憶装置に関するものである。[Detailed Description of the Invention] (1) Field of Application of the Invention The present invention relates to high integration of semiconductor devices, and in particular, a semiconductor device in which a part of a capacitor for information storage is formed so as to overlap above a switching transistor. The present invention relates to semiconductor memory devices.
(2) 従来技術
第１図に平面図を、第２図にＹ方向断面図（メ
モリセル１ビツト分）を示す。従来知られている
１トランジスタ型MOSランダム・アクセス・メ
モリはスイツチングのためのMOSトランジスタ
１を情報を記憶するための容量２よりなるメモリ
セルをワード線（Al線）３とデータ線（拡散
層）４によつて選択するようになつている。第１
図、第２図において５は基板、６は素子間分離用
の絶縁膜、７はゲート酸化膜、８，１２は第１層
多結晶シリコン、９は層間絶縁膜、４，１０は拡
散層、１１は反転層、２２はコンタクト孔であ
る。(2) Prior Art FIG. 1 shows a plan view, and FIG. 2 shows a cross-sectional view in the Y direction (for one bit of memory cell). A conventionally known one-transistor type MOS random access memory has a memory cell consisting of a MOS transistor 1 for switching, a capacitor 2 for storing information, a word line (Al line) 3 and a data line (diffusion layer). The selection is made by 4. 1st
2, 5 is a substrate, 6 is an insulating film for isolation between elements, 7 is a gate oxide film, 8 and 12 are first layer polycrystalline silicon, 9 is an interlayer insulating film, 4 and 10 are diffusion layers, 11 is an inversion layer, and 22 is a contact hole.
図からわかるように、情報を蓄積するための容
量２はスイツチングトランジスタ１と互いに重な
らないように同一平面に２次元的に配置されてい
るために、メモリ・セルのセル面積が大きくな
る。 As can be seen from the figure, since the capacitor 2 for storing information is two-dimensionally arranged on the same plane as the switching transistor 1 so as not to overlap with each other, the cell area of the memory cell increases.
(3) 発明の目的
本発明は蓄積容量の少なくとも一部をスイツチ
ング・トランジスタの上方に重なるように設ける
ことによつて、メモリセル面積を少なくし、
MOSメモリの集積度を上げることを目的とす
る。(3) Purpose of the invention The present invention reduces the memory cell area by providing at least a portion of the storage capacitor so as to overlap above the switching transistor.
The purpose is to increase the degree of integration of MOS memory.
(4) 実施例
以下、本発明を実施例を参照して詳細に説明す
る。(4) Examples Hereinafter, the present invention will be explained in detail with reference to examples.
第３図および第４図に本発明による半導体記憶
装置の一例を平面図および断面図で示す（メモリ
セル２ビツト分）。図からわかるように、本発明
においては比抵抗15Ω．cm、結晶軸方向〈100〉
のＰ型シリコン基板５の一部に1.5μｍの厚さの
素子分離用酸化膜６，800Åの厚さのゲートSiO2
膜７、膜厚500Å、層抵抗15Ω／□の第１多結晶
シリコン・ゲート電極１２、接合深さ1.5μｍで
層抵抗10Ω／□のソースおよびドレイン領域１
０，１３、4000Åの厚さのSiO2膜１９を設けた
後、コンタクト孔１８を通して不純物添加領域
（拡散領域）１０に接するように膜厚5000Å、層
抵抗30Ω／□の第２多結晶シリコン電極１４を形
成する。更に絶縁膜１６および膜厚5000Å、層抵
抗15Ω／□の第３多結晶シリコン電極１５を形成
し、8000Åの厚さのりんガラス（P2O5濃度2mole
％）９を堆積した後、コンタクト孔１７を設け、
Al電極４１を形成する。なお、第３図および第
４図において、第２多結晶シリコン１４、絶縁膜
１６、第３多結晶シリコン１５は蓄積容量を構成
している。また、この場合、絶縁膜１６としては
SiO2膜以外にSi3N4膜、Ta2O5膜の如き誘電率の
大きな膜あるいはこれらを組み合わせた多層絶縁
膜を使用することにより大きな蓄積容量を得るこ
とができる。従つて、従来のメモリセルで用いら
れている蓄積容量と同一の値を得る場合、その面
積は少なくてすむ。たとえば、絶縁膜として800
ÅのSiO2膜、Si2N4膜、Ta2O5膜を用いた場合、
コンタクト孔寸法２μｍ、マスク合わせ余裕２μ
ｍ、多結晶シリコンゲート幅６μｍ、不純物添加
層（拡散層）幅６μｍ、蓄積容量2.22pFとする
と、１ビツトあたりのメモリセル面積は、それぞ
れ、725μm2，297μm2，192μm2となる。この面
積はそれぞれ同じ設計値を用いて製作した従来型
メモリのメモリセル面積925μm2の78％，32％，
21％である。 FIGS. 3 and 4 show a plan view and a sectional view of an example of a semiconductor memory device according to the present invention (for 2 bits of memory cells). As can be seen from the figure, in the present invention, the specific resistance is 15Ω. cm, crystal axis direction <100>
A device isolation oxide film 6 with a thickness of 1.5 μm is formed on a part of the P-type silicon substrate 5, and a gate SiO 2 with a thickness of 800 Å is formed.
Membrane 7, film thickness 500 Å, first polysilicon gate electrode 12 with layer resistance 15 Ω/□, source and drain regions 1 with junction depth 1.5 μm and layer resistance 10 Ω/□
After forming a SiO 2 film 19 with a thickness of 0, 13, or 4000 Å, a second polycrystalline silicon electrode with a thickness of 5000 Å and a layer resistance of 30 Ω/□ is placed in contact with the impurity doped region (diffusion region) 10 through the contact hole 18. form 14. Furthermore, an insulating film 16 and a third polycrystalline silicon electrode 15 with a film thickness of 5000 Å and a layer resistance of 15 Ω/□ are formed, and a phosphorous glass electrode 15 with a thickness of 8000 Å (P 2 O 5 concentration of 2 moles) is formed.
%) 9, a contact hole 17 is provided,
An Al electrode 41 is formed. Note that in FIGS. 3 and 4, the second polycrystalline silicon 14, the insulating film 16, and the third polycrystalline silicon 15 constitute a storage capacitor. Further, in this case, the insulating film 16 is
A large storage capacity can be obtained by using, in addition to the SiO 2 film, a film with a high dielectric constant such as a Si 3 N 4 film or a Ta 2 O 5 film, or a multilayer insulating film that is a combination of these films. Therefore, in order to obtain the same storage capacitance value as that used in conventional memory cells, the area required is smaller. For example, 800 as an insulating film.
When using SiO 2 film, Si 2 N 4 film, Ta 2 O 5 film of Å,
Contact hole size 2μm, mask alignment margin 2μm
Assuming that the polycrystalline silicon gate width is 6 μm, the impurity doped layer (diffusion layer) width is 6 μm, and the storage capacitance is 2.22 pF, the memory cell areas per 1 bit are 725 μm 2 , 297 μm 2 , and 192 μm 2 , respectively. These areas are 78%, 32%, and 32% of the memory cell area of 925 μm 2 of conventional memory fabricated using the same design values, respectively.
It is 21%.
本実施例で示したメモリセルへの情報の書き込
み、読み出しは次のように行う。すなわち、第３
多結晶シリコン電極１５を接地電位に固定した
後、第１多結晶シリコンより成るワード線３１に
正電圧を印加することによりスイツチングトラン
ジスタ１を導通させる。その後、Alより成るデ
ータ線４１に“０”または“１”に相当する電圧
を印加することにより、蓄積容量２に情報となる
電荷を蓄積する。情報の読み出しはスイツチング
トランジスタ１を導通させた後、データ線４１の
電位変化を検出することによつて行われる。本発
明のメモリセルにおいては、蓄積容量を形成する
のに反転層を用いていないため、それに基づくリ
ーク電流が流れない。従つて、記憶情報保持時間
が著く長くなるという利点がある。 Writing and reading information to and from the memory cell shown in this embodiment is performed as follows. That is, the third
After fixing polycrystalline silicon electrode 15 to the ground potential, switching transistor 1 is made conductive by applying a positive voltage to word line 31 made of first polycrystalline silicon. Thereafter, by applying a voltage corresponding to "0" or "1" to the data line 41 made of Al, charges serving as information are stored in the storage capacitor 2. Reading of information is performed by turning on the switching transistor 1 and then detecting a change in the potential of the data line 41. In the memory cell of the present invention, since an inversion layer is not used to form a storage capacitor, no leakage current flows due to the inversion layer. Therefore, there is an advantage that the storage information retention time becomes significantly longer.
第５図および第６図に本発明の他の実施例につ
いて平面図と断面図（メモリセル２ビツト分）を
示す。図からわかるように本実施例においては、
不純物添加領域（拡散領域）１０，１３と第２多
結晶シリコン電極１４およびAl電極４１を接触
させるためのコンタクト孔１８，１７を自己整合
で形成している。このような自己整合によるコン
タクト孔の形成は本発明者等が先に出願した特願
昭50−111622号明細書に詳しく示されている。 FIGS. 5 and 6 show a plan view and a cross-sectional view (for 2 bits of memory cells) of another embodiment of the present invention. As can be seen from the figure, in this example,
Contact holes 18 and 17 for bringing the impurity doped regions (diffusion regions) 10 and 13 into contact with the second polycrystalline silicon electrode 14 and Al electrode 41 are formed in a self-aligned manner. The formation of contact holes by such self-alignment is described in detail in Japanese Patent Application No. 111622/1982, previously filed by the present inventors.
自己整合コンタクト方式を採用することによ
り、本発明を用いる利点が更に顕著になる。たと
えば、絶縁膜１６として800ÅのSiO2膜、Si3N4
膜、Ta2O5膜を使用し、前述の設計値に基づいて
本実施例のメモリを製作するとメモリセル面積は
それぞれ675μm2，270μm2，176μm2となる。こ
の面積は、それぞれ、同じ設計値を用いて製作し
た従来型メモリのメモリセル面積925μm2の73
％，29％，19％である。 By employing a self-aligned contact method, the advantages of using the present invention become even more pronounced. For example, as the insulating film 16, an 800 Å SiO 2 film, Si 3 N 4
When the memory of this embodiment is manufactured using a Ta 2 O 5 film and a Ta 2 O 5 film based on the above-mentioned design values, the memory cell areas will be 675 μm 2 , 270 μm 2 , and 176 μm 2 , respectively. This area is 73% of the memory cell area of 925μm 2 of conventional memory fabricated using the same design values, respectively.
%, 29%, 19%.
第７図および第８図に本発明の他の実施例につ
いて平面図と断面図を示す（メモリセル２ビツト
分）。本実施例においては図に示すようにＸ方向
（データ線方向）の素子分離を800ÅのSiO2膜２
１上に形成した第１多結晶シリコン２０に負電圧
を印加すること（フイールド・シールドと記す）
により行つている。フイールド・シールド方法に
ついてはすでに公知の文献に詳しく述べられてい
る。自己整合コンタクトおよびフイールド・シー
ルド方法を採用することにより、本発明を用いる
利点が更に顕著になる。すなわち、局所酸化によ
つて素子分離用酸化膜を形成する場合に生じるよ
うな横方向酸化（バード・ビーク）によるコンタ
クト孔寸法の変化、および素子分離用酸化膜端部
での結晶欠陥などに基づくリーク電流が少なくな
り、自己整合コンタクト方式が容易になる。メモ
リセル面積に関しては第５図、第６図の場合とほ
ぼ同じである。なお、第３図から第８図におい
て、蓄積容量２を構成する第２多結晶シリコン１
４、絶縁膜１６、第３多結晶シリコン１５は自己
整合エツチングによりマスク合わせ余裕を必要と
せずに加工できる。 FIGS. 7 and 8 show a plan view and a sectional view of another embodiment of the present invention (for 2 bits of memory cells). In this example, as shown in the figure, element isolation in the X direction (data line direction) is performed using an 800 Å SiO 2 film 2.
Applying a negative voltage to the first polycrystalline silicon 20 formed on the first polycrystalline silicon 1 (referred to as field shield)
It is going by. Field shielding methods have already been described in detail in the known literature. By employing self-aligned contacts and field shielding methods, the advantages of using the present invention are even more pronounced. In other words, changes in contact hole dimensions due to lateral oxidation (bird's beak), which occur when forming an oxide film for element isolation by local oxidation, and crystal defects at the edges of the oxide film for element isolation, etc. Leakage current is reduced and self-aligned contact method is facilitated. Regarding the memory cell area, it is almost the same as in the cases of FIGS. 5 and 6. In addition, in FIGS. 3 to 8, the second polycrystalline silicon 1 constituting the storage capacitor 2
4. The insulating film 16 and the third polycrystalline silicon 15 can be processed by self-aligned etching without requiring a mask alignment margin.
(5) まとめ
以上説明したごとく本発明によれば、蓄積容量
の一部がスイツチング・トランジスタの上部に重
なるように設けるために、従来の半導体メモリに
くらべてメモリセル面積を著しく小さくでき、半
導体メモリの集積度を大幅に向上できる。本発明
による半導体記憶装置においては従来の１トラン
ジスタ型のMOSメモリのように、蓄積容量を形
成するために誘起した反転層に基づくリーク電流
が存在しないために、情報保持時間が著しく長く
なるという利点がある。(5) Summary As explained above, according to the present invention, since a part of the storage capacitor is provided so as to overlap with the top of the switching transistor, the memory cell area can be significantly reduced compared to conventional semiconductor memory, and semiconductor memory The degree of integration can be greatly improved. Unlike the conventional one-transistor type MOS memory, the semiconductor memory device according to the present invention has the advantage that the information retention time is significantly longer because there is no leakage current due to the inversion layer induced to form the storage capacitor. There is.
第１図は従来の１トランジスタ型MOSメモリ
セル１ビツトの平面図、第２図はその断面図、第
３図、第５図、第７図は本発明によるMOSメモ
リセル２ビツトの平面図、第４図、第６図、第８
図はその断面図である。
１：スイツチング・トランジスタ、２：蓄積容
量、３：ワード線（Al線）、４：データ線（拡散
層）、５：シリコン基板、６：素子間分離用酸化
膜、７：ゲート酸化膜、８：第１多結晶シリコン
電極、９：層間絶縁膜（りんガラス）、１０，１
３：拡散層、１１：反転層、１２：第１多結晶シ
リコン・ゲート電極、１４：第２多結晶シリコ
ン、１５：第３多結晶シリコン、１６：蓄積容量
形成用絶縁膜、１７，１８，２２：コンタクト
孔、１９：層間酸化膜、２０：フイールドシール
ド用第１多結晶シリコン、２１：フイールドシー
ルド用酸化膜、３１：ワード線（第１多結晶シリ
コン）、４１：データ線（Al線）。
FIG. 1 is a plan view of a conventional one-transistor type MOS memory cell with 1 bit, FIG. 2 is a cross-sectional view thereof, and FIGS. 3, 5, and 7 are plan views of a 2-bit MOS memory cell according to the present invention. Figure 4, Figure 6, Figure 8
The figure is a sectional view thereof. 1: Switching transistor, 2: Storage capacitor, 3: Word line (Al line), 4: Data line (diffusion layer), 5: Silicon substrate, 6: Oxide film for isolation between elements, 7: Gate oxide film, 8 : first polycrystalline silicon electrode, 9: interlayer insulating film (phosphorus glass), 10,1
3: Diffusion layer, 11: Inversion layer, 12: First polycrystalline silicon gate electrode, 14: Second polycrystalline silicon, 15: Third polycrystalline silicon, 16: Insulating film for forming storage capacitor, 17, 18, 22: Contact hole, 19: Interlayer oxide film, 20: First polycrystalline silicon for field shield, 21: Oxide film for field shield, 31: Word line (first polycrystalline silicon), 41: Data line (Al line) .
Claims (1)
用の厚い絶縁膜で区分された表面領域に、所望の
間隔をもつて形成された第２導電形を有する複数
の不純物添加領域および所望の該不純物添加領域
間の上記半導体基板上に第１の絶縁膜を介して形
成された第１の導電膜からなるゲート電極をそな
えた絶縁ゲート電界効果トランジスタと、上記ゲ
ート電極の上部と側部に形成された第２の絶縁膜
と、上記ゲート電極上の上記第２の絶縁膜上から
上記不純物添加領域の表面を経て上記厚い絶縁膜
上へ延びる第２の導電膜および該第２の導電膜上
に積層して形成された第３の絶縁膜と第３の導電
膜から構成された記憶容量と、隣接する二つのメ
モリセル間に形成された上記不純物添加領域に電
気的に接続され、上記二つのメモリセルの有する
上記第３の導電膜上に形成された第４の絶縁膜上
に延びる第４の導電膜を少なくともそなえ上記第
２の導電膜は上記ゲート電極の側部に形成された
上記第２の絶縁膜と上記厚い絶縁膜によつて規定
される開口部を介して上記不純物添加領域と電気
的に接続されていることを特徴とする半導体装
置。1. A plurality of impurity doped regions having a second conductivity type formed at desired intervals in a surface region of a semiconductor substrate having a first conductivity type divided by a thick insulating film for element isolation and a desired conductivity type. an insulated gate field effect transistor including a gate electrode made of a first conductive film formed on the semiconductor substrate between the impurity doped regions via a first insulating film; a second insulating film extending from above the second insulating film on the gate electrode to the thick insulating film through the surface of the impurity doped region; A storage capacitor composed of a third insulating film and a third conductive film formed in a laminated manner is electrically connected to the impurity doped region formed between two adjacent memory cells, and the second at least a fourth conductive film extending over a fourth insulating film formed on the third conductive film of the two memory cells; A semiconductor device, wherein the semiconductor device is electrically connected to the impurity-doped region through an opening defined by a second insulating film and the thick insulating film.
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2268577A JPS53108392A (en) | 1977-03-04 | 1977-03-04 | Semiconductor device |
| NLAANVRAGE7707297,A NL176415C (en) | 1976-07-05 | 1977-06-30 | SEMI-CONDUCTOR MEMORY DEVICE CONTAINING A MATRIX OF SEMI-CONDUCTOR MEMORY CELLS CONSISTING OF A FIELD-EFFECT TRANSISTOR AND A STORAGE CAPACITY. |
| GB27724/77A GB1572674A (en) | 1976-07-05 | 1977-07-01 | Semiconductor memory devices |
| DE19772730202 DE2730202A1 (en) | 1976-07-05 | 1977-07-04 | SEMICONDUCTOR STORAGE |
| US05/812,907 US4151607A (en) | 1976-07-05 | 1977-07-05 | Semiconductor memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2268577A JPS53108392A (en) | 1977-03-04 | 1977-03-04 | Semiconductor device |
Related Child Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60093607A Division JPS6110272A (en) | 1985-05-02 | 1985-05-02 | Semiconductor device |
| JP60093606A Division JPS6110271A (en) | 1985-05-02 | 1985-05-02 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS53108392A JPS53108392A (en) | 1978-09-21 |
| JPS6155258B2 true JPS6155258B2 (en) | 1986-11-27 |
Family
ID=12089712
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2268577A Granted JPS53108392A (en) | 1976-07-05 | 1977-03-04 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS53108392A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62198560U (en) * | 1986-06-09 | 1987-12-17 |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58209156A (en) * | 1982-05-31 | 1983-12-06 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor device and its manufacture |
| JPS58215067A (en) * | 1982-06-08 | 1983-12-14 | Nec Corp | Semiconductor integrated circuit device |
| JPS602784B2 (en) * | 1982-12-20 | 1985-01-23 | 富士通株式会社 | semiconductor storage device |
| US5244825A (en) * | 1983-02-23 | 1993-09-14 | Texas Instruments Incorporated | DRAM process with improved poly-to-poly capacitor |
| US5359216A (en) * | 1983-02-23 | 1994-10-25 | Texas Instruments Incorporated | DRAM process with improved polysilicon-to-polysilicon capacitor and the capacitor |
| JPH0618257B2 (en) * | 1984-04-28 | 1994-03-09 | 富士通株式会社 | Method of manufacturing semiconductor memory device |
| JPH0673368B2 (en) * | 1985-01-31 | 1994-09-14 | 富士通株式会社 | Semiconductor memory device and manufacturing method thereof |
| US5098192A (en) * | 1986-04-30 | 1992-03-24 | Texas Instruments Incorporated | DRAM with improved poly-to-poly capacitor |
| JPH02312269A (en) * | 1989-05-26 | 1990-12-27 | Toshiba Corp | Semiconductor memory device and manufacture thereof |
| JPH0496270A (en) * | 1990-08-03 | 1992-03-27 | Sharp Corp | Manufacture of semiconductor device |
| JP3421230B2 (en) * | 1997-11-04 | 2003-06-30 | 株式会社日立製作所 | Semiconductor storage device and method of manufacturing the same |
-
1977
- 1977-03-04 JP JP2268577A patent/JPS53108392A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62198560U (en) * | 1986-06-09 | 1987-12-17 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS53108392A (en) | 1978-09-21 |
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