JP3177038B2 - Semiconductor memory device and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a dynamic semiconductor memory device (DRA) using a memory cell block (NAND memory cell block) having a plurality of MOS transistors connected in series.
M).

[0002]

2. Description of the Related Art In recent years, remarkable progress has been made in the integration of DRAM, which is a kind of RAM in LSI memories. DR
A new memory cell block called a NAND type memory cell block has been proposed in order to further increase the integration of AM.

FIG. 15 shows an equivalent circuit of this NAND type memory cell block. In this memory cell block, a plurality of MOS transistors are connected in series, a capacitor is connected to each common source / drain of these MOS transistors, and word lines WL1, WL2, W
L3 and WL4 are connected to the gates of the respective MOS transistors, and the bit line BL is connected to the drain of the MOS transistor at the end of the memory cell block.

According to the memory cell block configured as described above, the number of contacts between the bit line BL and the MOS transistor is reduced as compared with the conventional memory cell block, so that the area of the entire memory cell is reduced. Can be integrated.

[0005] A DRAM cell actually using such a NAND type memory cell block is a stack type D cell.
RAM cells are known. One of this kind of DRAM cell
The minimum memory cell area per bit is 4F ^{2 where} F is the design rule (minimum dimension width). Was the limit.

In the case of a stacked DRAM cell,
In order to obtain a large capacitor capacity, the capacitor electrode needs to be formed high. For this reason, when an upper wiring is formed by depositing a wiring material such as Al in a region of the DRAM cell, the step of the underlying layer becomes 1 μm or more, and it is difficult to form the upper wiring.

[0007]

As described above, the conventional N
Stack type DR using AND type memory cell block
In the AM cell, when the design rule (minimum dimension width) is F, the memory cell area is 4F ² There was a problem that it could not be smaller.

In the case of a stacked DRAM cell,
In order to increase the capacitance of the capacitor, it is necessary to form the capacitor electrode high, so that it is difficult to form the upper wiring.

SUMMARY OF THE INVENTION The present invention has been made in consideration of the above circumstances. It is an object of the present invention to provide a semiconductor memory device capable of realizing higher integration and easily forming an upper layer wiring, and a method of manufacturing the same. To provide.

[0010]

In order to achieve the above object, a semiconductor memory device according to the present invention is provided in a memory cell region of a semiconductor substrate and includes a plurality of serially connected MOS transistors. And a trench-type capacitor connected to each common source / drain of the plurality of MOS transistors and having a capacitor insulating film inserted between the storage electrode and the plate electrode connected to the common source / drain. In a semiconductor memory device having a dynamic memory cell, at least a part of the plate electrode is made of the semiconductor substrate.

Here, at least a part of the plate electrode means, for example, a lower part of the plate electrode. That is, the plate electrode is divided into a portion made of a semiconductor substrate and other portions.

According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor memory device, comprising: a plurality of serially connected MOS transistors provided in a memory cell region of a semiconductor substrate; A dynamic memory cell including a trench capacitor connected to each drain, a word line connected to each gate of the plurality of MOS transistors, and the plurality of MOS transistors
In the method of manufacturing a semiconductor memory device having a bit line connected to the drain of one of the MOS transistors on the most end, the word line, the bit line, the trench pattern of the capacitor, and the dynamic memory cell Forming a first word line, a first bit line, a first trench pattern, and a first element isolation insulating film whose pitch interval is twice the minimum processing size. Forming a film, wherein the pitch interval is twice the minimum processing size, and wherein the first first word line, the first bit line, the first trench pattern, and the first isolation for element isolation are formed. Forming a second word line, a second bit line, a second trench pattern, and a second isolation insulating film, each of which is displaced from the film by a minimum processing dimension. And wherein the Rukoto.

[0013]

According to the semiconductor memory device of the present invention, since the semiconductor substrate itself is used as at least a part of the plate electrode in the NAND type memory cell, the plate electrode structure can be simplified and the cell area can be further reduced.

Further, according to the method of manufacturing a semiconductor device of the present invention, a main portion (word line, bit line, trench pattern, insulating film for element isolation) can be formed by 2F with a processing size twice the minimum processing size. Since it is formed twice in the pitch, one main part can be formed in the F pitch instead of forming one main part in the 2F pitch. As a result, the cell area is changed to F ² (Conventionally, 4
F ² Is the limit. ), And higher integration can be achieved.

[0015]

Embodiments will be described below with reference to the drawings.

FIG. 1 shows a NAND according to an embodiment of the present invention.
2 (a), 2 (b), and 2 (c) are cross-sectional views of the DRAM cell array of FIG. 1 taken along the lines AA 'and BB', respectively. CC '
It is sectional drawing.

In this embodiment, a case where a NAND cell block is formed by four memory cells of one transistor / one capacitor will be described. However, the number of memory cells may be other than four.

In the figure, 1 is n ⁺ Type silicon substrate, and this n ⁺ On the type silicon substrate 1, an n-type epitaxial layer 2 and a p-type well layer 14 are sequentially formed. An element isolation insulating film 13 for partitioning the memory cells is formed in the p-type well 14 in the memory cell region.

A capacitor insulating film 7 is formed on the inner wall of the capacitor trench 6, and a storage electrode 8 is buried in the trench 6 via the capacitor insulating film 7. This storage electrode 8 is connected to an n-type common source / drain region 16 via an n-type impurity diffusion layer 12. On the other hand, the plate electrode, which is another electrode constituting the capacitor, is connected to the n-type epitaxial layer 2 and n ⁺ The mold silicon substrate 1 plays the role. Therefore, a special structure for the plate electrode is not required, and the cell area can be reduced.

The element isolation insulating film 13 is orthogonal to the word lines WL _{1 to} WL ₄ (also serving as a gate electrode), and a cell block adjacent in the bit line direction is a field shield line FS ( (A gate electrode is also used.) Also,
The word lines WL _{1 to} WL ₄ are orthogonal to the bit line BL, and the bit line BL is connected to the n-type drain region 1 of the MOS transistor at the end of the cell block via the bit line contact 17.
6 '. Next, a method of manufacturing a DRAM having the above basic structure will be described.

First, as shown in FIG.
N ⁺ on which the n-type epitaxial layer 2 is formed First, a stacked insulating film including a thin silicon oxide film 3, a nitride film 4, and an oxide film 5 is formed on an n-type epitaxial layer 2 as a trench forming mask.

Next, as shown in FIG. 3B, the mask laminated insulating films 3, 4, and 5 for forming trenches are processed using photolithography and etching techniques, and the n-type epitaxial layer , N ⁺ The mold silicon substrate 1 is etched to form a deep trench 6.

Next, as shown in FIG.
Is formed on the inner wall of the capacitor. As the capacitor insulating film 7, for example, a silicon oxide film, a stacked film of a nitride film and an oxide film, or a ferroelectric film such as Ta ₂ O ₅ or HfO ₂ is used. Next, a conductive material such as polycrystalline silicon which becomes the storage electrode 8 is deposited on the entire surface to such a thickness that the trench is completely filled, and then the conductive material is processed by reactive ion etching, polishing or the like to form the storage electrode 8. To form Here, the storage electrode 8 is formed by doping or ion implantation during the deposition of the storage electrode 8 so as to include an n-type impurity. Next, an oxide film 9 is formed on the surface of the storage electrode 8 and capping is performed. This oxide film 9 is, for example,
It is formed by thermal oxidation or the like.

Next, after removing the silicon oxide film 3, the nitride film 4 and the oxide film 5 (at this time, the oxide film 9 becomes a thin oxide film 9).
′), And epitaxial growth of silicon is performed as shown in FIG. This epitaxial growth
Since the upper portion of the storage electrode 8 is covered with the thin oxide film 9 ', lateral growth proceeds preferentially. As a result, a storage node opening 11 is automatically formed on each trench capacitor. Next, after the oxide film 9 'in the storage node opening 11 is removed by wet etching or the like, epitaxial growth is subsequently performed, and as shown in FIG.
Impurity diffusion layer 12 is formed in storage node opening 11. As a result, an epitaxial layer 10 'having a flat surface is obtained. Next, as shown in FIG. 4B, after forming an isolation insulating film 13, a p-type well 14 in a memory cell portion is formed.
To form

Next, as shown in FIG.
After simultaneously forming L _{1 to} WL ₄ and the field shield line FS with polycrystalline silicon, high melting point metal, silicide or the like, the n-type common source / drain region 16 and the n-type drain at the end of the cell block are formed by ion implantation or the like. Area 1
6 'is formed. Finally, the data line contact 17 and the bit line 18 are formed by using reactive ion etching or the like. Further, when there is an upper layer wiring, the upper layer wiring and the interlayer insulating film are processed to obtain a desired DRAM.

As described above, according to the DRAM of this embodiment, the silicon substrate 1 is used as the lower part of the plate electrode.
Since the device itself is used, a special structure for the plate electrode is not required, and the cell area can be reduced. The ratio of the silicon substrate 1 to the plate electrode may be increased or decreased as needed.

FIG. 5 shows a NAN according to another embodiment of the present invention.
FIG. 6A is a plan view of a D-type DRAM cell array,
FIGS. 6B, 7A, and 7B are cross-sectional views of the DRAM cell array of FIG. 5 taken along the lines AA ', BB', CC ', and D-, respectively. It is D sectional drawing. 1 to 4 are denoted by the same reference numerals as those in FIGS. 1 to 4, and detailed description thereof will be omitted.

The DRAM of this embodiment is different from that of the previous embodiment in that an element isolation insulating film, data lines, bit lines,
Each layer of the data line contact is divided into two and formed within the pitch of the design rule (F).

That is, the gate electrodes 15, 15 ', the bit lines BL1, BL2, and the data line contacts 17, 17'.
Are formed two times at a pitch of 2F. For this reason, each layer is substantially composed of two layers. In addition, the insulating films 13 for element isolation, 13
', Trenches 6 and 6' are also formed in two steps. With such a formation method, the cell area of one bit is reduced to the conventional 4F ² To F ² It can be reduced to near. Next, a specific method for forming each layer will be described. FIG. 8 is a plan view showing a step of forming a trench.

First, as shown in FIG. 8A, a resist pattern for forming a trench 6 having a pitch of 2F and one side of F is formed using ordinary photolithography and etching techniques. The trench laminated masking insulating film is processed.

Next, as shown in FIG.
Then, a resist pattern for forming a trench 6 'whose one side is shifted by F is formed, and the underlying trench-forming mask laminated insulating film is processed.

Finally, the silicon substrate is etched using the mask pattern for forming a trench as a mask to form trenches 6 and 6 '. As a result, trenches 6, 6 'having an F pitch are obtained. FIG. 9 is a plan view showing a step of forming an isolation insulating film. First, as shown in FIG. 9A, a groove for element isolation having a pitch of 2F is formed.
An insulating film for element isolation 13 '(first insulating film for element isolation) is formed.

Next, as shown in FIG. 9B, a mask pattern which is shifted from the mask pattern of the groove 13 for element isolation by F is formed, and using this as a mask, the base is etched to form a groove for element isolation. I do.

Finally, when an insulating film is buried in the trench to form an element isolating insulating film 13 '(second element isolating insulating film), the element isolating insulating films 13, 1 having a pitch of F are formed.
3 'is formed. FIG. 10 is a plan view showing a step of forming word lines and field shield lines. First, as shown in FIG. 10A, the word lines WL are arranged at a pitch of 2F.
₁ ', WL _1, WL ₃ (first word line), to form a field shield line FS.

Next, as shown in FIG. 10B, after a conductive film serving as a word line or the like is deposited on the entire surface via an insulating film,
A mask pattern is formed which is shifted from the mask pattern of the word lines WL ₁ ′, WL ₁ , WL ₃ and the field shield FS by F, and the conductive film is etched using the mask pattern as a mask.
WL ₂ to form a _{', WL 2, WL 4,} WL 4'.

As a result, the word lines WL having a pitch interval of F
₂ ′, WL ₂ , WL ₄ , WL ₄ ′ (second word lines) are formed, and word lines having a pitch interval of F as a whole are formed.

FIGS. 11 and 12 are plan views showing steps of forming data line contacts and bit lines, respectively. The method of forming these layers is the same as that of other rays,
What is necessary is just to form the thing of a pitch twice. FIG.
FIG. 9 is a process chart showing another trench formation method.

First, as shown in FIGS. 13A and 13B, a thick silicon nitride film 20 is formed on a thin silicon oxide film 3 as a trench mask material. Next, a silicon oxide film 21 is formed on the silicon nitride film 20 by CVD.
Then, a photoresist pattern 19 (first trench pattern) is formed on the silicon oxide film 21 using an edge-based phase shift mask method or the like. Next, using the photoresist pattern 19 as a mask, the silicon oxide film 20 is etched by reactive ion etching to transfer the photoresist pattern to the silicon oxide film 20. Next, as shown in FIGS. 13C and 13D, after removing the photoresist pattern 19, a photoresist pattern 19 '(second trench pattern) shifted vertically and horizontally by F is formed on the silicon oxide film 20. Form. Then, using the photoresist pattern 19 'and the silicon oxide film 21 as a mask, the silicon nitride film 20 is formed.
Is etched to form an F pitch trench mask pattern.

The silicon oxide film 3, the n-type epitaxial layer 2 and the silicon substrate 1 are formed using the trench mask pattern formed of the silicon nitride film 20 as a mask.
By etching (not shown), a trench having an opening whose one side is close to F can be formed.

The processes other than the above-mentioned layers are the same as those of the previous embodiment. However, if necessary, the layers other than the above-mentioned layers may be formed twice at F pitch intervals. By such a manufacturing method, the cell area is F ² Is obtained. FIG. 14 shows four cell areas (F ² , 2F
^Two , 4F ² , 8F ² FIG. 14 is a diagram showing the relationship between the degree of integration and the design rule in the case of FIG.

From FIG. 14, the cell area is 2F ² in the case of,
With the design rule of 0.35 μm, the degree of integration is 1 Gbit and the cell area is F ² In the case of (1), the integration degree is 1 Gbit even with a design rule of 0.5 μm. And if the cell area is F ² In the case of, the degree of integration is dramatically increased to 16 Gbits with a design rule of 0.25 μm.

For this reason, the cell area is F ² By using the method of this embodiment, which can be reduced to near, a highly integrated D
The RAM can be easily realized. In the present embodiment, a case has been described in which the layer is formed twice at a pitch interval of 2F, but the pitch interval may be larger than 2F if the cell area is smaller than before.

The present invention is not limited to the above embodiment. For example, in the above embodiment, polycrystalline silicon is mainly used as the conductive material, but silicide, metal, or a stacked film of these may be used. In addition, the conductivity type of the substrate, the well, and the like may be the opposite conductivity type. Also, the layout patterns shown in FIGS. 8 to 13 can be variously modified. Further, the present invention can be applied to a case where the capacitor has an STC structure or the like. In addition, various modifications can be made without departing from the scope of the present invention.

[0044]

As described in detail above, in the semiconductor memory device of the present invention, the structure of the capacitor is simplified because the semiconductor substrate itself is used as at least a part of the plate electrode. As a result, the size of the capacitor can be reduced, and the degree of integration can be increased.

In the method of manufacturing a semiconductor memory device according to the present invention, the same layer is formed twice at a pitch of 2F. As a result, one data line or the like can be formed in the F pitch, and the degree of integration can be increased.

[Brief description of the drawings]

FIG. 1 is a plan view of a DRAM according to an embodiment of the present invention.

FIG. 2 is a sectional view of the DRAM of FIG. 1;

FIG. 3 is a process sectional view showing the first half of the manufacturing process of the DRAM according to one embodiment of the present invention;

FIG. 4 is a process sectional view showing a latter half of a manufacturing process of the DRAM according to one embodiment of the present invention;

FIG. 5 is a plan view of a DRAM according to another embodiment of the present invention.

FIG. 6 is a sectional view of the DRAM of FIG. 5;

FIG. 7 is a sectional view of the DRAM of FIG. 5;

FIG. 8 is a process plan view showing a method of forming a trench pattern.

FIG. 9 is a process plan view showing a method for forming an insulating film pattern for element isolation.

FIG. 10 is a process plan view showing a method for forming a word line pattern.

FIG. 11 is a process plan view showing a method for forming a data line contact pattern.

FIG. 12 is a process plan view showing a method of forming a bit line pattern.

FIG. 13 is a process plan view showing another method for forming a trench pattern.

FIG. 14 is a diagram showing the dependence of the degree of integration on the design rule and the cell area.

FIG. 15 is a diagram showing an equivalent circuit of a NAND memory cell block.

[Explanation of symbols]

1: Silicon substrate (plate electrode), 2, 10, 10 '
... Epitaxial layer, 3,5,21 ... Silicon oxide film,
4, 20, 20 '... silicon nitride film, 6, 6' ... trench, 7 ... capacitor insulating film, 8 ... storage electrode, 9, 9 '...
Oxide film, 11: Opening of storage node, 16: Common source
Drain region, 16 ': drain region at the end of the cell block, 13, 13': insulating film for element isolation, 14: p-type well, 17, 17 ': data line contact, 19: photoresist pattern (first trench) Pattern), 19 '
... Photoresist pattern (second trench pattern), WL _{1 to} WL ₄ ... Word line (gate electrode), B
L, BL1, BL2 ... bit lines, FS ... field shield electrodes.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-4-3463 (JP, A) JP-A-3-227563 (JP, A) JP-A-60-136366 (JP, A) JP-A-62-267 276869 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) H01L 21/8242 H01L 21/822 H01L 27/04 H01L 27/108

Claims (7)

(57) [Claims] A semiconductor substrate provided in a memory cell region;
A plurality of MOS transistors connected in series,
In a semiconductor memory device having a dynamic memory cell including a trench capacitor formed between a storage electrode and a plate electrode connected to each common source / drain region of an OS transistor via a capacitor insulating film, The storage electrode is selected under the common source / drain region
A semiconductor memory device, wherein at least a part of the plate electrode is formed of the semiconductor substrate. 2. A single crystal semiconductor layer is formed on the semiconductor substrate.
And the common source / drain region is
The storage electrode is formed on the surface of the body layer, and the storage electrode is
The plate electrode formed in the body layer and the semiconductor substrate;
The pole is composed of the single crystal semiconductor layer and the semiconductor substrate
The semiconductor memory device according to claim 1, wherein: 3. A semiconductor device comprising : a memory cell area provided on a semiconductor substrate;
A plurality of MOS transistors connected in series and these
Number of MOS transistors for each common source / drain
Dynamit consisting of a connected trench capacitor
And click type memory cell, which is connected to each gate of the plurality of MOS transistors
A plurality of gate lines formed of word lines and one of the plurality of MOS transistors,
A bit line connected to the drain of the MOS transistor;
In the semiconductor memory device having a plurality of word lines to the first word line and the second word line
Are alternately arranged, and these first and second
The cross-sectional shape of the plane perpendicular to the longitudinal direction of the word line is different from each other.
A semiconductor memory device characterized by the following. 4. The cross section of the first word line has a rectangular shape.
Shape, wherein the cross-sectional shape is the upper corner of the rectangle of the second word line
Wherein the portion has a shape projecting upward.
Item 4. The semiconductor memory device according to item 3. 5. A memory comprising a plurality of dynamic memory cells.
Memory cell array, wherein the dynamic type
A memory cell is provided in a memory cell area of a semiconductor substrate.
And a plurality of MOS transistors connected in series,
Source / drain of multiple MOS transistors
Consisting of trench-type capacitors connected to each other
A cell array connected to each gate of the plurality of MOS transistors;
A word line and each of the plurality of dynamic memory cells are connected in series.
Of the plurality of MOS transistors on the one end side
From the bit line connected to the drain of the S transistor
A plurality of bit lines , wherein the plurality of bit lines are a first bit line and a second bit line.
Are alternately arranged, and these first and second
The cross-sectional shape of the plane perpendicular to the longitudinal direction of the bit line
A semiconductor memory device characterized by the following. 6. The cross section of the first word line is rectangular.
And the cross-sectional shape of the second word line is a rectangular upper corner.
Wherein the portion has a shape projecting upward.
Item 4. The semiconductor memory device according to item 3. 7. A semiconductor device provided in a memory cell region of a semiconductor substrate,
A dynamic memory cell comprising a plurality of MOS transistors connected in series, and a trench capacitor connected to each common source / drain of the plurality of MOS transistors; and a dynamic memory cell connected to each gate of the plurality of MOS transistors. A method of manufacturing a semiconductor memory device, comprising: a word line connected to a drain of a MOS transistor on the one end of the plurality of MOS transistors; and the word line, the bit line, and the capacitor. Forming a first word line, a first bit line, and a first trench having a pitch interval twice as large as a minimum processing dimension. Forming a pattern and a first element isolation insulating film; A second processing dimension which is twice as large as the processing dimension and which is deviated from the first first word line, the first bit line, the first trench pattern, and the first element isolation insulating film by a minimum processing dimension. Word line, second bit line,
Forming a second trench pattern and a second element isolation insulating film.