JPH04340270A - Semiconductor memory and manufacture thereof - Google Patents

Abstract

PURPOSE:To make the title memory suitable for a high integration by providing a stacked capacity including the following: a lower-layer electrode on which a definite undulation has been formed on its side face; a capacity insulating film which is formed on the lower-layer electrode and whose thickness is nearly definite; and an upper-layer electrode formed on the capacity insulating film. CONSTITUTION:A definite undulation is formed on the side face of a lower-layer electrode 6 for a stacked capacity in a 1T1C memory cell. Thereby, the surface area of the lower-layer electrode is increased and a storage capacity is increased. A capacity insulating film 7 is formed in such a way that its thickness is nearly uniform it is formed along the surface of the lowerlayer electrode. A silicon oxide film 2 is formed in an element isolation region on p-type single- crystal silicon 1; an n-type source-drain region 3 is formed. After that, a silicon oxide film is deposited as a first insulating film 4 and a silicon oxide film is deposited as a second insulating film 5 on the whole surface. After that, phosphorus-doped silicon oxide films as third insulating films and undoped oxide films as fourth insulating films are deposited alternately. The lowerlayer electrode 6 is formed in a self-aligned manner with a contact hole and is favorable for the high integration of the title memory.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory and a method of manufacturing the same, and more particularly to a shape of a lower electrode of a stacked capacitor and a method of forming the same.

0002

2. Description of the Related Art Semiconductor memories that store binary information in the form of charges have a small cell area, so they are highly integrated, have a large capacity, and are excellent as memory cells. In particular, a memory cell (hereinafter referred to as ``1'') consisting of one transistor and one capacitor is used as a memory cell.
The T1C cell (abbreviated as T1C cell) is important as a highly integrated memory cell because it has a small number of components and a small cell area. By the way, as the memory cell size is reduced due to higher integration of memories, the area of the capacitor part in the 1T1C cell structure is reduced. A decrease in the amount of storage charge due to a decrease in the area of the capacitor section causes problems with respect to alpha particles and deterioration of the sensitivity of the sense amplifier.

Conventionally, in order to solve this problem, a method has been known in which a large storage capacity section is formed despite the reduction in memory cell area. For example, the 1988 International Solid State Devices Meeting (International Electron Devices Meeting)
Electron Devices Meetin
g)), pp. 596-599, ``A New Stacked Capacitor DRAM Cell Characterized by a Storage Capacitor on a Bit Line Structure (A New
Stacked Capacitor DRA
M Cell Characterized by
aStorage Capacitor On
a Bit-line Structure)
In the paper published under the title, as shown in FIG. 6, a 1T1C cell capacitor section is formed on a bit line to maximize the planar area of the capacitor section. Figure 6
6 is the lower layer electrode (charge storage electrode), 7 is the capacitive insulating film,
Reference numeral 8 indicates an upper layer electrode (counter electrode), 14 indicates a bit line, and 15 indicates a word line.

0004

[Problems to be Solved by the Invention] However, as the memory cell area decreases, there is a limit to increasing the surface area of the lower electrode in such a conventional structure, and in order to increase the surface area, it is necessary to increase the film thickness of the lower electrode. It has to be thick. An increase in the thickness of the lower electrode results in an increase in surface steps. This increase in surface level difference is a major problem when transferring pattern shapes using lithography technology.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate such problems and provide a lower electrode structure in a stacked capacitor structure of a semiconductor memory suitable for high integration, and a method for manufacturing the same.

[0006]

[Means for Solving the Problems] A semiconductor memory of the present invention includes a lower layer electrode having a certain undulation on its side surface, a capacitive insulating film having a substantially constant thickness provided on the lower layer electrode, and a capacitive insulating film provided on the lower layer electrode with a substantially constant thickness. It is equipped with a laminated capacitor including an upper layer electrode provided on the film.

[0007] Furthermore, the method for manufacturing a semiconductor memory of the present invention includes:
Depositing a first insulating film to a fourth insulating film on a semiconductor chip, and penetrating the first to fourth insulating film to reach an underlying conductive region using a non-selective etching method. a step of forming a contact hole; a step of selectively etching the third insulating film to provide undulations on the side surface of the contact hole; a step of filling the contact hole with a conductor; The method includes a step of removing the insulating film and the fourth insulating film to form a lower layer electrode of a laminated capacitor having a certain undulation on the side surface.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Examples of the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic cross-sectional view showing one embodiment of the present invention.

In this embodiment, by providing a certain undulation on the side surface of the lower electrode 6 of the laminated capacitor of the 1T1C memory cell, the surface area of the lower electrode can be increased and the storage capacitance can be increased. 1 is a silicon substrate, 2 is an element isolation oxide film, 3 is a high concentration n-type diffusion layer, 4 is a first insulating film (silicon oxide film), 5 is a second insulating film (silicon nitride film),
6 is a lower layer electrode having a certain undulation; 7 is a capacitive insulating film;
8 indicates a counter electrode (upper layer electrode).

The capacitor insulating film 7 has a substantially uniform thickness and is provided along the undulations of the surface of the lower electrode.

FIGS. 2 to 5 are cross-sectional views shown in order of steps for explaining the semiconductor memory manufacturing method of the present invention.

First, as shown in FIG. 2, a silicon oxide film 2 is provided in an element isolation region on p-type single crystal silicon 1.
After providing the n-type source/drain regions 3, a silicon oxide film is deposited as the first insulating film 4, a silicon nitride film is deposited as the second insulating film 5, and then a phosphorus-doped silicon oxide film is deposited as the third insulating film. 9-1, 9-2, 9-3 and 4th
Non-doped oxide films 10-1, 10-2,
10-3 are alternately deposited to a thickness of 10 to 100 nm.

Next, as shown in FIG. 3, a resist film 1 is formed that covers the entire surface except for a portion above the n-type source/drain region 3.
1 is formed, the fourth insulating film or the first insulating film and the silicon oxide film 2 are etched away using the resist film 11 as an etching mask using a reactive sputter etching technique to open a contact hole 12.

Next, as shown in FIG. 4, the resist film 11 is
After removing the contact, the inside of the contact is etched using dilute hydrofluoric acid, and a conductor 13 such as phosphorus-doped polysilicon is buried inside the contact. When the inside of the contact hole is etched using dilute hydrofluoric acid, the phosphorus-doped silicon oxide film 9-
1, 9-2, 9-3 and non-doped silicon oxide film 10-
Since the etching rates of 1, 10-2, and 10-3 are different, unevenness is formed on the side wall inside the contact hole. The size of the waviness of the sidewall in the contact can be controlled by the ratio of the phosphorus-doped silicon oxide film thickness to the non-doped silicon oxide film thickness and the etching time with dilute hydrofluoric acid. For example, in the case of a phosphorus-doped silicon oxide film containing 4 to 5 mol% of phosphorus, by using 0.5% of dilute hydrofluoric acid,
It is possible to form irregularities of about 0 to 100 nm.

Next, as shown in FIG. 4, the conductor 13 is etched back using a reactive sputter etching technique, leaving only the conductor 13a in the contact hole, and then phosphorus doped with the silicon nitride film (5) as an etching mask. The silicon oxide films 9-1 to 9-3 and the non-doped silicon oxide films 10-1 to 10-3 are removed by etching.

Next, as shown in FIG. 1, thermal oxidation or CV
A capacitor insulating film 7 made of silicon oxide or the like and an upper layer wiring 8 (counter electrode) are formed by method D to form a laminated capacitor section. The thickness of the capacitor insulating film 7 is 4 to 6 nm in terms of silicon oxide film.
Make it.

As is clear from the above description, the lower electrode is formed in self-alignment with the contact hole, which is advantageous for high integration.

[0019]

[Effects of the Invention] According to the present invention, by providing a certain undulation on the side surface of the lower electrode, it is possible to secure a large surface area of the lower electrode, and it is possible to easily obtain a large storage capacity even in a fine lower electrode. Can be done. Therefore, it has the effect of contributing to higher integration of semiconductor memories.

[0020]

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view showing a stacked capacitance of a semiconductor memory cell according to an embodiment of the present invention.

[0021]

FIG. 2 is a cross-sectional view for explaining a manufacturing method according to an embodiment of the present invention.

[0022]

FIG. 3 is a cross-sectional view for explaining a manufacturing method according to an embodiment of the present invention.

[0023]

FIG. 4 is a cross-sectional view for explaining a manufacturing method according to an embodiment of the present invention.

[0024]

FIG. 5 is a cross-sectional view for explaining a manufacturing method according to an embodiment of the present invention.

[0025]

FIG. 6 is a cross-sectional view showing a stacked capacitance of a conventional semiconductor memory cell.

[0026]

[Explanation of symbols]

1 P-type silicon substrate 2 Silicon oxide film 3 N-type source/drain region 4 Silicon oxide film (first insulating film) 5
Silicon nitride film (second insulating film) 6 Lower electrode 7 Capacitive insulating film 8 Upper electrode 9-1, 9-2, 9-3 Phosphorus-doped silicon oxide film (third insulating film) 10-1, 10-2, 10-3 Non-doped silicon oxide film (fourth insulating film) 11 Resist film 12 Contact holes 13, 13a Conductor 14 Bit line 15 Word line 16, 17 Silicon oxide film

Claims (2)

[Claims] 1. A lower layer electrode having a certain undulation on a side surface, a capacitive insulating film with a substantially constant thickness provided on the lower layer electrode, and an upper layer electrode provided on the capacitive insulating film. A semiconductor memory characterized by having a stacked capacitor. 2. A step of depositing a first insulating film to a fourth insulating film on a semiconductor chip, and a non-selective etching method to penetrate the first insulating film to the fourth insulating film to remove the lower layer. a step of forming a contact hole reaching a conductive region of the third insulating film, a step of selectively etching the third insulating film to form undulations on a side surface of the contact hole, and a step of filling the contact hole with a conductor. . A method of manufacturing a semiconductor memory, comprising the steps of: removing the third insulating film and the fourth insulating film to form a lower electrode of a laminated capacitor having a certain undulation on the side surface.