JP3082691B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

The present invention relates to a semiconductor device and a method for manufacturing the same.

[0001]

2. Description of the Related Art In recent years, the cell size has been reduced in accordance with the high integration of DRAMs (Dynamic Read Only Memory). A dimensional cell structure has been introduced. Considering a simple type stack, a 256 Mb DRAM has a minimum design dimension of 0.25 [μm] and a cell size of about 0.6 [μm ² ]. In order to obtain a storage capacity of about 25 [fF] using an insulating film, a stack height of about 1.4 [μm] is simply required. However, if the stack is too high, it will be difficult to perform processing in a subsequent step, so the stack height must be kept low. For this reason, several methods have been proposed for increasing the storage capacity by increasing the surface area. As one of the methods, an amorphous silicon film is heated in a vacuum to form a polysilicide to form hemispherical grains (fine irregularities) on the film surface to increase the surface area (HSG technology). No. 4,127,519. When this HSG technology is used, the surface area becomes 2
Stack height is 0.7 [μm]
The processing in the post-process is facilitated.

FIGS. 10 (a) to 10 (e) show H according to the prior art.
This is a method for manufacturing an SG stacked capacitor. FIG.
In (a) to (e), 1 is a silicon substrate, 2 is a diffusion layer region, 3 is an element isolation oxide film, 4 is a gate insulating film, 5 is a gate electrode, 6 is an interlayer insulating film, and 7 is a contact hole. Reference numeral 8 denotes a contact hole, 10 denotes a doped amorphous silicon film, 11 denotes a stack resist for patterning a stack electrode, and 12 denotes a polysilicon film obtained by crystallizing the doped amorphous silicon film by HSG processing. As described above, the above-mentioned fine irregularities are formed on the surface of the polysilicon film 12 after the HSG processing.

According to the above-mentioned manufacturing method, the phosphorus concentration is 0.5 ×
Using a doped amorphous silicon film of 10 ²⁰ [atom / cm ³ ], an HSG-formed stacked capacitor and a simple stacked capacitor are formed and C (capacity) −
FIG. 11 shows the result of the V (voltage) characteristic evaluation. It is apparent from this figure that the HSG stack has a smaller storage capacity at the same impurity concentration. From this, it can be said that it is necessary to increase the phosphorus concentration in the doped amorphous silicon film. Therefore, at present 0.6 × 1
A film having a phosphorus concentration of about 0 ^{20 to} 3.0 × 10 ²⁰ [atom / cm ³ ] is used.

[0004]

However, the HSG
The conversion treatment is a low-temperature heat treatment at about 550 ° C., which reduces the solid solubility of phosphorus in the amorphous silicon film,
Phosphorus segregates at the interface between the polysilicon film obtained by crystallizing the amorphous silicon film, the interlayer insulating film, and the silicon substrate. Then, phosphorus segregated at the interface with the silicon substrate is diffused into the substrate by heat treatment in a later step. As a result, the diffusion layer region is widened, and the cell isolation characteristics deteriorate. This problem becomes more prominent as semiconductor devices become more highly integrated. FIG. 12 shows a comparison between the production of a DRAM having an HSG capacitor and the non-defective rate of the DRAM with and without HSG processing. From this figure, H
It can be seen that when SG conversion is performed, the non-defective product rate is greatly reduced. FIG. 13 shows the static hold characteristics of the DRAM. From this figure, it can be said that the deterioration of the non-defective rate is caused by the deterioration of the static hold characteristic. In other words, when the HSG processing is performed, impurities seep into the silicon substrate to deteriorate the isolation characteristics of the cells, thereby deteriorating the static hold characteristics and causing a reduction in the yield of DRAM.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device which suppresses deterioration of cell hold characteristics due to HSG processing, thereby suppressing a decrease in non-defective product rate, and improves the yield, and a method of manufacturing the same. It is.

[0006]

According to the present invention, an interlayer insulating film formed on a silicon substrate and a contact hole formed in the interlayer insulating film and reaching a conductive layer provided on the silicon substrate are provided. Doping impurities along the inner wall of the contact hole so as not to fill the contact hole.
A polysilicon film formed without being etched, and an impurity concentration formed on the polysilicon film being 6 × 10 ^{19 to} 3 × 10
^{It has a} polysilicon film obtained by crystallizing an amorphous silicon film in a range of ²⁰ [atom / cm ³ ], and fine irregularities formed on the surface of the polysilicon film obtained by crystallizing the amorphous silicon film. A semiconductor device is obtained. Preferably, a semiconductor device is obtained in which the impurity concentration in the polysilicon film is lower than the impurity concentration in a polysilicon film obtained by crystallizing the amorphous silicon film.

Further, according to the present invention, an interlayer insulating film formed on a silicon substrate, a contact hole formed in the interlayer insulating film and reaching a conductive layer provided on the silicon substrate, A formed polysilicon plug, and a polysilicon film formed by crystallizing an amorphous silicon film having an impurity concentration in the range of 6 × 10 ^{19 to} 3 × 10 ²⁰ [atom / cm ³ ] formed on the polysilicon plug; Fine irregularities formed on the surface of the polysilicon film obtained by crystallizing the amorphous silicon film, and the polysilicon plug is configured such that the impurities in the polysilicon film obtained by crystallizing the amorphous silicon film are thermally diffused. A semiconductor device characterized in that the semiconductor device is prevented from reaching the silicon substrate is obtained. More preferably, a semiconductor device is obtained in which the impurity concentration in the polysilicon plug is lower than the impurity concentration in a polysilicon film obtained by crystallizing the amorphous silicon film.

Further, according to the present invention, a step of forming an interlayer insulating film on a silicon substrate, a step of forming a contact hole reaching the conductive layer provided on the silicon substrate in the interlayer insulating film, Along the inner wall of the contact hole,
Forming a polysilicon film to a thickness that does not completely fill the contact holes; and forming an amorphous silicon film having an impurity concentration in the range of 6 × 10 ^{19 to} 3 × 10 ²⁰ [atom / cm ³ ] on the polysilicon film. And forming a fine uneven portion on the surface of the amorphous silicon film crystallized, wherein the impurity in the polysilicon film obtained by crystallizing the amorphous silicon film is thermally diffused. As a result, a method for manufacturing a semiconductor device having an impurity concentration low enough to prevent the impurity from reaching the silicon substrate is obtained.

Further, according to the present invention, a step of forming an interlayer insulating film on a surface of a semiconductor substrate having a conductive layer, and a step of forming a contact hole reaching the surface of the conductive layer at a predetermined position of the interlayer insulating film. Forming a polysilicon film only in the contact hole; and forming an impurity concentration of 6 × 10 ^{19 to} 3 on the surface of the interlayer insulating film and the surface of the polysilicon film.
A step of forming an amorphous silicon film in the range of × 10 ²⁰ [atom / cm ³ ], a step of patterning the amorphous silicon film, and a step of forming fine irregularities on the surface of the patterned amorphous silicon film. Wherein the polysilicon film has an impurity concentration low enough to prevent the impurities in the polysilicon film obtained by crystallizing the amorphous silicon film from reaching the silicon substrate by thermal diffusion. Is obtained.

According to the invention, a step of forming a first interlayer insulating film on a surface of a semiconductor substrate having a conductive layer, and a step of forming an amorphous silicon layer doped with impurities on the first interlayer insulating film Forming a second interlayer insulating film on the amorphous silicon layer; and contacting the first interlayer insulating film, the amorphous silicon layer, and the second interlayer insulating film with the conductive layer surface. Forming a hole, forming an amorphous silicon film in the contact hole that does not add impurities to a thickness that does not completely fill the contact hole, crystallizing the amorphous silicon film, and forming a surface of the amorphous silicon layer. Forming a fine uneven portion on the surface of the amorphous silicon film; and forming an amorphous portion without adding the crystallized impurity. And introducing a predetermined impurity into the facsimile silicon film.

[0011]

According to the present invention, even if impurities (for example, phosphorus) in a crystallized polysilicon film are exuded by performing a low-temperature heat treatment at the time of HSG formation, the crystallized polysilicon film and the silicon substrate are in contact with each other. Since the polysilicon film is present between the two, the exuded impurities (eg, phosphorus) do not reach the interface with the silicon substrate, and do not largely diffuse into the silicon substrate even if heat treatment is performed thereafter.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION

1 (a) to 1 (e) are sectional views in the order of steps for explaining a first embodiment of the present invention. First, FIG.
As shown in FIG. 1, an element isolation oxide film 3, a gate insulating film 4, a gate electrode 5, a diffusion layer region 2, and an interlayer insulating film 6 are formed on a silicon substrate 1. Here, in a COB (capacitor over bit line) structure, a bit line exists on a gate electrode via an interlayer insulating film, but is not shown in the drawing. Next, as shown in FIG. 1B, the contact hole 8 reaching the diffusion layer region 2 is opened by using a photolithography technique and a contact resist 7 for opening the contact hole 8. I do. Next, as shown in FIG. 1C, the polysilicon film 9 and the doped amorphous silicon film 1 are formed.
0 is formed. At this time, impurities may be introduced into the polysilicon film 9 to some extent. The impurity concentration of phosphorus in the doped amorphous silicon film 10 is, for example, 1 × 10
^{About 20} [atom / cm ³ ] is introduced. Next, FIG.
As shown in (d), the polysilicon film 9 and the doped amorphous silicon film 10 are patterned by using a photolithography technique and a stack resist 11 for patterning a stack electrode. Then, as shown in FIG. 1E, the doped amorphous silicon film 10 is polysilicided by performing an HSG process. As a result, fine irregularities are formed on the surface of the doped polysilicon film 12 after the HSG processing. As a method of the HSG processing, as described in the related art (Japanese Patent Laid-Open No. 4-127519), the doped amorphous silicon film 10 may be heat-treated at 550 to 900 ° C. in a vacuum. Thereafter, a capacitor insulating film and a counter electrode are sequentially formed to obtain a capacitor structure. In the present embodiment, the example in which the simple stack type capacitor is converted to the HSG is shown. However, it is possible to similarly form the cylinder type stack and the fin type stack. And FIG.
(G) respectively. It can also be formed with a multi-cylinder structure and a multi-fin structure.

FIGS. 3 (a) to 3 (e) and FIGS. 4 (f) and 4 (g) are step-by-step sectional views for explaining a second embodiment of the present invention. First, as shown in FIG. 3A, an element isolation oxide film 3, a gate insulating film 4, a gate electrode 5, a diffusion layer region 2, and an interlayer insulating film 6 are formed on a silicon substrate 1. Here, in a COB (capacitor over bit line) structure, a bit line exists on a gate electrode via an interlayer insulating film, but is not shown in the drawing. Next, as shown in FIG. 3B, a contact hole 8 reaching the diffusion layer region 2 is opened by using a contact resist 7 for opening the contact hole 8 by using a photolithography technique. I do. Next, as shown in FIG. 3C, a polysilicon film 9 is formed so that the contact holes 8 are completely buried. Here, a certain amount of impurities may be introduced into the polysilicon film 9. Next, as shown in FIG. 3D, the entire surface is etched back so that the polysilicon film 9 remains only in the contact hole 8. At this time, the remaining polysilicon film 9
A polysilicon plug 13 is formed. This etch back may be either dry etching or wet etching, or may be performed using a CMP method. Next, a doped amorphous silicon film 10 is formed as shown in FIG. Next, as shown in FIG. 4F, the doped amorphous silicon film 10 is patterned by using a photolithography technique and a stack resist 11 for patterning a stack electrode.
Then, as shown in FIG. 4G, an HSG process is performed to crystallize the doped amorphous silicon film to form a polysilicon film. As a result, fine irregularities are formed on the surface of the doped polysilicon film 12 after the HSG processing.
Thereafter, a capacitor insulating film and a counter electrode are sequentially formed to obtain a capacitor structure. In the present embodiment, the example in which the simple stack type capacitor is converted into the HSG is shown.

5 (a) to 5 (d) and 6 (e) to 5 (e).
FIG. 6H is a step-by-step cross-sectional view for explaining the third embodiment of the present invention. First, as shown in FIG. 5A, an element isolation oxide film 3, a gate insulating film 4, a gate electrode 5, a diffusion layer region 2, and an interlayer insulating film 6 are formed on a silicon substrate 1.
Here, in a COB (capacitor over bit line) structure, a bit line exists on a gate electrode via an interlayer insulating film, but is not shown in the drawing. Next, as shown in FIG. 5B, a nitride film (silicon nitride film) 14 for a stopper, a doped amorphous silicon film 10, and an oxide film (silicon oxide film) 15 for a spacer are sequentially formed. Next, as shown in FIG. 5C, an oxide film 15, a doped amorphous silicon film 10, a nitride film 14, and a contact resist 7 for forming a contact hole 8 are formed by photolithography. Then, a contact hole 8 penetrating through the interlayer insulating film 6 and reaching the diffusion layer 2 is formed. Next, as shown in FIG. 5D, for example, a non-doped amorphous silicon film 16 is formed on the entire surface. Next, FIG.
As shown in (e), the non-doped amorphous silicon film 16, the oxide film 15, and the doped amorphous silicon film 10 are patterned using the stack resist 11 by using the photolithography technique. Next, the oxide film 15 is removed as shown in FIG. Next, FIG.
The nitride film 14 is removed as shown in FIG. And FIG.
As shown in (h), the doped amorphous silicon film 10 and the non-doped amorphous silicon film 16 are polysilicided by performing an HSG process. This allows
Fine irregularities are formed on the surface of the doped polysilicon film 12 and the surface of the non-doped polysilicon film 18 after the HSG processing. Thereafter, phosphorus is implanted into the non-doped polysilicon film 18 using, for example, an ion implantation method, and a capacitor insulating film and a counter electrode are sequentially formed to obtain a capacitor structure.

FIGS. 7A to 7E are cross-sectional views in the order of steps for explaining a fourth embodiment of the present invention. First, FIG.
As shown in FIG. 1A, an element isolation oxide film 3, a gate insulating film 4, a gate electrode 5, a diffusion layer region 2, a pad polysilicon film 17 serving as a lead electrode of the diffusion layer region 2, and an interlayer insulating film on a silicon substrate 1. 6 is formed. Here, in the COB (capacitor over bit line) structure, a bit line exists on the pad polysilicon film 17 via the interlayer insulating film, but is not shown in the drawing. Further, impurities such as phosphorus may be introduced into the pad polysilicon film 17 to some extent. Next, as shown in FIG. 7B, a contact hole 8 is formed using a contact resist 7 by using a photolithography technique. Next, as shown in FIG. 7C, a doped amorphous silicon film 10 is formed on the entire surface. Next, FIG.
As shown in (d), the doped amorphous silicon film 10 is patterned using the stack resist 11 by using the photolithography technique. Then, as shown in FIG. 7E, the doped amorphous silicon film 10 is polysilicided by performing an HSG process. As a result, fine irregularities are formed on the surface of the doped polysilicon film 12 after the HSG processing. Thereafter, a capacitor insulating film and a counter electrode are sequentially formed to obtain a capacitor structure. In this embodiment, the example in which the simple stack type capacitor is converted to the HSG has been described.
A fin-type stack and a cylinder-type stack can be formed in a similar manner.

As an HSG conversion method, for example, as described in JP-A-5-304273, after forming an amorphous silicon film, SiH ₄ or SiH ₄ is formed.
A method of forming a crystal nucleus on the amorphous silicon film by flowing a silane-based gas such as ₂ H ₆ and then heating to 450 to 650 ° C. to form HSG may be used. Alternatively, a crystallized polysilicon film having HSG on the surface may be formed by an LP-CVD method at 550 to 600 ° C. and used.

[0018]

According to the present invention, even if impurities (for example, phosphorus) in an amorphous silicon film exude due to low-temperature heat treatment at the time of HSG formation, a polysilicon film is formed between the amorphous silicon film and the silicon substrate. Exists, the exuded impurities (eg, phosphorus) do not reach the interface with the silicon substrate, and do not significantly diffuse into the silicon substrate even if heat treatment is performed thereafter. As a result, the hold characteristic is greatly improved without deteriorating the isolation characteristic in the cell. Here, FIG. 8 is a graph showing a difference in static hold characteristics of a DRAM having an HSG stacked capacitor according to a difference between the present invention and the conventional technique. Since the hold characteristic has a great influence on the yield rate of chips, the yield is also improved. Here, H due to the difference between the present invention and the prior art
FIG. 9 shows the non-defective product rate of the DRAM having the SG stacked capacitor.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view in a process order for explaining a first embodiment of the present invention.

FIG. 2 is a cross-sectional view for explaining a modification of the first embodiment.

FIG. 3 is a process order sectional view for explaining a second embodiment of the present invention.

FIG. 4 is a process order sectional view for explaining the second embodiment.

FIG. 5 is a sectional view in order of process for explaining a third embodiment of the present invention.

FIG. 6 is a process order sectional view for explaining the third embodiment.

FIG. 7 is a process order sectional view for explaining a fourth embodiment of the present invention.

FIG. 8 is a graph showing a difference between static hold characteristics of a DRAM having an HSG type stacked capacitor according to the present invention and the prior art.

FIG. 9 is a graph showing a difference in a non-defective rate of a DRAM having an HSG type stacked capacitor according to the present invention and the prior art.

FIG. 10 is a process order sectional view for describing a manufacturing method according to a conventional technique.

FIG. 11 is a graph showing a difference in capacitance CV characteristics between a simple stacked capacitor and an HSG type stacked capacitor.

FIG. 12 is a graph showing a difference between non-defective products of a DRAM having a simple stacked capacitor and a conventional HSG type stacked capacitor.

FIG. 13 is a graph showing a difference between static hold characteristics of a DRAM having a simple stacked capacitor and a conventional HSG type stacked capacitor.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Diffusion layer area 3 Element isolation oxide film 4 Gate insulating film 5 Gate electrode 6 Interlayer insulating film 7 Contact resist 8 Contact hole 9 Polysilicon film 10 Doped amorphous silicon film 11 Stack resist 12 Doped after HSG processing Amorphous silicon film 13 Polysilicon plug 14 Nitride film 15 Oxide film 16 Non-doped amorphous silicon film 17 Pat polysilicon film

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-6-5805 (JP, A) JP-A-5-67730 (JP, A) JP-A-5-315543 (JP, A) JP-A-5-315543 129548 (JP, A) JP-A-5-343636 (JP, A) JP-A-6-224388 (JP, A) JP-A-6-188365 (JP, A) JP-A-6-104400 (JP, A) JP-A-5-21751 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 27/108 H01L 21/822 H01L 21/8242 H01L 27/04

Claims (9)

(57) [Claims] An interlayer insulating film formed on a silicon substrate; a contact hole formed in the interlayer insulating film and reaching a conductive layer provided on the silicon substrate; and a contact hole formed along an inner wall of the contact hole. Shape that does not fill up
A polysilicon film formed without being doped with an impurity, and an impurity concentration formed on the polysilicon film being 6
A polysilicon film obtained by crystallizing an amorphous silicon film in the range of × 10 ^{19 to} 3 × 10 ²⁰ [atom / cm ³ ]; and fine irregularities formed on the surface of the polysilicon film obtained by crystallizing the amorphous silicon film. To have
Characteristic semiconductor device. 2. The semiconductor device according to claim 1, wherein said impurity is phosphorus or arsenic. 3. The semiconductor device according to claim 1, wherein an impurity concentration in said polysilicon film is lower than said impurity concentration in a polysilicon film obtained by crystallizing said amorphous silicon film. 4. A step of forming an interlayer insulating film on a silicon substrate, a step of forming a contact hole reaching a conductive layer provided in the silicon substrate in the interlayer insulating film, and forming a contact hole along an inner wall of the contact hole. Forming a polysilicon film to a thickness not filling the contact holes,
An impurity concentration of 6 × 10 ^{19 to} 3 is formed on the polysilicon film.
A step of forming an amorphous silicon film in a range of × 10 ²⁰ [atom / cm ³ ], and a step of forming fine irregularities on a surface of the amorphous silicon film crystallized, wherein the polysilicon film is A method of manufacturing a semiconductor device, wherein the impurity concentration in a polysilicon film obtained by crystallizing an amorphous silicon film has a low impurity concentration that prevents the impurity from reaching the silicon substrate by thermal diffusion. 5. The semiconductor device according to claim 4, wherein the step of forming the concave and convex portions is a step of forming the fine concave and convex portions on the surface by polysilicizing the amorphous silicon film by performing a heat treatment. Production method. 6. A step of forming an interlayer insulating film on a surface of a semiconductor substrate having a conductive layer, a step of forming a contact hole reaching a surface of the conductive layer at a predetermined position of the interlayer insulating film, Forming a polysilicon film only on the surface of the substrate, and forming an impurity concentration on the surface of the interlayer insulating film and the surface of the polysilicon film of 6 × 10 ^{19 to} 3 × 10 ²⁰ [at
om / cm ³ ], a step of patterning the amorphous silicon film, and a step of forming fine irregularities on the patterned amorphous silicon film surface,
The method of manufacturing a semiconductor device, wherein the polysilicon film has an impurity concentration low enough to prevent the impurities in the polysilicon film obtained by crystallizing the amorphous silicon film from reaching the silicon substrate by thermal diffusion. Method. 7. The method according to claim 4, wherein the impurity contained in the amorphous silicon film is phosphorus or arsenic. 8. A step of forming a first interlayer insulating film on a surface of a semiconductor substrate having a conductive layer; a step of forming an amorphous silicon layer doped with impurities on the first interlayer insulating film; Forming a second interlayer insulating film on a silicon layer, forming a contact hole reaching the conductive layer surface in the first interlayer insulating film, the amorphous silicon layer, and the second interlayer insulating film; Forming an amorphous silicon film in which no impurities are added to a thickness that does not completely fill the contact hole in the contact hole, and crystallizing the amorphous silicon film, and forming a film on the surface of the amorphous silicon layer and the surface of the amorphous silicon film. A step of forming fine irregularities, and a step of forming a crystallized amorphous silicon film to which the impurity is not added. The method of manufacturing a semiconductor device which comprises a step of introducing an impurity. 9. The method according to claim 8, wherein the predetermined impurity is phosphorus or arsenic.