JP2969876B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

The present invention relates to a semiconductor device and a method for manufacturing the same.

[Conventional technology]

2. Description of the Related Art With the advance of high integration of semiconductor devices, multilayer wiring has been developed. A typical example of a highly integrated semiconductor device is a dynamic semiconductor memory.

A semiconductor memory cell (hereinafter, referred to as a 1T cell) including one transistor and one capacitor is widely used in highly integrated semiconductor memories because it has few components and can be easily miniaturized. In this 1T cell, the output voltage is proportional to the capacitance of a capacitor (hereinafter referred to as a cell capacitor). Therefore, in order to highly integrate the 1T cell and keep its output voltage at a sufficiently large value, the cell capacitor needs to have a small area and a large capacity.

Conventionally, as one of such cell capacitors, a 1T using a so-called multilayer capacitor stacked on a transistor is used.
Cells (referred to as stacked cells) have been proposed. In a multilayer capacitor, the side surfaces of the electrodes to be stacked can be used as capacitor electrodes. Therefore, by increasing the thickness, the area of the capacitor electrodes can be increased. Therefore, the stacked cell can be made large in cell capacitor without increasing its occupied area, and is suitable for a highly integrated semiconductor memory.

However, in the conventional stacked cell, when the thickness of the stacked electrode is increased, it is difficult to make an electrical connection to an electrode formed below the electrode. Usually, in order to make such a connection, a hole (contact hole) is formed from the upper part to the lower part of the laminated electrode, and the hole is filled with a conductor. However, as the memory cell becomes smaller and the laminated electrode becomes thicker, the contact hole becomes thinner and deeper, and it becomes difficult to embed the conductor.

In general, in a semiconductor device having a multilayer wiring structure, when the thickness of an interlayer insulating film between an upper wiring and a lower wiring becomes large, it is difficult to make contact between the two.

As a method of overcoming the above-described difficulty of the electrical connection, a stacked cell having a structure for eliminating such connection has been proposed. For example, a paper published by T. Ema et al. At the 1988 International Electron Devices Meeting (International Electron Devices Meeting),
"3 Dimensional Stacked Capacitor Cell for 16 Mega and 64 Mega Dillams" (3
−dimensional stacked capacitor cell for 16M and 6
This is the stacked cell proposed in 4M DRAMs) (Preliminary Meeting, p. 592). In this stacked cell, a word line and a bit line which need to electrically connect to an electrode formed below the stacked electrode are formed below the stacked electrode. Therefore, the above-mentioned thin and deep contact hole is not required.

[Problems to be solved by the invention]

However, in the multilayer cell proposed by Emma et al., It was necessary to design the contact hole for making an electrical connection between the electrode of the multilayer capacitor and the electrode of the transistor so that the bit line would not cross. Therefore, the bit line, the above-mentioned contact hole, and the contact hole for establishing an electrical connection between the bit line and the electrode of the transistor have to be well arranged. In this arrangement, it is necessary to consider the separation between adjacent memory cells arranged in a matrix. In the stacked cell proposed by Emma et al., The memory cell area had to be increased to enable these arrangements.

Further, in this laminated cell, it is necessary to form a laminated capacitor after forming a word line and a bit line. However, after two wirings are formed, the surface irregularities are severe,
It was difficult to make it flat, and as a result, it was difficult to process the multilayer capacitor electrode.

In general, in a semiconductor device having a multilayer wiring structure, the surface of a base on which an upper wiring is to be provided has a rough surface, and step coverage is deteriorated.

An object of the present invention is to alleviate the above-mentioned problems by providing one of the wirings in a semiconductor crystal substrate.

Another object of the present invention is to provide a structure of a stacked cell in which a word line and a bit are formed under a stacked capacitor, the bit line and the contact hole can be arranged in a small area with little waste, and the unevenness of a base for forming the stacked capacitor is small. And to provide a manufacturing method by which the structure can be easily obtained.

[Means for solving the problem]

A semiconductor device according to the present invention includes an element region, a word line intersecting the element region, a bit line intersecting the word line and connected to the element region in a first region of the element region, A capacitor connected to the element region in a second region of the element region, wherein the element region includes a first groove provided inward from one main surface of the semiconductor crystal substrate. The bit line is surrounded by an element isolation region filled with an insulator, and the bit line is formed by providing a second groove having a width and a depth smaller than that of the first groove in the element isolation region and filling the bit line with a conductor. It is a feature.

Further, the method of manufacturing a semiconductor device according to the present invention includes an element region,
A word line that intersects the element region, a bit line that intersects the word line and is connected to the element region in a first region of the element region, and a bit line that intersects the element region in a second region of the element region. A capacitor connected to the region;
Forming the element region so as to be surrounded by an element isolation region in which a first groove provided inward from one main surface of the semiconductor crystal substrate is filled with an insulator. Connecting the element region and the bit line by forming a second groove in which the bit line is smaller in width and depth than the first groove in the element isolation region and filling it with a conductor; And forming a wiring to be formed.

〔Example〕

 Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1A is a plan view showing the structure of a laminated cell according to one embodiment of the present invention, and FIGS. 1B and 1C are cross-sectional views taken along line AA of FIG. 1A, respectively. It is BB sectional drawing.

1 is a p-type silicon crystal substrate, 2 is a first element isolation region.
3 is an insulator buried in the first groove of the element isolation region where the bit line is arranged. 4 is a low-resistance polysilicon buried in the insulator 3 in the second groove having a smaller width and depth than the first groove, 5 is a gate insulating film of the MOS transistor, 6 is a gate electrode of the MOS transistor and a word line. Low resistance polysilicon that doubles as a line, 7 is MOS
N-type silicon regions forming source / drain regions of transistors, 8 and 10 are interlayer insulating films for insulating between conductive layers,
9a and 9b are n-type, low-resistance polysilicon used for wiring, 1
1 is an n-type, low-resistance polysilicon for a capacitor electrode, 1
Reference numeral 11 denotes a formation region, 12 denotes a capacitor insulating film, 13 denotes a conductor serving as the other electrode of the capacitor, 14 denotes a boundary between an element region and an element isolation region, and 15a and 15b denote contact holes. In the plan view of FIG. 1 (a), some lines are omitted in order to avoid obfuscation.

In the stacked cell of FIG. 1, a switching MOS transistor is formed by low-resistance polysilicon 6 and source / drain regions 7 formed on both sides thereof. This MOS
One source / drain region of the transistor is connected to the bit line 4 through low-resistance polysilicon 9b, and the other source / drain region is formed of 11, 12, and 13 through low-resistance polysilicon 9 and connected to the multilayer capacitor. You. Since the low-resistance polysilicon 6 also serves as a word line,
This structure constitutes a 1T cell.

2 (a) to 2 (d) are process diagrams for explaining a method of manufacturing a semiconductor memory cell according to an embodiment of the method of manufacturing a semiconductor device of the present invention. It is a figure for explaining the first half of a manufacturing process. As shown in FIG. 2 (a), p
After a first groove is formed from one main surface of the type silicon crystal substrate 1 toward the inside, a silicon oxide film 31 is deposited and formed by a CVD method so as to fill the first groove. Next, as shown in FIG. 2B, after the silicon oxide film 31 is polished by mechanical chemical polishing to flatten the surface, the silicon nitride film 30 is removed and thermal oxidation is performed. At this time, the insulator 3 is buried in the first groove, and the silicon oxide film 16 is formed on the silicon surface. Silicon nitride film
The substrate 30 is not polished because 30 serves as a stopper during polishing. Next, as shown in FIG. 2C, a second groove having a width and a depth smaller than that of the first groove is formed by etching the insulator 32 at a portion where the bit line is to be arranged. A low-resistance polysilicon 41 is adhered and formed so as to be filled. Next, as shown in FIG. 2 (d), the polishing rate of the polysilicon is higher than that of the insulator 3 or the silicon oxide film 16 by selective polishing, and the surface is flattened. Thereafter, the silicon oxide film 16
Is removed, and various insulating films, word lines, low-resistance polysilicon wirings 9a and 9b, multilayer capacitors, and the like are formed by a normal manufacturing method, whereby the structure shown in FIG. 1 is obtained.

In the case of the embodiment of the present invention shown in FIG. 1, low-resistance polysilicon 9b is connected between the bit line 4 and the source / drain region 7.
Use Therefore, there is no need to provide a margin for separating the adjacent bit line at the connection portion between the two, and the area of the memory cell can be reduced. Further, in the case of this embodiment,
The bit line is buried in the first groove of the element isolation region, and its surface has high flatness as can be seen from the manufacturing method. Therefore, the unevenness of the substrate surface when forming the multilayer capacitor can be easily reduced, and the processing of the multilayer capacitor electrode can be facilitated.

If the polysilicon 11 of the capacitor electrode is replaced with the upper wiring in a general semiconductor device, the description of the above embodiment can be applied to the general semiconductor device almost as it is.

(Effect of the Invention) As described above, according to the present invention, by embedding one of the wiring layers in the element isolation region, the contact between the wiring layer and the active region (source / drain region of the transistor, etc.) can be easily made. Steps peculiar to the multilayer wiring structure can be reduced, and the step coverage of the upper wiring can be improved.
In particular, when the present invention is applied to a semiconductor memory cell, bit lines and contact holes can be arranged in a small area with little waste,
In addition, it is possible to obtain a laminated cell structure in which word lines and bit lines are formed below the laminated capacitor, in which the unevenness of the base for forming the laminated capacitor is small. Further, this structure can be formed with high flatness.

[Brief description of the drawings]

FIG. 1 (a) is a plan view showing the structure of a laminated cell which is one embodiment of the semiconductor device of the present invention, and FIGS. 1 (b) and 1 (c).
1A is a cross-sectional view taken along line AA of FIG. 1A and FIG. 2B is a cross-sectional view taken along line BB of FIG. 1A. FIGS. It is a process order drawing for explaining a manufacturing method. 1 ... P-type silicon crystal substrate, 2,3,31 ... Insulator, 4,41
... polysilicon, 5 ... gate insulating film, 6 ... polysilicon (gate electrode, word line), 7 ... n-type silicon region, 8,10 ... interlayer insulating film, 9a, 9b ... polysilicon ( Wiring), 11 ... Polysilicon (capacitor electrode), 12
...... Capacitor insulating film, 13 Conductive film (the other electrode of the capacitor), 14 ... Boundary between element region and element isolation region, 15a, 15b ... Contact hole, 16 ... Silicon oxide film, 17 ... Insulator.

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 27/08 H01L 21/8242

Claims (2)

(57) [Claims] An element region; a word line intersecting the element region; a bit line intersecting the word line and connected to the element region in a first region of the element region; A capacitor connected to the element region in a second region of the semiconductor memory device, wherein the element region is provided with an insulator extending inward from one principal surface of the semiconductor crystal substrate. Wherein the bit line is formed by providing a second groove having a width and a depth smaller than that of the first groove in the element isolation region and filling the bit line with a conductor. Semiconductor device. 2. An element region, a word line intersecting the element region, a bit line intersecting the word line and connected to the element region in a first region of the element region, A capacitor connected to the element region in a second region of the region, wherein the first region is provided inward from one main surface of the semiconductor crystal substrate. And forming a second groove in the element isolation region where the bit line is smaller in width and depth than the first groove in the element isolation region. A method for manufacturing a semiconductor device, comprising: a step of filling and forming; and a step of forming a wiring connecting the element region and the bit line.