JPH0480540B2 - - Google Patents
Info
- Publication number
- JPH0480540B2 JPH0480540B2 JP58005084A JP508483A JPH0480540B2 JP H0480540 B2 JPH0480540 B2 JP H0480540B2 JP 58005084 A JP58005084 A JP 58005084A JP 508483 A JP508483 A JP 508483A JP H0480540 B2 JPH0480540 B2 JP H0480540B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- layer
- semiconductor
- conductive layer
- capacitor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 42
- 239000003990 capacitor Substances 0.000 claims description 37
- 239000000758 substrate Substances 0.000 claims description 22
- 239000004020 conductor Substances 0.000 claims description 18
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 238000010030 laminating Methods 0.000 claims description 2
- 230000000149 penetrating effect Effects 0.000 claims 1
- 230000015654 memory Effects 0.000 description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 11
- 229920005591 polysilicon Polymers 0.000 description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 239000013078 crystal Substances 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 238000000034 method Methods 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 230000005540 biological transmission Effects 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 4
- 230000010354 integration Effects 0.000 description 4
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/33—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor extending under the transistor
Description
【発明の詳細な説明】
(a) 発明の技術分野
本発明は半導体装置に係り、特に１トランジス
タ・１キヤパシタ型ダイナミツク・ランダムアク
セスメモリ（Ｄ・RAM）構造の半導体メモリと
その製造方法に関するものである。[Detailed Description of the Invention] (a) Technical Field of the Invention The present invention relates to a semiconductor device, and particularly relates to a semiconductor memory having a one-transistor, one-capacitor type dynamic random access memory (DRAM) structure, and a method for manufacturing the same. be.
(b) 技術の背景
周知のように半導体メモリの発展は目覚しいも
のがあり、コンピユータなどの情報機器を背景に
して種々の形式構造のメモリが開発され、特に高
集積化された64Kビツトや256KビツトのLSIメモ
リは１個のMOS形半導体素子と１個のキヤパシ
タ（容量素子）とが組合わされた１トランジス
タ・１キヤパシタ型DRAM構造の半導体メモリ
が一般に広く用いられている。(b) Background of the technology As is well known, the development of semiconductor memory has been remarkable, and memories with various format structures have been developed for information devices such as computers, and in particular, highly integrated 64K-bit and 256K-bit memory. Generally, a semiconductor memory having a one-transistor/one-capacitor type DRAM structure in which one MOS type semiconductor element and one capacitor (capacitive element) are combined is widely used as an LSI memory.
(c) 従来技術と問題点
従来の1MOSキヤパシタ型のトランジスタメモ
リセルについて第１図を用いて説明すると、Ｐ型
シリコン基板１内にLOCOS法によつて作られた
局部的な厚い酸化膜層２により１トランジスタメ
モリセルの能動領域３の境界が形成される。(c) Prior Art and Problems To explain a conventional 1MOS capacitor type transistor memory cell with reference to FIG. This forms the boundary of the active area 3 of a one-transistor memory cell.
この能動領域３の上に絶縁膜４により能動領域
３から分離され、又相互間が隔離されてそれぞれ
一つの平面内にあるボリシリコン導電層５および
６が設けられ第１導電層５は１トランジスタメモ
リセルのメモリキヤパシタの一方の電極を形成し
第２導電層６はそのMOSトランジスタの伝送ゲ
ート電極（ワード線に接続）を構成する。導電層
５と６によつて覆われていない能動領域３の片側
にたとえばイオン注入によつてドープしてn+ド
ープ領域（ビツト線に接続）が形成され1MOSキ
ヤパシタ型のトランジスタメモリセルが構成され
る。しかしながら上記構造の1MOSキヤパシタ型
メモリセルにおいては、１トランジスタ・１キヤ
パシタの各素子がシリコン基板１の同一表面上に
横に配列されるため所要面積が比較的大きくな
り、より高集積化に対して制限の要素となり、そ
の対策としてスタツクド（Stacked）キヤパシタ
型、或は埋込キヤパシタ型の１トランジスタメモ
リセルが考案されている。上記スタツクドキヤパ
シタ型及び埋込キヤパシタ型の要部概略構成図を
第２図及び第３図に示す。第２図においてＰ型シ
リコン基板１０上に絶縁膜１１を介してn+ポリ
シリコン層よりなるゲート電極１２（ワード線に
接続）、該ゲート電極１２の両側のシリコン基板
１０内にソース（ビツト線に接続）１３、及びド
レイン１４のn+領域を形成し、該ゲート電極１
２上に絶縁膜１１を介してキヤパシタを構成する
第１のキヤパシタ電極１５（ドレイン領域に接
続）、及び第２キヤパシタ電極１６を形成すれば、
１トランジスタ・１キヤパシタの各素子が縦方向
に配列される。此のスタツクドキヤパシタ型構造
は前記1MOSキヤパシタ型に比べて高集積化が可
能であるがゲート電極上にキヤパシタ素子が積層
されるため表面に凹凸が出き、後の工程における
Al配線の際に断線を生ずる危険があり又製作上
歩留が悪い欠点がある。又第３図に示す埋込キヤ
パシタ型においてはＰ型シリコン基板２０にn+
埋没層２１を予め形成し、シリコン基板２０の所
定領域にn+拡散によつて図示したように埋没層
２１に接続拡散層２２を形成した後、該基板２０
に図示したごとくソース２３（拡散層２２に接
続）、ドレイン２４（ビツト線に接続）、及び絶縁
膜２５を介してゲート電極２６をそれぞれ形成す
れば基板表面のMOSトランジスト素子の真下に
n+埋没層２１とＰ型シリコン基板２０のPN接合
の空乏層によるキヤパシタ素子が作られ、第２図
のスタツクドキヤパシタ型と同様に縦型の構造で
表面の凹凸の小さい１トランジスタメモリセルが
形成されるが、Ｐ−Ｎ接合のリーク電流が大き
く、そのため電荷蓄積の保持時間が短かく、かつ
α線によつて生ずるいわゆるソフトエラー（Soft
error）に弱い欠点がある。 On this active region 3, polysilicon conductive layers 5 and 6 are provided which are separated from the active region 3 by an insulating film 4 and are isolated from each other and each lie within one plane, and the first conductive layer 5 has one transistor. One electrode of the memory capacitor of the memory cell is formed, and the second conductive layer 6 constitutes the transmission gate electrode (connected to the word line) of the MOS transistor. One side of the active region 3 not covered by the conductive layers 5 and 6 is doped, for example, by ion implantation, to form an n + doped region (connected to the bit line) to constitute a 1MOS capacitor type transistor memory cell. Ru. However, in the 1MOS capacitor type memory cell with the above structure, each element of one transistor and one capacitor is arranged horizontally on the same surface of the silicon substrate 1, so the required area is relatively large, and it is difficult to achieve higher integration. This is a limiting factor, and as a countermeasure to this, one-transistor memory cells of a stacked capacitor type or a buried capacitor type have been devised. A schematic diagram of the main parts of the stacked capacitor type and embedded capacitor type is shown in FIGS. 2 and 3. In FIG. 2, a gate electrode 12 (connected to a word line) made of an n + polysilicon layer is placed on a P-type silicon substrate 10 via an insulating film 11, and a source (bit line) is placed in the silicon substrate 10 on both sides of the gate electrode 12. ) 13 and the n + region of the drain 14, and the gate electrode 1
If a first capacitor electrode 15 (connected to the drain region) and a second capacitor electrode 16 constituting a capacitor are formed on 2 with an insulating film 11 interposed therebetween,
Each element of one transistor and one capacitor is arranged in the vertical direction. This stacked capacitor type structure allows for higher integration than the 1MOS capacitor type described above, but since the capacitor element is stacked on the gate electrode, the surface becomes uneven, making it difficult to use in later processes.
There is a risk of disconnection during Al wiring, and the production yield is low. In addition, in the buried capacitor type shown in FIG .
After forming the buried layer 21 in advance and forming the connection diffusion layer 22 on the buried layer 21 by n + diffusion in a predetermined region of the silicon substrate 20 as shown in the figure, the substrate 20
If the source 23 (connected to the diffusion layer 22), the drain 24 (connected to the bit line), and the gate electrode 26 are formed through the insulating film 25 as shown in the figure, the gate electrode 26 will be located directly under the MOS transistor element on the substrate surface.
A capacitor element is created by the depletion layer of the PN junction between the n + buried layer 21 and the P-type silicon substrate 20, and the one-transistor memory has a vertical structure with small surface irregularities, similar to the stacked capacitor type shown in FIG. A cell is formed, but the leakage current of the P-N junction is large, so the retention time for charge accumulation is short, and so-called soft errors caused by α rays occur.
error) has a weak disadvantage.
(d) 発明の目的
本発明の目的はかかる問題点を解消するためな
されたもので高集積化可能で、表面の凹凸が小さ
く、かつソフトエラーに強い半導体装置及びその
製造方法の提供にある。(d) Object of the Invention The object of the present invention was made to solve the above problems, and it is to provide a semiconductor device that can be highly integrated, has small surface irregularities, and is resistant to soft errors, and a method for manufacturing the same.
(e) 発明の構成
上記目的は、半導体基板上に形成された絶縁膜
と、該絶縁膜中に導電体層が埋め込まれてなり、
該基板と該導電体層とその間に介在する該絶縁膜
にて構成されたキヤパシタ素子と、該導電体層上
に位置する該絶縁膜の平坦化された領域上に積層
された半導体層と、該半導体層内に形成され、チ
ヤネル領域及び該半導体層の下端に達するソー
ス、ドレイン領域とを有するMIS型トランジスタ
素子と、該導電体層上に位置する該絶縁膜を選択
的に貫通して該導電体層と該MIS型トランジスタ
素子の該ソースとを接続する接続用電極とを備え
た半導体装置によつて達成される。(e) Structure of the invention The above object comprises an insulating film formed on a semiconductor substrate, and a conductive layer embedded in the insulating film,
a capacitor element composed of the substrate, the conductive layer, and the insulating film interposed therebetween; a semiconductor layer stacked on a flattened region of the insulating film located on the conductive layer; A MIS type transistor element is formed in the semiconductor layer and has a channel region and a source and drain region reaching the lower end of the semiconductor layer, and selectively penetrates the insulating film located on the conductor layer. This is achieved by a semiconductor device including a conductor layer and a connection electrode that connects the source of the MIS type transistor element.
或いは半導体基板上に第１の絶縁膜を形成し、
該第１の絶縁膜上に導電体層を被着してパターニ
ングし、該基板と該導電体層と該第１の絶縁膜に
て構成されたキヤパシタ素子を形成する工程と、
該導電体層を被覆し、平坦な表面を有する第２の
絶縁膜を形成する工程と、該導電体層上の該第２
の絶縁膜を選択的に開口し、該開口部内に導電体
を埋め込むことにより、該導電体層に接続する接
続用電極を形成する工程と、該第２の絶縁膜の該
平坦な表面及び該接続用電極上に半導体層を積層
する工程と、該半導体層内に、チヤネル領域及び
該半導体層の下端に達するソース、ドレイン領域
とを有するMIS型トランジスタ素子を、該ソース
が該接続用電極に接続するように形成する工程と
を含んだ半導体装置の製造方法によつて達成され
る。 Alternatively, forming a first insulating film on the semiconductor substrate,
depositing and patterning a conductive layer on the first insulating film to form a capacitor element composed of the substrate, the conductive layer, and the first insulating film;
forming a second insulating film covering the conductive layer and having a flat surface;
selectively opening the second insulating film and burying a conductor in the opening to form a connecting electrode to be connected to the conductive layer; A step of laminating a semiconductor layer on the connection electrode, and an MIS type transistor element having a channel region and a source and drain region reaching the lower end of the semiconductor layer in the semiconductor layer, the source of which is connected to the connection electrode. This is achieved by a method of manufacturing a semiconductor device including a step of forming the semiconductor device so as to be connected.
(f) 発明の実施例
以下本発明に係る半導体装置をその製造方法と
共に実施例により具体的に説明する。第４図は本
発明の一実施例を製造工程に従つて示す要部断面
図である。同図ａにおいて半導体基板３０たとえ
ばシリコン基板（導体）の表面を酸化して約300
Åの厚さのシリコン酸化膜（SiO2）よりなる第
１の絶縁膜３１を形成し、該絶縁膜３１上に厚さ
約5000Åのn+型ポリシリコン層よりなる導電体
層３２をCVD法によつて被着し、該導電体層３
２を連続発振アルゴン（CWAr）レーザビーム照
射によつて単結晶化する。前記絶縁膜３１は
SiO2膜の代りにSi3N4膜、Ta3O3膜を用いてもよ
い。次いで同図ｂに示すごとく前記導電体層３２
を選択酸化膜、又はレアクテイブイオンエツチン
グ（RIE）法によつて所定形状に分離パターンニ
ングした後、該分離された導電体層３２上に第２
のシリコン酸化膜よりなる絶縁膜３３を形成す
る。次いで同図ｃに示すように第２絶縁膜３３の
所定領域をパターンニングして接続窓（Via
hole）３４を形成し、次にCVD法にて該接続窓
３４を含む第２絶縁膜上にn+型ポリシリコン層
を形成した後、接続窓３４内に充填されたn+型
ポリシリコン３５を残して他を全てエツチングす
ることにより除去し、次にn+型ポリシリコン３
５の表面にたとえば熱酸化法にて二酸化シリコン
膜３６を形成し、次に再びCVD法にて所定厚の
ポリシリコン層を被着して前述したと同様に
CWArレーザビームの照射によつて該ポリシリコ
ン層を単結晶化し同時にＰ型の半導体単結晶層３
７を形成する。このようにするとn+型ポリシリ
コン３５は二酸化シリコン膜３６で覆われている
のでCWArレーザビームの照射を行なつてもn+型
不純物がＰ型半導体単結晶層３７中に拡散される
ことはない。次いで同図ｄに示すごとく再び接続
窓３４内のn+型ポリシリコン３５上の二酸化シ
リコン膜３６及びＰ型単結晶層の一部を選択的に
エツチングして除去してn+型ポリシリコン３８
を充填した後、前記Ｐ型半導体単結晶層３７を
LOCOS法によつて選択酸化して局部的な厚い酸
化膜３９によつて素子分離を行なう。次いで該半
導体単結晶層３７に通常の拡散プロセス技術を用
いてn+層のソース４０、ドレイン４１（ビツト
線に接続）及びゲート酸化膜４２を介して伝送ゲ
ート電極４３（ワード線に接続）を形成して
MOSトランジスタ素子を形成する。一方ソース
４０は接続窓３４を介して導電体層３２に導通さ
れ、該導電体層３２（キヤパシター電極）は半導
体基板３０との間に介在する絶縁膜３１中に電荷
蓄積層とからなるキヤパシター素子を形成し、本
発明による１トランジスタメモリセルを構成す
る。かかるように構成された本発明による１トラ
ンジスタ・１キヤパシタ型DRAM半導体装置は
MOSトランジスタ直下に二つの対向する導電体、
即ち導電体層３２と半導体基板３０との間の絶縁
膜３１を介在せしめたキヤパシタ素子に形成され
るので埋込キヤパシタ型（第３図）のPN接合に
よるキヤパシタの問題であるPN接合によるリー
ク電流の増加、及びソフトエラーに弱い欠点を解
消することができる。又第５図に示すごとく本発
明の製造方法を用いて半導体基板上に導電体層３
２、接続窓３４、ソース４０、伝送ゲート電極４
３に、それぞれ対応する導電体層３２′、接続窓
３４′、ソース４０′、伝送ゲート電極４３′を同
時に形成し、ドレイン４１を共通ビツト線とすれ
ば２つのトランジスタメモリセルが並列配置さ
れ、より高集積化が可能となる。(f) Embodiments of the Invention The semiconductor device according to the present invention will be specifically described below with reference to Examples along with its manufacturing method. FIG. 4 is a sectional view of a main part showing an embodiment of the present invention according to the manufacturing process. In the same figure a, the surface of a semiconductor substrate 30, for example, a silicon substrate (conductor) is oxidized and
A first insulating film 31 made of a silicon oxide film (SiO 2 ) with a thickness of 5000 Å is formed on the insulating film 31, and a conductive layer 32 made of an n + type polysilicon layer with a thickness of about 5000 Å is formed by CVD. The conductor layer 3 is deposited by
2 is single-crystalized by continuous wave argon (CWAr) laser beam irradiation. The insulating film 31 is
A Si 3 N 4 film or a Ta 3 O 3 film may be used instead of the SiO 2 film. Next, as shown in FIG.
After separating and patterning into a predetermined shape using a selective oxide film or reactive ion etching (RIE) method, a second conductor layer 32 is formed on the separated conductor layer 32.
An insulating film 33 made of a silicon oxide film is formed. Next, as shown in FIG.
After forming an n + type polysilicon layer on the second insulating film including the connection window 34 by CVD method, an n + type polysilicon layer 35 filled in the connection window 34 is formed. All the remaining parts are removed by etching, and then the n + type polysilicon 3 is removed by etching.
A silicon dioxide film 36 is formed on the surface of 5 by thermal oxidation, for example, and then a polysilicon layer of a predetermined thickness is deposited again by CVD in the same manner as described above.
The polysilicon layer is made into a single crystal by irradiation with a CWAr laser beam, and at the same time a P-type semiconductor single crystal layer 3 is formed.
form 7. In this way, since the n + type polysilicon 35 is covered with the silicon dioxide film 36, the n + type impurity will not be diffused into the P type semiconductor single crystal layer 37 even when irradiated with the CWAr laser beam. do not have. Next, as shown in FIG. 4D, the silicon dioxide film 36 and a part of the P-type single crystal layer on the n + type polysilicon 35 within the connection window 34 are selectively etched and removed again to form the n + type polysilicon 38.
After filling the P-type semiconductor single crystal layer 37 with
Selective oxidation is performed by the LOCOS method, and element isolation is performed by a locally thick oxide film 39. Next, a transmission gate electrode 43 (connected to the word line) is formed on the semiconductor single crystal layer 37 via the source 40, drain 41 (connected to the bit line) and gate oxide film 42 of the n + layer using a normal diffusion process technique. form
Form a MOS transistor element. On the other hand, the source 40 is electrically connected to the conductor layer 32 through the connection window 34, and the conductor layer 32 (capacitor electrode) is a capacitor element consisting of a charge storage layer in an insulating film 31 interposed between the semiconductor substrate 30 and the conductor layer 32. is formed to constitute a one-transistor memory cell according to the present invention. The one-transistor/one-capacitor type DRAM semiconductor device according to the present invention configured as described above is
Two opposing conductors directly below the MOS transistor,
That is, since it is formed in a capacitor element with an insulating film 31 interposed between the conductor layer 32 and the semiconductor substrate 30, leakage current due to the PN junction is a problem with capacitors using a buried capacitor type (Figure 3) PN junction. It is possible to eliminate the drawbacks of increased susceptibility to soft errors and soft errors. Further, as shown in FIG. 5, a conductor layer 3 is formed on a semiconductor substrate using the manufacturing method of the present invention.
2, connection window 34, source 40, transmission gate electrode 4
3, the corresponding conductor layer 32', connection window 34', source 40', and transmission gate electrode 43' are simultaneously formed, and the drain 41 is used as a common bit line, so that two transistor memory cells are arranged in parallel. Higher integration becomes possible.
(g) 発明の効果
以上説明したように本発明の一実施例によれば
半導体基板上の絶縁膜中に電荷蓄積層と電極とを
設けてキヤパシタを構成し、該キヤパシタの直上
に該電極を介して該キヤパシタと接続された
MOSトランジスタを設ける積層構造によつて高
集積化可能で凹凸が小さく、かつソフトエラーに
強い半導体装置とその製造が可能となり、１トラ
ンジスタメモリの高集積化、品質向上に大きな効
果がある。尚本実施例は本発明の一例としてあげ
たものであり、本発明の範囲を制限するものでは
ない。(g) Effects of the Invention As explained above, according to one embodiment of the present invention, a charge storage layer and an electrode are provided in an insulating film on a semiconductor substrate to form a capacitor, and the electrode is placed directly above the capacitor. connected to the capacitor via
The stacked structure in which MOS transistors are provided makes it possible to manufacture a semiconductor device that is highly integrated, has small irregularities, and is resistant to soft errors, and has a great effect on increasing the degree of integration and improving the quality of one-transistor memories. Note that this example is given as an example of the present invention, and is not intended to limit the scope of the present invention.
第１図、第２図、及び第３図はそれぞれ従来の
1MOSキヤパシタ型、スタツクド（Stacked）キ
ヤパシタ型、及び埋込キヤパシタ型の１トランジ
スタメモリの要部概略構成図、第４図は本発明の
一実施例を製造工程に従つて示す要部断面図、第
５図は他の実施例を示す要部断面図である。
図において、３０は半導体基板、３１は第１の
絶縁膜、３２は導電体層、３３は第２の絶縁膜、
３４は接続窓、３７は半導体単結晶層、４０はソ
ース、４１はドレイン、４２はゲート酸化膜、４
３は伝送ゲート電極を示す。
Figures 1, 2, and 3 are respectively conventional
4 is a schematic diagram of the essential parts of a 1MOS capacitor type, stacked capacitor type, and embedded capacitor type 1-transistor memory; FIG. FIG. 5 is a sectional view of main parts showing another embodiment. In the figure, 30 is a semiconductor substrate, 31 is a first insulating film, 32 is a conductive layer, 33 is a second insulating film,
34 is a connection window, 37 is a semiconductor single crystal layer, 40 is a source, 41 is a drain, 42 is a gate oxide film, 4
3 indicates a transmission gate electrode.
Claims (1)
基板と該導電体層とその間に介在する該絶縁膜に
て構成されたキヤパシタ素子と、 該導電体層上に位置する該絶縁膜の平坦化され
た領域上に積層された半導体層と、 該半導体層内に形成され、チヤネル領域及び該
半導体層の下端に達するソース、ドレイン領域と
を有するMIS型トランジスタ素子と、 該導電体層上に位置する該絶縁膜を選択的に貫
通して該導電体層と該MIS型トランジスタ素子の
該ソースとを接続する接続用電極とを備えたこと
を特徴とする半導体装置。 ２ 半導体基板上に第１の絶縁膜を形成し、該第
１の絶縁膜上に導電体層を被着してパターニング
し、該基板と該導電体層と該第１の絶縁膜にて構
成されたキヤパシタ素子を形成する工程と、 該導電体層を被覆し、平坦な表面を有する第２
の絶縁膜を形成する工程と、 該導電体層上の該第２の絶縁膜を選択的に開口
し、該開口部内に導電体を埋め込むことにより、
該導電体層に接続する接続用電極を形成する工程
と、 該第２の絶縁膜の該平坦な表面及び該接続用電
極上に半導体層を積層する工程と、 該半導体層内に、チヤネル領域及び該半導体層
の下端に達するソース、ドレイン領域とを有する
MIS型トランジスタ素子を、該ソースが該接続用
電極に接続するように形成する工程とを含むこと
を特徴とする半導体装置の製造方法。[Claims] 1. An insulating film formed on a semiconductor substrate, a conductive layer embedded in the insulating film, and composed of the substrate, the conductive layer, and the insulating film interposed therebetween. a semiconductor layer stacked on a flattened region of the insulating film located on the conductor layer; and a semiconductor layer formed in the semiconductor layer and reaching a channel region and a lower end of the semiconductor layer. A MIS type transistor element having a source and a drain region, and a connection for selectively penetrating the insulating film located on the conductive layer to connect the conductive layer and the source of the MIS type transistor element. A semiconductor device characterized by comprising an electrode. 2. A first insulating film is formed on a semiconductor substrate, a conductive layer is deposited and patterned on the first insulating film, and the substrate, the conductive layer, and the first insulating film are formed. a second capacitor element covering the conductive layer and having a flat surface;
selectively opening the second insulating film on the conductor layer and burying the conductor in the opening;
forming a connection electrode connected to the conductor layer; laminating a semiconductor layer on the flat surface of the second insulating film and the connection electrode; forming a channel region in the semiconductor layer; and source and drain regions reaching the lower end of the semiconductor layer.
1. A method of manufacturing a semiconductor device, comprising the step of forming an MIS type transistor element so that the source is connected to the connection electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58005084A JPS59129461A (en) | 1983-01-13 | 1983-01-13 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58005084A JPS59129461A (en) | 1983-01-13 | 1983-01-13 | Semiconductor device and manufacture thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59129461A JPS59129461A (en) | 1984-07-25 |
| JPH0480540B2 true JPH0480540B2 (en) | 1992-12-18 |
Family
ID=11601518
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58005084A Granted JPS59129461A (en) | 1983-01-13 | 1983-01-13 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59129461A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3477102D1 (en) * | 1984-04-25 | 1989-04-13 | Siemens Ag | One-transistor memory cell for high-density integrated dynamic semiconductor memories, and method for manufacturing the same |
| JPS60250665A (en) * | 1984-05-25 | 1985-12-11 | Mitsubishi Electric Corp | Semiconductor memory device |
| US5306648A (en) * | 1986-01-24 | 1994-04-26 | Canon Kabushiki Kaisha | Method of making photoelectric conversion device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5519820A (en) * | 1978-07-27 | 1980-02-12 | Nec Corp | Semiconductor device |
| JPS5687359A (en) * | 1979-12-19 | 1981-07-15 | Fujitsu Ltd | Manufacture of one transistor type memory cell |
| JPS58212160A (en) * | 1982-06-02 | 1983-12-09 | Toshiba Corp | Manufacture of semiconductor memory device |
| JPS59110154A (en) * | 1982-12-16 | 1984-06-26 | Nec Corp | Semiconductor memory cell |
-
1983
- 1983-01-13 JP JP58005084A patent/JPS59129461A/en active Granted
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5519820A (en) * | 1978-07-27 | 1980-02-12 | Nec Corp | Semiconductor device |
| JPS5687359A (en) * | 1979-12-19 | 1981-07-15 | Fujitsu Ltd | Manufacture of one transistor type memory cell |
| JPS58212160A (en) * | 1982-06-02 | 1983-12-09 | Toshiba Corp | Manufacture of semiconductor memory device |
| JPS59110154A (en) * | 1982-12-16 | 1984-06-26 | Nec Corp | Semiconductor memory cell |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59129461A (en) | 1984-07-25 |
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