JP3039475B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having transistors formed in a memory cell region and other regions, and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, in an integrated circuit device constituting a DRAM, a transistor around a memory cell region has an L level.
It has a DD structure, and does not employ an LDD structure for a transistor forming a memory cell. In manufacturing such a conventional integrated circuit device, first, as shown in FIG.
For example, a memory cell region 3 is formed on a p-type semiconductor substrate 301.
01a and the external region 301b, a field oxide film 302 is formed by the LOCOS method, a gate insulating film 303 is formed by the thermal oxidation method, and the gate electrode 30 is formed thereon.
4a and 304b are formed.

Next, as shown in FIG. 3B, source / drain regions 305a and 305b are formed in the memory cell region 301a and the external region 301b, respectively, using the gate electrodes 304a and 304b as a mask. Then, FIG.
As shown in (c), sidewalls 306a and 306b are formed on the side walls of the gate electrodes 304a and 304b, and then the resist pattern 30 is formed on the memory cell region 301a.
7 is formed. Thereafter, the impurity region 308 is formed in the semiconductor substrate 301 in a self-aligned manner by selectively ion-implanting the external region 301b using the gate electrode 304b and the sidewall 306b as a mask. As a result, the transistor in the external region 301b is
It has a D structure.

[0004]

SUMMARY OF THE INVENTION MISFE
With the increase in the degree of integration and performance of LSIs using T, the gate insulating film constituting a transistor is required to have a 10-bit structure in order to improve the current capability of the transistor and to suppress the short channel effect.
It is becoming thinner than about nm. For this reason, the band-to-band tunneling current generated between the gate electrode and the source / drain region under the gate electrode cannot be ignored in terms of device characteristics.

[0005] The inter-band tunneling current is the following phenomenon. That is, when a potential is not applied to the gate electrode but a potential is applied between the source and the drain, the overlap region is depleted at the gate insulating film interface. Then, as the gate insulating film becomes thinner, a current is observed between the gate electrode and its overlapping region. This band-to-band tunneling current is not negligible in a memory cell storing a small amount of charge, and deteriorates the hold characteristics of the transistor.

In order to prevent this problem, the impurity concentration of the source / drain regions may be reduced. However, as described above with reference to FIG. 3B, part of the formation of the source / drain region of the transistor in the memory cell and part of the formation of the source / drain region of the peripheral transistor are performed in the same step. I have. Therefore, if the source / drain concentration of the transistor in the memory cell is simply reduced, the source / drain concentration of the peripheral transistor will be reduced. In particular, the impurity concentration in the low concentration diffusion region overlapping with the gate electrode of the peripheral transistor is reduced. That is, conventionally,
In order to suppress the deterioration of the hold characteristic of the transistor in the memory cell, it is necessary to sacrifice the characteristic of the peripheral transistor such as a decrease in the drain current of the peripheral transistor in the external region.

The present invention has been made to solve the above problems, and suppresses deterioration of the hold characteristics of the transistors of the memory cell without sacrificing the characteristics of the transistors other than the memory cell. The purpose is to:

[0008]

According to a semiconductor device of the present invention, a transistor constituting a memory cell has a source / drain region which does not have an LDD structure and has no memory cell.
In the semiconductor device the source-drain region of the near-Ru transistor has an LDD structure, the source and drain regions of the gate insulating film interface between the gate electrode and the overlapped area density of the memory cell, no memory cell area
Concentration of source / drain regions of transistors
Than the concentration of the gate insulating film interface of diffusing region is overlapped with the gate electrode region and to be a low concentration. That is, in this semiconductor device, the band-to-band tunneling current is suppressed in the transistor in the memory cell.

In the method of manufacturing a semiconductor device according to the present invention, first, a gate insulating film is formed in a memory cell region and a region without a memory cell on a semiconductor substrate, and a gate electrode is formed on the gate insulating film. A source / drain region is formed so that a concentration of a gate insulating film interface in a region overlapping with a gate electrode of a memory cell in a cell region becomes a predetermined concentration, and a gate electrode of a transistor in a region without a memory cell is formed. The first diffusion region is formed using the gate electrode as a mask so that the concentration at the gate insulating film interface in the overlapping region is higher than that in the source / drain region in the memory cell region. A side wall is formed on the side surface of the gate electrode, and a gate electrode and an Fine sidewalls and to form a source and drain regions of the LDD structure by forming a second diffusion region of a higher concentration than the first diffusion region as a mask. Therefore, the transistor in the memory cell of the semiconductor device is formed such that the interband tunneling current is suppressed.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. 1 and 2 are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. A method of manufacturing a semiconductor device according to this embodiment will be described. First, as shown in FIG. 1A, for example, a memory cell region 101a and an external region 101b are formed on a p-type semiconductor substrate 101 by a LOCOS method. A field oxide film 102 is formed, and a gate insulating film 103 is formed by a thermal oxidation method. The thickness of the field oxide film 102 is about 300 nm, and the thickness of the gate insulating film 103 is about 10 nm. Then, the gate insulating film 10
3, a 300 nm-thickness gate electrode 104 made of polysilicon doped with n-type impurities at a high concentration, for example.
a, 104b are formed. In addition, polycide may be used as the gate electrode material.

Next, as shown in FIG. 1B, a resist pattern 121 is formed by a known photolithography technique so as to cover the area of the external area 101b. Then, by using this resist pattern 121 and selectively implanting ions into the memory cell region 101a, the source / drain region 105a is formed using the gate electrode 104a as a mask. In this ion implantation, for example, P
(Phosphorus) is implanted at 1 × 10 ¹³ cm ⁻² at 40 keV. As a result, the source / drain region 105a has an implantation depth xj of about 0.2 μm. Here, assuming that the dose at the time of ion implantation is Do, the average impurity concentration ID is “ID
= Do / xj ". Therefore, in this case, the average impurity concentration is 1 × 10 ¹³ cm ⁻² /0.2×10 ⁻⁴ cm =
It becomes 5 × 10 ¹⁷ cm ⁻³ . The impurity is not limited to P but may be As (arsenic).

Then, after removing the resist pattern 121, as shown in FIG. 1C, a resist pattern 122 is formed so as to cover the memory cell region 101a, and ion implantation is selectively performed on the external region 101b. Then, the source / drain region 105b is formed using the gate electrode 104b as a mask. In this ion implantation, for example, P is implanted at 40 keV at 3 × 10 ¹³ cm ⁻² . As a result, the source / drain region 105b has an implantation depth xj of about 0.2 μm. Therefore, by the foregoing, the average impurity concentration of the source and drain regions 105b ^{is, 3 × 10 13 cm- 2 /0.2×10} -4 cm = 1.
It becomes 5 × 10 ¹⁸ cm ⁻³ . This has a higher concentration than the source / drain region 105a of the memory cell region 101a formed earlier. Further, since the source / drain region 105b is formed by one ion implantation, it has a single concentration profile. Therefore, the external area 101
Source / drain region 105 which is a low concentration diffusion region of b
The controllability of the concentration of b is good, and the variation of the drain current is small. Note that the impurity is not limited to P, but may be As.

Then, after removing the resist pattern 122, as shown in FIG.
Sidewalls 106a and 106b made of, for example, an insulating film such as SiO ₂ are formed on side surfaces of the surface 104b. In addition,
The material of the side walls 106a and 106b may be another insulating material such as a silicon nitride film. Although this sidewall needs to be formed on the gate electrode 104b, the gate electrode 104 in the memory cell region 101a is formed.
a need not be formed. Then, the memory cell region 10
By forming a resist pattern 123 so as to cover 1a and selectively implanting ions into external region 101b, impurity region 1 is formed in semiconductor substrate 101 in a self-aligned manner using gate electrode 104b and sidewall 106b as a mask.
08 is formed. In this ion implantation, As is 50 ke
Implant 3 × 10 ¹⁵ cm ^{−2 with} V. As a result, the outer region 1
The transistor 01b has an LDD structure.

Then, as shown in FIG. 2B, after forming the interlayer insulating film 109, a contact hole for connecting to one of the source / drain regions 105a of the transistor in the memory cell region 101a is formed, and A storage electrode 110 made of silicon is formed with a thickness of 300 nm, and a capacitive insulating film 111 made of SiN with a thickness of 5 nm is formed so as to cover the storage electrode 110. Then, a 150 nm-thick common electrode 112 made of polysilicon is formed thereon. Next, an interlayer insulating film 113 is formed, and the memory cell region 10 is formed.
A contact hole 114 for connecting to the other of the source / drain region 105a of the transistor 1a and a contact hole 115 for connecting to the transistor in the external region 101b are formed. Then, an electrode wiring 116 made of Al connected to each transistor through the contact holes 114 and 115 is formed.

By the above manufacturing method, the memory cell area 101
source / drain region 10 of the transistor constituting
5a does not have an LDD structure, and the source / drain region 105b and the impurity region 108 of the transistor in the external region 101b, which is a region without a memory cell, have an LDD structure, and the source / drain region 105a of the memory cell region 101a has a gate electrode. The concentration of the interface between the gate insulating film 103 and the region overlapping with the gate insulating film 103 is set to be lower than the concentration of the interface between the gate electrode 104b and the source / drain region 105b of the transistor in the external region 101b. be able to.

In the above embodiment, first, the impurity regions serving as the source / drain regions of the memory cell region are formed. However, the present invention is not limited to this. An impurity region (low-concentration diffusion region) serving as a low-concentration source / drain region constituting a transistor in an external region may be formed first. In the above embodiment, the impurity is introduced by ion implantation. However, the present invention is not limited to this. For example, the impurity may be introduced by diffusion. By the way, in the above-described embodiment, the case where the thickness of the gate insulating film is about 10 nm has been described. However, when the thickness of the gate insulating film is further reduced, in order to suppress the interband tunneling current, it is necessary to use other than the memory cell. Both the concentration of the lightly doped diffusion region of the transistor in the external region and the concentration of the source / drain region of the transistor of the memory cell need to be lower than those described above. However, the relative relationship that the concentration of the low concentration diffusion region of the transistor in the external region other than the memory transistor is higher than the concentration of the source / drain region of the transistor of the memory cell is maintained.

[0017]

As described above, the concentration of the gate insulating film interface in the region where the source / drain region of the memory cell overlaps with the gate electrode is lower than the concentration of the source / drain region of the transistor in the region without the memory cell. By setting the concentration diffusion region to be lower than the concentration at the gate insulating film interface in the region where the concentration diffusion region overlaps with the gate electrode, the inter-band tunneling current is suppressed in the memory cell,
While the hold characteristics can be improved, a transistor in a region other than the memory cell has an effect that a desired drain current can be obtained.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view for describing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view following FIG. 1 for illustrating the method of manufacturing the semiconductor device in the embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a partial configuration of a manufacturing process of an integrated circuit device forming a conventional DRAM.

[Explanation of symbols]

101: semiconductor substrate, 101a: memory cell region, 10
1b external region, 102 field oxide film, 103
Gate insulating films, 104a, 104b ... gate electrodes, 10
5a, 105b ... source / drain regions, 106a, 1
06b: sidewall, 108: impurity region, 10
9, 113 ... interlayer insulating film, 110 ... storage electrode, 111 ...
Capacitance insulating film, 112: common electrode, 114, 115: contact hole, 116: electrode wiring, 121, 122, 1
23 resist pattern.

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 27/108 H01L 21/8234 H01L 21/8242 H01L 27/088

Claims (7)

(57) [Claims] 1. A no source-drain region of the transistor constituting the memory cell is in the LDD structure, the semiconductor device the source-drain region of the region without near-Ru transistor of said memory cell is in the LDD structure, the memory The concentration at the gate insulating film interface in the region where the source / drain region of the cell overlaps with the gate electrode,
The source of a transistor in an area without the memory cell;
A semiconductor device, characterized in that the low-concentration diffusion region in the source / drain region has a lower concentration than the concentration at the gate insulating film interface in a region overlapping with the gate electrode. 2. The semiconductor device according to claim 1, wherein a source / drain region of a transistor constituting said memory cell and a source / drain region of a transistor in a region where said memory cell is absent are phosphorus or arsenic impurities. A semiconductor device comprising: 3. The semiconductor device according to claim 1, wherein a thickness of a gate insulating film of a transistor forming the memory cell and a thickness of a gate insulating film of a transistor in a region where the memory cell is not present are 10 nm. A semiconductor device characterized by the following. 4. The semiconductor device of any one of claims 1 to 3, a semiconductor device, wherein the memory cell is a DRA M. 5. The semiconductor device according to claim 4, wherein said memory cells are of a stack type. 6. A step of forming a gate insulating film in a memory cell region and a region without a memory cell on a semiconductor substrate, a step of forming a gate electrode on the gate insulating film, and a memory cell in the memory cell region Forming a source / drain region such that the concentration at the gate insulating film interface in a region overlapping with the gate electrode becomes a predetermined concentration; and overlapping the gate electrode of the transistor in the region without the memory cell. Forming a first diffusion region using the gate electrode as a mask so that the concentration of the interface of the gate insulating film in the region to be formed is higher than the concentration of the source / drain region in the memory cell region; Forming a sidewall on a side surface of the gate electrode of the transistor in a region where there is no memory cell; Forming a second diffusion region having a higher concentration than the first diffusion region by using the gate electrode and the sidewall in a region where the memory cell is not formed as a mask, and forming a source / drain region having an LDD structure; A method for manufacturing a semiconductor device, comprising at least: 7. The method of manufacturing a semiconductor device according to claim 6, wherein the source / drain regions in the memory cell region and the region without the memory cell are formed by ion implantation. Device manufacturing method.