JP3399229B2 - Method for manufacturing read-only semiconductor memory device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a read-only semiconductor memory device and its manufacturing method.

[0002]

[Prior Art and Problems to be Solved by the Invention] The ROM capacity of semiconductors has tended to increase in recent years, and since system-on-silicon for building a system on silicon is required, wiring becomes more complicated. It is becoming more and more multilayered.

In a mask ROM mounted on a microcontroller, that is, a read-only semiconductor memory device,
Shortening TAT (turn around time; period from determination of program contents to shipping) and cost reduction are major problems. As a program method for the mask ROM, there is a contact program method, for example.
This method has the advantage that the TAT is short because the programming step is close to the final step of the manufacturing process, but since one contact is required for one transistor, the occupied area of the memory cell becomes large, which is economically disadvantageous. is there.

There is also an ion implantation program system,
There are a depletion method and a high Vth ion implantation method. Among them, the high Vth method is an excellent method in that the TAT is relatively short and the memory cell size is not large. By the way, in order to further reduce the memory cell size, there is a structure in which one contact is provided to a common diffusion layer between two transistors adjacent to each other and the contact is formed in a self-aligned manner. In this method, a high Vth ion implantation method is promising.

However, if the program ion implantation is performed after the metal wiring is formed, the reliability of Al such as EM (electromigration) is deteriorated, so that the activation cannot be sufficiently performed. Therefore, the junction destruction cannot be recovered, the leak current increases, and the memory "1",
It becomes difficult to determine “0”. As a result, there is a problem that the reliability of the semiconductor device is reduced.

On the other hand, in the ion implantation method, "1",
In order to reliably perform the “0” determination, it is necessary to earn an on-current, and there are methods such as increasing the gate width, which leads to an increase in cell size. Further, in order to perform the program ion implantation after the metal wiring, as shown in FIG. 8, it is necessary to have a structure in which the metal wiring does not pass through the channel region, and in this case as well, the cell size becomes large. That is,
In FIG. 8, the aluminum wiring layer 32 is wired not on the channel region of the transistor Tr but on the LOCOS 21, and is connected to the contact SC formed in the diffusion region between a pair of adjacent transistors via the protrusion 32a. There is.

Further, it is unavoidable that the misalignment between the program mask and the gate becomes larger as the programming process becomes a later process, and the mask misalignment margin is expected in advance, which also leads to the expansion of the cell size. . As described above, in the method of increasing the threshold value of the transistor by ion implantation, the cell size is inevitably increased when the TAT is shortened, which leads to an increase in chip cost.

Further, there is a problem that the number of processes is increased as a factor of increasing the chip cost. In the prior art, since the impurities are introduced by using the program-dedicated mask, the mask ROM is not formed for the photoresist process and the ion implantation process. The cost increased compared to the case.

Therefore, there has been a demand for development of a read-only semiconductor memory device which ensures high reliability, further reduces cost and shortens TAT. The present invention has been made in view of the above demands, and an object of the present invention is to provide a read-only semiconductor device having high reliability, low cost, and short TAT even though the program is an ion implantation method, and a manufacturing method thereof.

[0010]

In order to achieve the above object, the present invention provides a field effect transistor on a semiconductor substrate.
Step of forming a constituent gate electrode, and the above gate electrode
The step of covering the electrode coating insulating film with
The step of covering with an etching stopper film and the above etching
Step of forming an interlayer insulating film on the upper layer of the stopper film
And the pattern of contact holes and should be programmed
The part corresponding to the channel region of the field effect transistor
Step of forming a mask that simultaneously opens the pattern
And the etching using the mask, the field effect type
A contact hole reaching the diffusion layer of the transistor
Channel region of field effect transistor to be programmed
For the part corresponding to
Ion implantation holes reaching up to
Program by insulating film formation and ion implantation
Process of introducing impurities for use and activity of the introduced impurities
Process of forming a wiring layer on the contact hole
Read-only semiconductor characterized by having a step of
A method for manufacturing a body storage device is provided.

The above-mentioned read-only semiconductor memory device of the present invention
The manufacturing method of the device is preferably for ion implantation of the wiring layer.
Also formed in the holes.

Manufacture of a read-only semiconductor memory device of the present invention
The read-only semiconductor device manufactured by the manufacturing method is a read-only semiconductor memory device in which programming is performed by implanting ions into a field effect transistor, and an interlayer insulating film covering the field effect transistor is
In this structure, an ion implantation hole is formed in a portion corresponding to the channel portion of the programmed field effect transistor, and a contact hole is formed in a diffusion layer of the transistor. In such a structure, a hole for programming by ion implantation and a contact hole for connecting a diffusion layer of a transistor and a wiring layer are simultaneously formed in an interlayer insulating film covering a transistor by an etching process using one mask. It can be realized by forming.

Therefore, since the programming process is the same as the contact forming process, there is no dedicated program process and the process is shortened. Further, since the wiring layer is formed in the contact hole after forming the hole in the interlayer insulating film, there is no fear that the annealing will affect the wiring layer, and therefore the sufficient annealing can be performed. Therefore, the junction leak and the variation in Vth are reduced, the read error is reduced, and the reliability is improved. Further, since the region where ions are implanted, that is, the channel region of the transistor and the wiring can be overlapped with each other, the cell size is reduced and the degree of integration is improved. In addition, the TAT is short because ions are implanted into the transistor after the transistor is formed.

In this case, since the ion implantation hole is formed by etching in the interlayer insulating film at a portion corresponding to the channel region of the transistor, the electrode coating insulating film covering the gate electrode of the transistor is provided with an etching stopper for protecting it from etching. It forms a film.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION A semiconductor device and a method of manufacturing the same according to the present invention will be described below in detail with reference to the embodiments shown in the drawings. Needless to say, the present invention is not limited to the following modes.

The semiconductor device of the present embodiment is a mask used for a controller having a structure in which a wiring is connected in a self-aligned manner to a common diffusion layer between a pair of transistors adjacent to each other by programming by increasing the threshold value of the transistor. This is a ROM, and its manufacturing process will be described with reference to FIGS.

1 and 2 are cell plan views of the manufacturing process, and FIGS. 3 to 7 are sectional views of the process from FIG. 2C to FIG. 2D. This read-only ROM is a mask ROM having a structure in which two transistors are shared by one contact in a T-shaped cell.

First, the steps leading to FIG. 3 will be described. Figure 3-
7A is a cross-sectional view taken along the line AA ′ of FIGS. 2C and 2D, showing a cross section of a cell in which programming is not performed, and FIG. (C), B- in FIG. 2 (d)
FIG. 9 is a cross-sectional view taken along the line B ′ of the cell for programming.

As shown in FIG. 1A, a thick element isolation oxide film (LOCOS) 21 is formed on the p-type semiconductor substrate 10 by thermal oxidation while protecting a region which becomes an active region with a silicon nitride film. Then, after removing the silicon nitride film, a gate oxide film (not shown) is formed. The thickness of the gate oxide film is 5.
It is about 0 to 10 nm. 1 and 2, a cell boundary line b is shown to show the area of one memory cell.

Next, as shown in FIG. 1B, for example, after depositing polycrystalline silicon 31a, silicide 31b, and silicon oxide, patterning is performed to form a gate electrode 31 and a gate electrode composed of polycrystalline silicon and silicide. An offset insulating film 23 is formed on the above. The gate length is 0.
It is about 35 μm. Then, an n-type impurity is ion-implanted to form an LDD (lightly doped drain) 11.

After that, as shown in FIG. 2C, a side wall 24 is formed on a side portion of the gate electrode 31 by depositing silicon oxide and then etching back. The offset insulating film 23 and the sidewall 24 form an electrode coating insulating film 25 that covers the gate electrode 31. After forming the sidewalls 24, n-type impurities are implanted to form the source / drain 12. This allows
Transistors Tr1 to Tr7 are formed.

Next, the etching stopper film 26 is formed by, for example, the CVD method. This etching stopper film 2
Reference numeral 6 is for protecting the gate electrode covering insulating film 25 from etching, and is made of a material having an etching ratio different from that of the interlayer insulating film 27 to be formed next, for example, Si ₃ N ₄ is used. In addition, it may be composed of a metal oxide, and may be formed by, for example, a method of oxidizing alumina, titanium oxide or the like after forming a metal film, or by directly forming a metal oxide film. The film thickness is about 80 to 100 nm. After that, the interlayer flattening film 27 is formed. This is BPSG
Is subjected to CVD for about 600 nm and flattened by reflow or etch back.

Next, a contact hole for a common diffusion layer between transistors adjacent to the interlayer insulating film,
The step of forming an ion implantation hole HI at a portion corresponding to the channel region of the transistor (Tr1 in this case) to be programmed is started. Resist R on the interlayer insulating film 27
After applying 1, the resist is patterned. In this step, as shown in FIG. 2C, the contact pattern 3 and the program pattern 5 are formed by one mask.

The contact mask is a mask ROM.
It is the same as the mask for programmed ion implantation. Since the program pattern of the mask ROM differs depending on the user, different masks are used. In the present invention, since it also serves as a contact mask, a dedicated process for programming is unnecessary. Through the above steps, the structure shown in FIG. 3 can be obtained.

Thereafter, as shown in FIG. 4, contact etching is performed. Etching is preferably performed wet or dry to form a taper at the interface with the resist R1. In addition, this etching ends with the etching stopper film (Si ₃ N ₄ ) 26. At this time, at least the bottom of the contact, and further, all of the exposed etching stopper film 26 is removed by overetching or etching in another step. In this case, the contact hole CH is formed in the diffusion layer between the pair of transistors in a self-aligned manner. Further, a hole HI for ion implantation is formed in the interlayer insulating film 26 above the channel region of the transistor Tr1 to be programmed.

After that, as shown in FIG.
Injection. The program is, for example, B⁺Using
Lugie 80 KeV to 120 KeV, Dose amount 5 ×
10 ¹³~ 8 × 10¹³cm^-2It is a degree. At this time, the same
As shown by the broken line B in the figure, the contact part is also programmed.
Ions are injected, but the energy is high and the dose is high.
There is not much so there is no effect on contact resistance.

Next, as shown in FIG. 6, the resist R1 is removed, and sufficient annealing is performed. Annealing is performed in a nitrogen atmosphere at 800 to 900 degrees Celsius for about 20 to 60 minutes. Transistor Tr1 programmed by annealing
The impurity is diffused into the channel portion of and the impurity diffusion layer 13 having the same conductivity type as the substrate is introduced to increase the threshold value,
Since it is activated, the defect in the drain junction is recovered. In this case, since the annealing causes auto-doping from the insulating film 26 to increase the contact resistance, the bottom of the contact is lightly removed by etching after the annealing. In addition, contact ion implantation is performed at about 10 ¹⁵ cm ^-2, so that sufficient contact can be made.

Thereafter, as shown in FIGS. 7 and 2D, a metal wiring layer 32 is formed by sputtering to form a bit line. Finally, an unillustrated overcoat is formed and the pad is opened to complete the read-only semiconductor device of the present invention.

The structural characteristic of the read-only semiconductor device thus obtained is that it covers the electrode covering insulating film 25 composed of the offset insulating film 23 covering the gate electrode 31 and the side wall 24 and the interlayer insulating film. An etching stopper film 26 having an etching ratio different from that of the film 27 is formed, and an ion implantation hole HI for adjusting a threshold is formed in the interlayer insulating film 27 on the transistor Tr1 to be programmed. Wiring layer 3 on HI
2 is formed, a contact hole CH formed by the same mask as the formation of the hole HI for ion implantation is formed, and the wiring layer 32 is formed in this hole CH. Is connected to the common diffusion layer 12 between the pair of transistors and is formed in a self-aligned manner.

In the above-mentioned manufacturing method, since the contact mask and the program mask can be covered by a single mask, it is possible to reduce the program-dedicated mask and the program-dedicated process even though the ion implantation method is used, and the cost can be reduced. Further, by sufficiently implanting the impurities for threshold value adjustment and then activating the impurities, a junction leak can be reduced and a highly reliable mask ROM can be provided. Due to such impurity diffusion, it is possible to take a sufficient margin against the variation in the film thickness of the interlayer film at the time of ion implantation.

Further, since the programming process and the contact forming process can be performed at the same time, the TAT can be shortened as compared with the method of programming before forming the gate. Moreover,
Since the contact can be formed in a diffusion layer between adjacent transistors in a self-aligned manner, the cell size can be reduced. Further, since the wiring layer can be formed on the gate electrode of the transistor, the cell size can be reduced also in this respect. Since the gate width can be increased with the reduction of the cell size, high-speed reading is possible depending on the application.

In this embodiment, one layer of metal wiring is used.
It goes without saying that even in the case of a multi-layer, an interlayer film can be formed and formed by the conventional technique. Further, although the program method in which the threshold value is increased by ion implantation has been described, the present invention can of course be applied to a depletion type method. Furthermore, although the read-only semiconductor device has been described as an OR type, it may be an AND type. Furthermore, the example in which the contacts are formed in a self-aligned manner has been described, but it is not necessary to be self-aligned, and various modifications can be made without departing from the scope of the present invention.

[0033]

The read-only semiconductor device of the present invention has features such as high reliability, low cost, and short TAT. Also,
The method for manufacturing a read-only semiconductor device of the present invention can easily manufacture a read-only semiconductor device having high reliability, low cost, and short TAT.

[Brief description of drawings]

FIG. 1 is a memory cell plan view showing a manufacturing process of a method of manufacturing a read-only semiconductor memory device according to an embodiment of the present invention, (a) is an element isolation stage by LOCOS, and (b) is a gate. The steps up to the electrode formation stage are shown.

FIG. 2 shows a step following that of FIG. 1, (c) showing a patterning step of a contact pattern and a program pattern, and (d) showing a metal wiring forming step.

FIG. 3 is a schematic cross-sectional structure diagram showing a manufacturing process of a method of manufacturing a read-only semiconductor memory device according to an embodiment of the present invention, showing up to a patterning process of a contact pattern and a program pattern, (a) Is shown in FIG.
2A is a cross-sectional view taken along line AA ′ in FIG.
FIG. 6 is a cross-sectional view taken along line BB ′ in FIG.

FIG. 4 shows a step following that of FIG. 3, showing up to the step of forming contact holes and program holes;
Is a cross-sectional view taken along the line AA ′ in FIG.
FIG. 2B is a sectional view taken along the line BB ′ in FIG.

5 shows a step following that of FIG. 4, showing up to the step of introducing a program impurity, FIG. 5A is a cross-sectional view taken along the line AA ′ in FIG. 2C, and FIG. FIG. 2B is a sectional view taken along line BB ′ in FIG.

FIG. 6 shows a step following that of FIG. 5, showing up to the step of activating program impurities by annealing, (a)
Is a cross-sectional view taken along the line AA ′ in FIG.
FIG. 2B is a sectional view taken along the line BB ′ in FIG.

FIG. 7 shows a step following that of FIG. 6, showing up to the step of forming a metal wiring layer, wherein FIG. 7A shows a step A- in FIG.
2B is a cross-sectional view taken along the line A ′, and FIG.
It is sectional drawing which followed the B'line.

FIG. 8 is a plan view of a memory cell of a conventional read-only semiconductor memory device using an ion implantation programming method.

[Explanation of symbols]

10 ... Substrate, 11 ... LDD, 12 ... Source / Drain,
Reference numeral 13 ... Program impurity diffusion layer, 21 ... Element isolation insulating film, 23 ... Offset insulating film, 24 ... Side wall,
25 ... Electrode coating insulating film, 26 ... Etching stopper film, 27 ... Interlayer insulating film, 31 ... Gate electrode, 32 ... Wiring layer, Tr ... Transistor, CH ... Contact hole, H
I ... Hole for ion implantation.

Continuation of front page (56) References JP-A-6-151781 (JP, A) JP-A-5-275654 (JP, A) JP-A-62-200597 (JP, A) JP-A-6-260618 (JP , A) JP-A-1-282863 (JP, A) JP-A-8-46173 (JP, A) JP-A-4-304671 (JP, A) JP-A-5-283653 (JP, A) (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/8246 H01L 27/112

Claims (2)

(57) [Claims] 1. A step of forming a gate electrode constituting a field effect transistor on a semiconductor substrate, a step of covering the gate electrode with an electrode coating insulating film, and a step of coating the electrode coating insulating film with an etching stopper film. And a step of forming an interlayer insulating film on the etching stopper film, and a step of forming a mask that simultaneously opens a pattern of contact holes and a pattern of a portion corresponding to a channel region of a field effect transistor to be programmed. And ion implantation for reaching the etching stopper film in the contact hole reaching the diffusion layer of the field effect transistor and the portion corresponding to the channel region of the field effect transistor to be programmed by etching using the mask. Forming a hole and a hole in the interlayer insulating film, respectively. A read-only semiconductor memory device including: a step of introducing a programming impurity by ion implantation; a step of activating the introduced impurity; and a step of forming a wiring layer in the contact hole. Manufacturing method. 2. A method of manufacturing a read-only semiconductor memory device according to claim 1, wherein also be formed on ion implantation holes the wiring layer.