JPH0422170A - Manufacture of nonvolatile memory - Google Patents

Abstract

PURPOSE:To restrain an element form being deteriorated, to make the element fine and to prevent the conductivity of a channel stopper region from being inverted by a method wherein, after a field oxide film and a gate oxide film are formed, ions are implanted and the channel stopper region is formed. CONSTITUTION:An SiO2 film as a fixed oxide film 6 is formed on a p-Si substrate 1 by a thermal oxidation operation; in addition, an SiO2 film as a gate oxide film 7 is formed by a thermal oxidation operation. Then, a poly-Si film as a conductive film for gate electrode use is grown on the whole surface of the substrate 1; it is patterned; and a gate electrode 8 is formed. Then, a resist film 4 having a thickness of 1mum is formed as an implantation mask on an element region; and B<+> is implanted into the substrate. An active annealing operation to be executed in a later process is executed at 90 deg.C for 10 minutes; implanted boron forms a channel stopper region 5 which electrically isolates adjacent elements; and the elements are isolated. Thereby, it is possible to prevent the region 5 from being extended in the transverse direction, to restrain the elements from being deteriorated, to make the elements fine and to prevent the conductivity of the region 5 from being inverted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a method of manufacturing a nonvolatile memory, and particularly to a method of forming an element isolation region.

The purpose is to prevent the channel stopper region from expanding in the lateral direction, thereby suppressing device deterioration and making it possible to miniaturize the device, so that device isolation is not inhibited by program implantation.

1) Form a field oxide film in an isolation region on a semiconductor substrate, form a gate oxide film on the substrate in an element region surrounded by the isolation region, and then form a gate oxide film on the substrate including the element region. two steps of forming an electrode and introducing impurities of the opposite conductivity type to the substrate into the mountain substrate on both sides of the gate electrode to form a source/drain region; and forming a source/drain region in the substrate in the isolation region. and forming a channel horn region by implanting ions of an impurity of the same type as that of the substrate through the field oxide film.

2) The method is structured so as to include the step described in 1) above and the step of implanting ions of a non-conducting material having a conductivity type opposite to that of the substrate into the channel region of the cell FET to be written.

3) The method is configured to include the step described in 2) above and a step of implanting impurity ions of the same conductivity type as the substrate into the substrate in the isolation region before forming the field oxide film.

[Industrial application field]

The present invention relates to a method of manufacturing a nonvolatile memory, and more particularly to a method of forming an element isolation region.

In recent years, miniaturization of elements has become essential in integrated circuits.
Furthermore, it is necessary to perform sufficient element isolation.

In particular, in highly integrated non-volatile memories such as mask ROMs, the transistors in the constituent cells have been miniaturized to the limit, so element isolation technology has become important. can be used. [Prior Art] FIGS. 4(a) to 4(d) are cross-sectional views illustrating a conventional element isolation method.

In FIG. 4(a), an underlying silicon dioxide (SiO□) film 2 formed by thermal oxidation for LOCO3 (partial oxidation) and silicon nitride formed by vapor phase growth (CVD) are deposited on a p-type silicon (p-3i) substrate J. (SisN4) film 3 is deposited.

In FIG. 4(b), Si3N<
Film 3 and SiO□ film 2 are etched to leave only the top of the element region.

Next, using the resist film 4 as an implantation mask, boron ions (B') are implanted into the substrate. This boron forms a channel stopper region 5 that electrically isolates adjacent elements.

Element isolation is performed.

In FIG. 4(C), the resist film 4 is removed.

A 5I02 film 6 is formed as a field oxide film by thermal oxidation using the Si3N4 film 3 as an oxidation-resistant mask.

At this time, the channel stopper region 5 expands into the element region as indicated by 5A due to the diffusion of boron due to the heat treatment.

In FIG. 4fd), the Si3N film 3 and the 5iO7 film 2 are removed by etching, and a new SiO□ film 7 is formed as a gate oxide film by thermal oxidation.

As described above, field oxide film 6 and channel stopper region 5A are formed in the element isolation region around the element region, and element isolation is performed.

However, in the conventional method described above, a large amount of boron is implanted in order to achieve sufficient element isolation. This causes characteristic deterioration such as fluctuations in the threshold voltage of the transistor and reduction in current amplification factor.
The channel stopper injection volume was not large enough (
usually.

10"cm-2 or less).

Therefore, attempts were made to achieve sufficient element isolation.

It is made of EEPROM (electrically erasable and programmable read-only memory), which requires high voltage resistance.

The method involves implanting boron after forming a field oxide film. According to this method, since boron can be implanted at a high concentration, element isolation is sufficiently performed.

However, since the step after implantation requires heat treatment to form a gate oxide film, the channel stopper region expands, which hinders device miniaturization.

[Problem to be solved by the invention]

Therefore, if element isolation is performed using conventional techniques.

This has caused problems such as deterioration of transistors and hindering miniaturization of elements.

Furthermore, if the amount of implantation into the channel stopper region is small, a problem arises in that the conductivity of the channel stopper region is reversed by program implantation during writing.

The present invention prevents the channel stopper region from expanding in the lateral direction, thereby making it possible to suppress device deterioration and miniaturize the device, and
The purpose of this invention is to increase the amount of implantation into the channel stopper region to achieve sufficient element isolation, and to prevent the conductivity of the channel stopper region from being reversed due to programmed implantation.

[Means to solve the problem]

What is the solution to the above problem?

1) Form a field oxide film in an isolation region on a semiconductor substrate, form a gate oxide film on the substrate in an element region surrounded by the isolation region, and then form a gate electrode on the substrate including the element region. forming a source/drain region by introducing impurities of a conductivity type opposite to that of the substrate into the substrate on both sides of the gate electrode, and forming a source/drain region in the substrate in the isolation region; forming a channel stopper region by implanting impurity ions of the same conductivity type as the substrate through the film;
or.

2) A method for manufacturing a nonvolatile memory comprising the step described in 1) above and the step of implanting impurity ions of a conductivity type opposite to that of the substrate into the channel region of a cell FET to be written, or 3) 2) above. This is achieved by a method of manufacturing a non-volatile memory, which includes the steps described in 1 and 2, and a step of implanting impurity ions of the same conductivity type as that of the substrate into the substrate in the isolation region before forming the field oxide film.

[Effect]

The present invention forms a channel stopper region by performing ion implantation after forming a field oxide film and a gate oxide film, in order to prevent the implanted elements in the channel stopper region from diffusing into the element region during post-process heat treatment. This eliminates the influence of post-process heat treatment.

However, if the implantation for forming the channel stopper region is performed immediately after the formation of the gate oxide film at this time, the gate oxide film will deteriorate due to resist coating, etc., so the implantation must be performed after the formation of the gate electrode.

In this way, since the implantation for forming the channel stopper region is performed after the formation of the gate oxide film, the temperature of the heat treatment in the post-process is low, so that the lateral diffusion of the implanted element becomes negligible.

〔Example〕

FIGS. 1A to 1C are cross-sectional views illustrating an element isolation method according to an embodiment of the present invention.

In FIG. 1(a), imLOc on p-3i substrate 1
A SiO □ film 6 with a thickness of 5000 thick is formed as a field oxide film by thermal oxidation using the O3 method, and a 5i02 film 7 with a thickness of 200 thick is further formed as a gate oxide film by thermal oxidation.

In FIG. 1(b), a polysilicon film with a thickness of 4,000 layers was deposited as a conductive film for the gate electrode over the entire surface of the substrate using the CVD method.
The i-film is grown and patterned to form the gate electrode 8.

In FIG. 1C, a resist film 4 with a thickness of 1 μm is formed on the element region as an implantation mask, and B4 is implanted into the substrate.

B+ implantation conditions are energy 300 KeV, )
” - amount of leakage lXl013cm-2.

Activation annealing performed in the post-process (melt annealing of the PSG film described later) is performed at 900° C. for 10 minutes.

This level of heat treatment is milder than the heat treatment for forming a gate oxide film, and the lateral diffusion of boron can be ignored.

Element isolation is achieved by forming channel stopper regions 5 in which the implanted boron electrically isolates adjacent elements.

Next, using FIG. 2, as an application example of the present invention, a CMOS
An outline of a method for manufacturing a NAND type mask ROM (when the cell portion is an n-channel FET) using a process will be described below.

Particularly, steps that are not related to the present invention will only be mentioned and their explanation will be omitted, but they can be carried out by a well-known method.

■ Formation of n-type well As a p-channel FET formation region for peripheral circuits.

An n-type well is formed in the p-3i substrate 1.

■ Formation of field oxide film 6 (Fig. 2 (a)) ■ p
Channel dose of channel FET ■ n-channel FE
Channel dose of T part ■ Formation of gate oxide film 7 (Fig. 2 (a)) ■ Formation of polycide (Fig. 2 (a)) As conductive film 8 for gate electrode, pre-Si film is deposited on the entire surface of the substrate with 2,000 layers of tungsten. (W) The film is grown for 2000 man-months to form a polycide film.

(2) Polycide etching (FIG. 2(a)) A gate electrode is formed by patterning the polycide film using ordinary glue etching.

■Through oxide film formation A through oxide film for implantation is formed over the entire surface of the substrate.

Ion implantation is performed through this.

■ Source/drain formation Using the gate electrode as a mask, form an n-type impurity (arsenic) in the substrate.
A north drain region is formed by implanting ions of As) or phosphorus (p).

Source and drain are on both sides of the gate electrode (perpendicular to the paper)
It is not shown because it is formed in

[F] Formation of channel stopper region 5 (Fig. 2(a)
) Cover the element area with resist and apply B+ to the substrate in one isolation area.
inject.

The B+ implantation conditions are: energy of -300 KeV, and dose of I x 10' 3 crn-2.

(2) Formation of interlayer insulating film (FIG. 2(b)) A 6000-80 PSG (phosphosilicate glass) film is grown as one interlayer insulating film 9 by the CVD method.

(2) Planarization (FIG. 2(b)) Annealing is performed at 900'C for 10 minutes to melt the PSG film and planarize the substrate surface.

At this time, the implanted impurities are simultaneously activated.

0 Writing data to the memory cell section (Fig. 2(b)) (
Program injection) Inject As+ or P+ into the channel part of the FET to be written with an acceleration energy of 700 KeV or more to convert it into a depletion type FET.

In this case, since the channel stopper region 5 is heavily doped, the conductivity will not be reversed by programmed implantation.

[Co., Ltd.] Contact hole formation in interlayer insulating film A contact hole is formed on the source/drain region.

[Phase] An aluminum (AI) film is formed as a wiring film over the entire surface of the wiring formation substrate and patterned to form wiring.

[F] Cover insulation film formation A cover insulating film is applied over the entire surface of the substrate to cover the wiring.

FIGS. 3fa) to 3(C) are cross-sectional views illustrating a device isolation method according to another embodiment of the present invention.

In this example, the channel stopper region is formed by performing implantation twice, before and after the field oxide film is formed.

According to this method, the first implantation before the formation of the field oxide film is performed at a dose of lXl0''cm-2 or less (the dose at which the influence of lateral diffusion explained in the conventional example can be ignored).
This has the advantage that the implanted impurities are prevented from diffusing laterally when forming the field oxide film, and the second implantation after forming the field oxide film can be performed with lower energy than the embodiment shown in FIG.

In Figure 3(a), LOCO is placed on p-3i substrate I.
Underlying SiO□ film 2 by thermal oxidation in step 5 and S by CVD method
After depositing the i3N4 film 3, it is patterned using a normal glue pattern so that the 5iJ4 film 3 remains only on the element region.

Next, B+ is implanted into the substrate in the isolation region using the Si3N4 film 3 as an implantation mask.

B+ implantation conditions are energy 50KeV, dose <
IX 10"cm-2.

5' is an injection region.

Figure 3 fb) Nioite, LOC on p-3i board 1
A SiO □ film 6 with a thickness of 5000 wafers is formed as a field oxide film by thermal oxidation using the O3 method, and an SiO □ film 7 with a thickness of 200 ml as a gate oxide film is further formed by thermal oxidation.

Next, using the CVD method, a poly-Si film with a thickness of 4000 nm was grown on the entire surface of the substrate as a conductive film for the gate electrode.
A gate electrode 8 is formed by patterning.

Next, a resist film 4 having a thickness of 1 μm is formed on the element region as an implantation mask, and B+ is implanted into the substrate.

The B+ implantation conditions are: energy 125 KeV, dose > IX 1012 cm-2.

Reference numeral 5 indicates a channel stopper region formed by two implantations.

In FIG. 3(C), similar to FIG. 2(b), program injection for writing data into the memory cell portion is performed.

As+ or P+ is injected into the channel portion of the FET to be written at an acceleration energy of 700 KeV or more to convert it into a depletion type FET.

In this case, since the channel stopper region 5 is heavily doped, the conductivity will not be reversed by the program implantation.

In the embodiment, boron ions were used to form the channel stopper region, but boron difluoride ions (BF2a) may be used instead.

Further, although the embodiments have been described with respect to an n-channel FET, the effects of the present invention are equivalent to those of an n-channel FET.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to prevent the channel stopper region from spreading in the lateral direction, thereby suppressing device deterioration and miniaturizing the device, and increasing the implantation amount of the channel stopper region to isolate the device. A nonvolatile memory in which the conductivity of the channel stopper region is not reversed by program implantation can be obtained.

[Brief explanation of drawings]

FIGS. 1A to 1C are cross-sectional views illustrating an element isolation method according to an embodiment of the present invention. FIGS. 2(a) and 2(b) are sectional views explaining the present invention in detail. FIGS. 3A to 3C are cross-sectional views illustrating an element isolation method according to another embodiment of the present invention. FIGS. 4(a) to 4(d) are cross-sectional views illustrating a conventional device isolation method. In fig. l is a semiconductor substrate and is a p-3i substrate. 2 is the underlying SiO□ film for LOCO3. 3 is Si3N4 film for LOCO3. 4 is a resist film. 5 is a channel stopper area. 6 is a field oxide film, which is a SiO□ film. 7 is a gate oxide film, which is a SiO□ film. 8 is a conductive film for the gate electrode, which is a poly-Si film. or polycide membrane. 9 is an interlayer insulating film, which is a PSG film B+.No. ↓↓↓↓↓↓↓↓↓&No. / Example P side view Figure t・Use cross-sectional view Back viewOther examples 'Ur side view of

Claims (1)

[Claims] 1) A field oxide film is formed in an isolation region on a semiconductor substrate, a gate oxide film is formed on the substrate in an element region surrounded by the isolation region, and then the element is formed on the substrate. forming a gate electrode including a region, and introducing impurities of a conductivity type opposite to that of the substrate into the substrate on both sides of the gate electrode to form a source/drain region; A method of manufacturing a nonvolatile memory, comprising the step of implanting impurity ions of the same conductivity type as the substrate through the gate electrode and the field oxide film to form a channel stopper region. 2) A method for manufacturing a non-volatile memory, comprising the step of claim 1 and the step of implanting impurity ions of a conductivity type opposite to that of the substrate into the channel region of the cell FET to be written. 3) A nonvolatile method comprising the step of claim 2 and the step of implanting impurity ions of the same conductivity type as that of the substrate into the substrate in the isolation region before forming the field oxide film. Method of manufacturing sexual memory.