JP2000357747A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device which allows a proper and easy heat treatment to be given to two transistors, which have impurity regions of different impurity distribution characteristics to provide each of the transistors with desired proper characteristics. SOLUTION: In order to form a source and drain regions 24 in one of two kinds of transistors which needs a relatively deep impurity distribution, impurities 23 are implanted. For diffusion of the implanted impurities, a semiconductor substrate 10 is heat-treated. Thereafter, impurities 27 are implanted shallowly in the substrate to form a source and drain region 28 for the other transistor and the substrate 10 is heat-treated for diffusion of the impurities at a temperature lower than the one, when it was heat-treated for the former transistor.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer in which FETs having different characteristics, such as a field-effect transistor (FET) having a high withstand voltage and a field-effect transistor (FET) for high-speed operation, are mounted. The present invention relates to a semiconductor device manufacturing method suitable for manufacturing such a semiconductor device.

[0002]

2. Description of the Related Art Some microcomputers incorporated in various electric appliances incorporate a flash memory. In such a microcomputer, generally, a high-speed CMOS transistor including a p-MOS transistor and an n-MOS transistor suitable for high-speed operation is used as a transistor of a logic circuit that requires high-speed operation. Further, as a switching element for rewriting data to each memory cell of a flash memory incorporated in a microcomputer, for example, each has a source-drain breakdown voltage characteristic (BV
p-MOS transistor and n-MOS having sd)
High-breakdown-voltage CMOS transistors composed of transistors are used, and these are incorporated on the same substrate.

A high-speed FET such as the above-described high-speed MOS transistor and a high-voltage FET such as a high-voltage MOS transistor have partially different configurations due to the required characteristics of each transistor. In a high-speed MOS transistor, the gate length is set to be relatively short, and the distribution due to the diffusion of impurities in the source / drain regions is set to be relatively shallow. On the other hand, in the high breakdown voltage MOS transistor, the gate length is set longer than in the high-speed MOS transistor, and the distribution due to diffusion of impurities in the source / drain regions is set deeper than in the high-speed MOS transistor.

In the prior art of the semiconductor device in which MOS transistors having different characteristics are mounted, respective active regions are sectioned on a semiconductor substrate by using, for example, a LOCOS method. Each gate is formed via a gate oxide film. Each active area has
Using each gate as a mask, impurities for source / drain regions are implanted on both sides thereof by, for example, an ion implantation method. The impurities implanted in each active region undergo predetermined diffusion and are activated by heat treatment.

By the way, regarding the implantation of impurities, a high breakdown voltage M
In the OS transistor, as described above, the high-speed MOS
Since it is necessary to set the gate length longer than that of the transistor, implantation of impurities into the active region requires sidewall portions on both sides of the gate to be part of a mask. On the other hand, in a high-speed MOS transistor having a shorter gate length, a sidewall portion having a smaller thickness dimension is used as necessary.

Conventionally, regardless of whether or not a sidewall portion is required for the above-described impurity implantation for a high-speed MOS transistor, both high-speed and high-voltage MOS transistors are used.
At each gate for the transistor, a sidewall material is deposited collectively and directly, and a necessary sidewall portion is formed from this material. Also, for example, by etching the sidewall portion having a large thickness dimension,
Etching to reduce the thickness of the sidewalls or to remove unnecessary sidewalls may damage the gate oxide film under the sidewalls to be etched. There is.

For these reasons, conventionally, first, a side wall portion for a high-speed MOS transistor which does not require a side wall portion or requires a side wall portion having a relatively small thickness is used as a gate of both transistors. , A relatively shallow impurity is implanted into the active region of the high-speed MOS transistor, and heat treatment is performed at a relatively low temperature.

Thereafter, a sidewall material is deposited again on the side wall portion having a relatively small thickness formed on the gate for the high breakdown voltage MOS transistor to increase the thickness, and by a predetermined molding, A sidewall portion having a desired thickness dimension suitable for high pressure resistance is formed. By using the sidewall portion having the increased thickness dimension, an impurity for a high withstand voltage MOS transistor is implanted deeper than that of a high-speed MOS transistor, and then, for diffusion and activation of the impurity, The semiconductor substrate is subjected to a heat treatment.

Since the impurity of the high breakdown voltage MOS transistor requires a deeper impurity distribution than the heat treatment for the impurity of the high-speed MOS transistor previously implanted, a high-temperature and long-time heat treatment is required. receive.
By the way, when the impurity region of the high-speed MOS transistor which has been subjected to appropriate impurity implantation and heat treatment by the impurity heat treatment of the high-breakdown-voltage MOS transistor is further subjected to a high-temperature and long-time heat treatment, the impurity distribution of the impurity region becomes a desired one. There is a risk that the value will deviate significantly.

[0010]

Therefore, in the above-mentioned conventional manufacturing method, if the distribution of the impurity region of the high-speed MOS transistor is to be properly maintained, the high breakdown voltage MOS
The heat treatment of the impurity region for the transistor may not be sufficient. Conversely, if this heat treatment is sufficiently performed so that the heat treatment of the impurity region for the high-breakdown-voltage MOS transistor is properly performed, the impurity distribution of the high-speed MOS transistor greatly deviates from a desired value, There is a possibility that desired performance cannot be obtained. For this reason, in the above-described conventional manufacturing method, it is not easy to perform heat treatment for giving desired appropriate characteristics to both transistors having different impurity distribution characteristics of the impurity regions.

[0011]

The present invention adopts the following constitution in order to solve the above points. <Structure> The present invention relates to two types of field-effect transistors formed corresponding to respective active regions of a semiconductor substrate, and different impurity distributions for source / drain regions depending on the types. In a method of manufacturing a semiconductor device having a field-effect transistor,
One of the two types of field-effect transistors, the gate formed on a gate oxide film on the active region for one of the transistors requiring a relatively deep impurity distribution, at least as a part of the mask, Impurities are implanted to form the source / drain regions, and a heat treatment for diffusing the impurities is performed on the semiconductor substrate. After this heat treatment, a heat treatment is performed on the gate oxide film on the active region for the other transistor. In order to form the source / drain region of the other transistor by using the gate to be formed as at least a part of the mask, the impurity is implanted shallower than in the impurity implantation of the one transistor, and the one of the two Heat treatment is performed on the semiconductor substrate at a lower temperature than in the heat treatment of the transistor.

According to the manufacturing method of the present invention, the impurity for the one transistor requiring a higher heat treatment is implanted and subjected to the heat treatment. Thereafter, an impurity for the other transistor requiring a lower heat treatment is implanted and subjected to a heat treatment. Therefore, the implantation of the impurity for the other transistor that is subjected to the heat treatment at a low temperature is performed after the formation of the impurity region for the one transistor that requires the high heat treatment. The impurities for the other transistor that are received are not subjected to the heat treatment of the impurities of the one transistor that require high-temperature treatment.

Therefore, according to the present invention, appropriate heat treatment can be easily performed on each of the two transistors having different impurity region distribution characteristics so as to provide desired appropriate characteristics to each transistor. The characteristics of each of the high-voltage transistor and the high-voltage transistor can be improved.

More specifically, the present invention relates to two types of field-effect transistors formed corresponding to respective active regions of a semiconductor substrate, and the source-drain regions corresponding to the types. Forming a gate for the transistor on a gate oxide film formed on each of the active regions of the semiconductor substrate. Forming an etching stopper film covering the gate and the gate oxide film; and, in relation to the gates for the two transistors, a deeper impurity distribution and a longer gate length of the two types of transistors. A sidewall portion having a thickness suitable for one of the required transistors is formed on the etching stopper film. Implanting an impurity for source / drain into the activation region for the one transistor, using the sidewall portion as an etching mask, and diffusing the impurity into the semiconductor substrate for diffusion of the impurity. Performing a heat treatment, and after the heat treatment, removing at least a sidewall portion provided in connection with the other gate while the gate oxide film under the gate is protected by the etching stopper film by an etching process. Injecting an impurity into the active region of the other transistor from which the sidewall portion has been removed, so as to be shallower than in the impurity implantation for the one transistor, and to diffuse the impurity more than in the one transistor. Subjecting the semiconductor substrate to a heat treatment at a low temperature.

According to the method of the present invention, a sidewall portion having a thickness dimension suitable for the one transistor requiring a deeper impurity distribution and a long gate length is used to form an impurity for the one transistor. After injecting impurities into the region and performing heat treatment, the sidewall portion of the gate in the other transistor is removed. At this time, since the gate oxide film below the gate is protected by the etching stopper film, unnecessary sidewall portions formed on the other gate are removed without damaging the gate oxide film. can do. Therefore, after formation of the impurity region of the one transistor which requires heat treatment at a higher temperature, a sidewall portion can be formed at the gate of the other transistor as necessary, and formation of the sidewall portion can be performed. Thereafter, an impurity for the other transistor is implanted, and heat treatment can be performed on the impurity. Therefore, in order to give desired appropriate characteristics to each of the two transistors having different impurity region distribution characteristics, appropriate Heat treatment can be easily performed.

According to the present invention, there are provided two types of field-effect transistors formed respectively corresponding to the active regions of the semiconductor substrate, and the impurity distributions for the source / drain regions are mutually changed according to the types. In a method of manufacturing a semiconductor device including different field-effect transistors, a gate layer for a gate of the transistor is formed on a gate oxide film formed on the active region of the semiconductor substrate; By performing selective etching treatment on a part of the layer, of the two types of transistors,
Forming a gate for one of the transistors requiring a deep impurity distribution and a long gate length, and forming a sidewall portion which becomes a part of a mask at the time of impurity implantation in relation to the gate for the transistor; That is, an impurity for source / drain is implanted into the activation region for the one transistor using the sidewall portion as a mask, and a heat treatment is performed on the semiconductor substrate to diffuse the impurity. Performing a selective etching process on the remaining portion of the gate layer to form a gate for the other transistor, and implanting impurities for the one transistor into the activation region for the other transistor. The impurity for the source / drain is implanted shallower than in Comprises applying a heat treatment to said semiconductor substrate at a lower temperature than in the heat treatment of the register.

According to the method of the present invention, selective etching is performed on a part of the gate layer formed in the active region, so that a deeper impurity distribution and a longer gate length are required for one of the transistors. Are formed, and impurities for the source / drain are implanted using the sidewall portion formed in association with the gate as a part of the mask, and heat treatment is performed on the semiconductor substrate to diffuse the impurities. Will be applied. Thereby, an impurity region for the one transistor is formed. Thereafter, by selectively etching the remaining portion of the gate layer, a gate for the other transistor is formed, and a sidewall portion is formed on the gate as necessary. An impurity for a source and a drain is implanted into the activation region at a lower temperature than in the impurity implantation for the one transistor, and the semiconductor is formed at a lower temperature than in the heat treatment of the one transistor due to diffusion of the impurity. Heat treatment is applied to the substrate.

Therefore, after forming the impurity region of the one transistor which requires a heat treatment at a higher temperature, a sidewall portion can be formed at the gate of the other transistor if necessary. After the formation of the portion, the impurity for the other transistor is implanted, and heat treatment can be performed on the impurity, so that the distribution characteristics of the impurity region are given to each of the two transistors different from each other to provide desired appropriate characteristics. Appropriate heat treatment can be easily performed for each.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the illustrated embodiments. <Embodiment 1> FIGS. 1 and 2 show a method of manufacturing a semiconductor device according to the present invention. The present invention provides, for example, p-
A logic circuit composed of a high-speed CMOS transistor composed of a MOS transistor and an n-MOS transistor; and a high-voltage CMOS transistor composed of a high-voltage p-MOS transistor and an n-MOS transistor used as a switching element of a memory cell of a flash memory. In a single semiconductor substrate.

In the illustrated example, a p-type silicon substrate, for example, is used as the semiconductor substrate 10, and on the substrate,
P-MOS of each CMOS transistor
Description will be made along an example of forming a transistor. In the example shown in FIG. 1A, an n-type well portion 11a, which is well known in the art, is formed in the semiconductor substrate 10 by partial implantation of impurities imparting conductivity opposite to that of the substrate and heat treatment (for example, at 1150 ° C.). And 11b are formed. Each well part 1
1a and 11b are, for example, the conventionally well-known LOCO
The field oxide films 12 formed by the S method are separated from each other, thereby forming one of the well portions 11a.
Is an active region 1 for a high voltage MOS transistor.
3a, and the upper surface of the other well portion 11b is
It is used as an active region 13b for a high-speed MOS transistor. On both active regions 13a and 13b, oxide film 14 having a thickness of, for example, 150 to 200 ° is formed by heat treatment.

Thereafter, the oxide film 14 formed on the active region 13b of the other well portion 11b is removed by using, for example, well-known photolithography and etching techniques. On the active region 13b from which the oxide film 14 has been removed,
On the remaining oxide film 14 on the active region 13a of the one well portion 11a, a gate oxide film 15b having a thickness of, for example, 60 to 100 ° is further heat-treated at a temperature of 850 ° C. lower than that of the oxide film 14, for example. Is formed by

As a result, as shown in FIG. 1B, on one active region 13a for the high breakdown voltage MOS transistor, the thickness formed by the oxide film 14 and the gate oxide film 15b is formed. As a result, a gate oxide film 15a having a large size is formed. On the other hand, the gate oxide film 1a is formed on the other active region 13b for the high-speed MOS transistor.
Gate oxide film 1 having a thickness smaller than the thickness of 5b
5b will be formed.

Through these gate oxide films 15a and 15b, predetermined active regions 13a and 13b are doped with a predetermined threshold adjusting impurity by using well-known photolithography and ion implantation techniques as necessary, though not shown. Can be injected.

Thereafter, as shown in FIG. 1C, for example, a polysilicon film doped with phosphorus is formed on the entire upper surface of the semiconductor substrate 10 including the gate oxide films 15a and 15b and the field oxide film 12. A lamination 16 is formed, which comprises 16a and a tungsten silicide film 16b on the polysilicon film. The polysilicon film 16a can be formed by, for example, a well-known low-pressure chemical vapor deposition (LP-CV) method.
By using D), for example, it is formed to a thickness dimension of 1500 °. The tungsten silicide film 16b is formed to a thickness of, for example, 1000 ° by using a sputter deposition method.

Unnecessary portions of the laminate 16 are removed by the same photolithography and etching techniques as described above. Thus, as shown in FIG. 1D, a gate 17a for a high-voltage MOS transistor is formed on one gate oxide film 15a, and a high-speed gate is formed on the other gate oxide film 15b. A gate 17b for a MOS transistor is formed.

As is well known, the lower portion of each of the gates 17a and 17b made of the polysilicon film 16a relaxes distortion caused by lattice mismatch between the gate oxide films 15a and 15b and the tungsten silicide film 16b. The tungsten silicide film 16b is a conductive layer that functions as a pad for performing the above operation, and lowers the resistance of the gate. Each gate 17a and 17b can adopt a single-layer structure.

In the example shown in FIG. 1E, the gates 17a and 17b of the wells 11a and 11b are formed by using the same photolithography and ion implantation techniques as described above.
b, LDD (Lightly-Doped Drain) layers 18 on both sides
Are formed. As is well known in the art, the LDD layer 18 is used to suppress the generation of hot electrons that adversely affect the characteristics of the device, in order to suppress the later-described source / drain edges near the upper surfaces of the active regions 13a and 13b. In order to alleviate the electric field, impurities are implanted into the well portions 11a and 11b at a density lower than the impurity density in a region wider than the source / drain regions, and heat treatment is performed as necessary. LDD layer 18
However, as described above, it is desirable to provide the LDD layer 18 in order to prevent deterioration of device characteristics due to generation of hot electrons.

After the formation of gates 17a and 17b, FIG.
As shown in (f), an etching stopper film 19 is formed on the entire upper surface of the semiconductor substrate 10 so as to cover the gates 17a and 17b and the gate oxide films 15a and 15b. The etching stopper film 19 is, for example, 10
Low pressure TEOS (LP-TE) having a thickness of 0 to 200 mm
OS) It can be formed of a film. As is well known, the low-pressure TEOS film has a small etching selectivity with respect to a predetermined etching gas with respect to a material of a sidewall portion described later.

Instead of the TEOS film, a nitride film having a small etching selectivity with respect to the sidewall portion can be used as the etching stopper film 19. The thickness of the etching stopper film 19 may be adjusted as required.
For example, it can be set to 700 to 1200 °. Also,
After forming the etching stopper film 19, if necessary,
A heat treatment (for example, at 800 to 850 ° C.) for activating and diffusing impurities in the D layer 18 can be performed on the semiconductor substrate 10.

After forming the etching stopper film 19, FIG.
(G), the etching stopper film 1
Sidewall portions 20a and 20b are formed on portions corresponding to the side portions of gates 17a and 17b on line 9. The sidewall portions 20a and 20b can be formed of, for example, polysilicon having a large etching selectivity with respect to the etching stopper film 19. The sidewall portions 20a and 20 made of this polysilicon
b is, for example, 2000 on the etching stopper film 19.
After uniformly growing a polysilicon film having a thickness of about 3,000 mm, unnecessary portions are removed by using a conventionally well-known dry etching technique showing anisotropy.
Can be formed.

The thickness t of each of the sidewall portions 20a and 20b, that is, the thickness t of the gate 17a along the gate length direction is determined by the thickness t and the etching stopper film 19 covering the side of the gate 17a. Is set to a value necessary for defining an appropriate gate length of the high breakdown voltage MOS transistor.

When sidewall portions 20a and 20b optimum for a high breakdown voltage MOS transistor are formed in association with gates 17a and 17b, the upper surface of semiconductor substrate 10 including sidewall portions 20a and 20b becomes
The entire surface is covered with a resist 21 (see FIG. 2H). Then, using photolithography and etching techniques,
As shown in (h), only one active region 13 a for the high breakdown voltage MOS transistor is opened by the opening 22.

The active region 13a for the high voltage MOS transistor which is exposed to the opening 22, for example BF ₂ ions 23 for forming the source and drain regions are irradiated. At this time, since the gate 17a and the side wall portion 20a formed on the side of the gate 17a act as a mask, a relatively long gate length (channel length) is correspondingly increased as conventionally known. Impurities 24 for defining the source and drain are implanted into active region 13a. At this time, the bottom portion 19b of the etching stopper film 19 covering the gate oxide film 15a functions to protect the gate oxide film 15a from ion implantation.

The ion implantation into active region 13a for the high breakdown voltage MOS transistor is performed relatively deeply, and after implantation, semiconductor substrate 10 is subjected to a heat treatment at a relatively high temperature for a long time. By this heat treatment, the impurities implanted in active region 13a are appropriately diffused and activated. By the diffusion and activation of the impurity, a source / drain region (24) for a high breakdown voltage MOS transistor is formed in the active region 13a.

Under the above-described high-temperature heat treatment for forming the source / drain regions (24), high-concentration impurities for the source / drain are implanted into the active region 13b for the high-speed MOS transistor. And LDD
Since the concentration of the layer 18 is lower than that of the source / drain impurities, the impurity distribution of the active region 13b is not substantially changed by the high-temperature heat treatment described above. Therefore, the conditions of the heat treatment for forming the above-described source and drain of the high breakdown voltage MOS transistor can be selected so as to be optimal for the high breakdown voltage MOS transistor.

After the formation of the source / drain regions (24) of the high breakdown voltage MOS transistor, the resist 21 is removed as shown in FIG.
Wall portion 2 formed in connection with and 17b
Oa and 20b are removed. For removing the sidewall portions 20a and 20b, for example, dry etching can be used, and an etching gas showing a sufficiently large selection ratio of the sidewall portions 20a and 20b to the etching stopper film 19 can be appropriately used. it can.

After the removal of the sidewall portions 20a and 20b, the upper surface of the semiconductor substrate 10 including the etching stopper film 19 covering the gates 17a and 17b is entirely covered with a resist 25 (see FIG. 2 (j)). . Then, only the other active region 13b for the high-speed MOS transistor is opened by the opening 26 by the photolithography and the etching technique, as shown in FIG.

The active region 13b for the high-speed MOS transistor that is exposed to the opening 26, for example BF ₂ ions 27 for forming the source and drain regions are irradiated. At this time, the side portion 19c of the etching stopper film 19 on the active region 13b remaining on the side of the gate 17b functions as a sidewall portion having a small thickness because it functions as a mask for ion implantation. . Therefore, by the above-described ion implantation, the impurity 28 for the source / drain defining a relatively short gate length (channel length) is implanted into the active region 13b. In addition, the bottom portion 19d of the etching stopper film 19 remaining on the gate oxide film 15b on the active region 13b functions to protect the gate oxide film 15a from ion implantation, as in the above-described high breakdown voltage MOS transistor.

The ion implantation into the active region 13b for the high-speed MOS transistor is performed shallower than the ion implantation into the active region 13a for the high breakdown voltage MOS transistor. On the other hand, it receives a heat treatment at a lower temperature and for a shorter time. By this heat treatment, the impurities implanted in active region 13b are appropriately diffused and activated. As a result of the diffusion and activation of the impurity, a source / drain region (28) for a high-speed MOS transistor is formed in the active region 13b.

After the formation of the source / drain regions of both MOS transistors and the removal of the resist 25, FIG.
As shown in (k), each transistor is covered with a conventionally well-known insulating film layer 29, and is connected to each source / drain region via a connection portion 30 through a contact hole formed in the insulating film layer. (24, 28) are connected to the wiring part 31.

According to the method of the present invention, as described above, the source
When the impurity 24 implanted into the active region 13a of the high-breakdown-voltage MOS transistor is subjected to a high-temperature heat treatment to form a drain region, the active region 13b of the high-speed MOS transistor has a source / drain which is easily affected by the high-temperature heat treatment. The impurity 18 for the region has not been implanted.

In connection with the gate 17a for the high-speed MOS transistor, a large sidewall portion 20b having a thickness similar to that of the sidewall portion 20a of the high breakdown voltage MOS transistor is temporarily formed. Unnecessary sidewall portions 20b are removed by, for example, dry etching. In addition, in the unnecessary sidewall portion 20b removing step, the gate oxide film 15b under the etching stopper film 19 is surely protected by the etching stopper film 19, so that the gate oxide film 15b becomes unnecessary as described above. Side wall part 2
There is no damage in the step of removing Ob. Thus, after the formation of the source / drain region (24) of the high breakdown voltage MOS transistor, the source / drain region (28) is properly formed in a state where damage to the gate oxide film 15b of the high-speed MOS transistor is reliably prevented. Can be formed.

Therefore, according to the present invention, the source / drain regions (24 and 28) of the high breakdown voltage MOS transistor and the high speed MOS transistor can be formed without causing damage to the gate oxide film. ,
Optimal heat treatment can be applied to each, and high withstand voltage MO
Optimum characteristics can be given to each of the S transistor and the high-speed MOS transistor.

The high-speed MOS described with reference to FIG.
When ions 27 are implanted into the active region 13b for forming the source / drain of the transistor, the side portion 1 remaining on the side of the gate 17b of the etching stopper film 19
It has been described that 9c functions as a side wall portion that functions as a mask. Therefore, when the side wall portion is not necessary for ion implantation for forming the source / drain of the high-speed MOS transistor, it is desirable to make the side portion 19c sufficiently thin.

On the contrary, when the side portion 19c remaining on the side of the gate 17b of the etching stopper film 19 is positively used as a side wall portion serving as a mask, as described above, the etching stopper Membrane 19
May be, for example, 700 to 1200 °. This etching stopper film 19 having a large thickness dimension
By performing, for example, an anisotropic dry etching process, the bottom portion 19d of the etching stopper film 19 can be thinned, and the side portion 19c can be left as a sidewall portion having an appropriate thickness. A desired thickness dimension can be given to the side portion 19c by adjusting the etching process time and the like.

After the formation of the sidewall portion by the side portion 19c, ions 27 are implanted into the active region 13b for forming the source / drain of the high-speed MOS transistor. At the time of this ion implantation, an etching stopper film is formed. If the thickness of the bottom portion 19d of 19 is large, high implantation energy is required for ion implantation,
Also, it is not easy to obtain an appropriate impurity distribution.

Therefore, in the manufacture of a high-speed MOS transistor requiring a relatively shallow impurity distribution in the source and the drain, in particular, in order to obtain a good impurity distribution with a relatively low implantation energy, the etching stopper film 19 is required.
It is desirable to make the thickness dimension of the bottom portion 19d as small as possible. Further, reduction in implantation energy in ion implantation is advantageous in suppressing variations in transistor characteristics such as threshold, source / drain current, and short channel effect.

In the case of a high-speed MOS transistor, when the bottom portion 19d of the etching stopper film 19 is reduced in thickness by the anisotropic etching process, the portion of the etching stopper film 19 on the gate 17b is easily removed at the same time. When this portion is removed by the etching process, the underlying tungsten silicide film 16b, which is the upper layer portion of the gate, is subjected to the etching process. This thinning of the tungsten silicide film 16b causes an increase in gate resistance. Therefore, in order to prevent the resistance of the gate from increasing, it is desirable to provide a sacrificial film layer on the gates 17a and 17b.

FIGS. 3A to 3F show the state of the gate 17a.
17 and 17b show a modified example in which a sacrificial layer is provided. FIG.
As shown in FIG. 1A, the semiconductor substrate 10 has the structure shown in FIG.
As in the case shown in FIG.
And gate oxide films 15a and 15b are formed on active regions 13a and 13b formed on field oxide film 12 and formed on field oxide film 12, respectively. Further, a gate oxide film 15a is
And 15b and on the entire surface of the semiconductor substrate 10 including the field oxide film 12, a polysilicon film 16a, a tungsten silicide film 16b on the polysilicon film, and a non-metallic material such as polysilicon or nitrogen oxide film. The laminate 16 having the sacrificial film 16c made of is formed. The sacrificial film 16c is formed by, for example, CVD method.
It can be as thick as 00 mm.

As shown in FIG. 3 (b), each gate 1 is formed from the laminate 16 having the sacrificial film 16c by the same photolithography and etching technique as described above.
After the formation of 7a and 17b, an etching stopper film 19 is formed to cover them. Further, the same LDD layer 18 as described above is formed in each of the well portions 11a and 11b in association with each of the gates 17a and 17b.

On the etching stopper film 19, a polysilicon film for the sidewall of the high voltage MOS transistor is formed, and unnecessary portions are removed from the sidewall portion, as shown in FIG. In addition, in connection with each of the gates 17a and 17b, the sidewall portion 2
0a and 20b are formed.

After the formation of the sidewall portions 20a and 20b, as shown in FIG. 3D, only one active region 13a for the high breakdown voltage MOS transistor is selectively formed by the resist 21 having the opening 22. The active region 13 which is opened and uses the side wall portion 20a as a part of the mask
The implantation of the ions 23 into the well 11a and the subsequent heat treatment described above allow the source / drain region (2
4) is formed.

Thereafter, as shown in FIG. 3E, a high-speed MO is formed by a resist 25 having an opening 26.
Only the other active region 13b for the S transistor is selectively opened, and the sidewall portion 20b provided on the other gate 17b is removed. By the subsequent etching process, the etching stopper film 19 is subjected to the etching process so that the side portion 19c and the bottom portion 19d become appropriate. By this etching process, the gate 1
7b, the top surface of the sacrificial film 16c
Is etched to protect the tungsten silicide film 16b as a lower layer from the etching process. Therefore, the etching stopper film 19 described above is used.
The side silicide film 1 of the gate 17b is formed by forming the side portion 19c and thinning the side portion 19c.
The thickness of 6b is not reduced, and it is possible to reliably prevent the gate 17b from having a high resistance due to the thinning of the tungsten silicide film 16b.

Therefore, as shown in FIG. 3 (f), the source / drain region (28) for the high-speed MOS transistor is formed by the subsequent implantation of the ion 27 into the active region 13b and the heat treatment, as described above. It can be suitably formed.

The steps described with reference to FIGS. 3A to 3F are basically performed by the gates 17a and 17b.
Except that the stack 16 for has a sacrificial film 16c.
This is the same as in the first specific example described with reference to FIGS. 1 (a) to 1 (k).

As described above, the etching stopper film 19 is formed in order to remove the sidewall portion 20b which is formed in connection with the high-speed MOS transistor and is not necessary for the high-speed MOS transistor and which is suitable for the high breakdown voltage MOS transistor. Has been described, an example in which the etching stopper film is not required will be described below.

<Specific Example 2> As shown in FIG. 4A, the semiconductor substrate 10 is formed on the well portions 11a and 11b of the semiconductor substrate 10 in the same manner as shown in FIG. 1C. Then, gate oxide films 15a and 15b are formed to cover active regions 13a and 13b each defined by field oxide film 12.

Thereafter, a gate layer 16 made of, for example, a polysilicon film 16a and a tungsten silicide film 16b is formed on the entire upper surface of the semiconductor substrate 10 including the gate oxide films 15a and 15b and the field oxide film 12 so as to cover them. , In the same manner as described above.

After the formation of the stack 16, as shown in FIG. 3B, the portion of the stack 16 covering the other active region 13b for the high-speed MOS transistor is left using, for example, photolithography and etching techniques. In addition, a gate 17a for a high withstand voltage MOS transistor is formed in one active region 13a by a part of the stack.

After the gate 17a is formed, an LDD layer 18 similar to that in the above-described example is formed in one of the active regions 13a as necessary by ion implantation using the gate as a mask. After the formation of the LDD layer 18, for example, 200
After an ozone TEOS film having a thickness of 0 to 3000 ° is uniformly formed on the surface of the semiconductor substrate 10, the gate 17 is subjected to, for example, anisotropic dry etching.
Sidewall portions 20a are respectively formed on the side portions of "a". When this sidewall portion 20a is formed, a similar residual portion 20b remains at the opening edge of the active region 13a. However, since the gate 17b is not yet formed in the active region 13b for the high-speed MOS transistor, MO for high speed
The sidewall portion 20b as described above is not formed on the gate of the S transistor.

As shown in FIG. 4C, the resist 21 for selectively opening one of the active regions 13a on which the sidewall portions 20a are formed is removed.
The active region 13a is irradiated with ions 23 through the opening 22 of the resist.
Upon irradiation with the ions 23, the gate 17a and its side wall portion 20a function as a mask. After the irradiation of the ions 23, a relatively high-temperature heat treatment is applied to the semiconductor substrate 10 to diffuse and activate the impurities 24. The other active region 13b for the high-speed MOS transistor has its source Since the impurity (28) for the drain region is not introduced, the characteristics of the high-speed MOS transistor are not affected by the heat treatment for the impurity 24.

Therefore, as in the first embodiment, the impurity 24 for the high-breakdown-voltage MOS transistor is properly introduced into the well portion 11a by ion implantation, and the high-temperature heat treatment is performed in the same manner as described above. Source / drain regions (24) for MOS transistors can be formed properly.

After the formation of the source / drain regions (24) for the high breakdown voltage MOS transistor, as shown in FIG. A gate 17b is formed in the other active region 13b for the high-speed MOS transistor by the same photolithographic etching technique as that described above. After the formation of the gate 17b, an LDD layer 18 similar to that described above is formed as necessary in this connection.

After the formation of both gates 17a and 17b, a low-voltage TEOS film 19, for example, 700 to 12 is formed so as to cover the gate and gate oxide films 15a and 15b.
It is formed with a thickness of 00 °. After the formation of the TEOS film 19, a resist 25 for selectively opening the other active region 13b for the high-speed MOS transistor is formed, and the other active region 13b is irradiated with ions 27 through the opening 26 of the resist. Is done. Upon irradiation with the ions 27, the gate 17b and the side portion 19c of the low-pressure TEOS film 19 along the side portion of the gate act as a part of a mask having a smaller thickness dimension than the side wall portion 20a. Therefore, the well portion 1 having the side portion 19c as a side wall portion
1b, and a heat treatment at a lower temperature than the heat treatment of impurities by the
Source / drain regions (28) suitable for the transistor are formed.

In order to obtain a desired thickness in the side portion 19c used as a side wall portion for forming the source / drain of the high-speed MOS transistor, the thickness of the low-voltage TEOS film 19 is set to a thickness of, for example, 1000 to 2000 mm. Can be dimensions.

The low pressure TEOS film 19 having a large thickness
Prior to the irradiation of the ions 27 shown in FIG.
By performing proper anisotropic dry etching,
A side portion 19c having an appropriate thickness dimension, that is, a side wall portion 19c can be obtained. At this time, as in the first embodiment, the source / source of the other active region 13b is
In order to obtain an appropriate impurity distribution in the drain, the bottom portion 19d
It is desirable to sufficiently reduce the thickness dimension of. Also,
In order to prevent the resistance of the gate 17b from increasing due to the reduction of the bottom portion 19d, a sacrifice layer similar to that in the first embodiment can be provided in the stack 16 for the gates 17a and 17b.

As a material for the sidewall portion 19c, various materials can be appropriately selected in place of the low-pressure TEOS film. Further, in the above, examples of the high-voltage MOS transistor and the high-speed MOS transistor have been described as the field-effect transistors, but the present invention can be applied to other field-effect transistors.

[0068]

According to the present invention, as described above, impurities for one transistor requiring higher heat treatment are implanted, and after the heat treatment, the other transistor requiring lower heat treatment is implanted. Is implanted and subjected to heat treatment, so that the impurity for the other transistor subjected to the heat treatment at a low temperature is subjected to the heat treatment of the impurity of the one transistor requiring the high temperature treatment. There is no.

Therefore, according to the present invention, appropriate heat treatment can be easily performed on each of the two transistors having different impurity region distribution characteristics so as to provide desired appropriate characteristics. Since the characteristics of both the high-voltage transistor and the high breakdown voltage transistor can be improved, good characteristics can be given to each transistor even in a semiconductor device in which transistors having different characteristics are mounted.

[Brief description of the drawings]

FIG. 1 is a manufacturing process diagram (part 1) showing a specific example 1 of the manufacturing method according to the present invention.

FIG. 2 is a manufacturing process diagram (part 2) showing a specific example 1 of the manufacturing method according to the present invention.

FIG. 3 is a manufacturing process diagram showing a modification of the specific example 1 of the manufacturing method according to the present invention.

FIG. 4 is a manufacturing process diagram showing a specific example 2 of the manufacturing method according to the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Semiconductor substrate 11a, 11b Well part 12 Field oxide film 13a, 13b Active region 15a, 15b Gate oxide film 16 Gate layer 16c Sacrificial (film) layer 17a, 17b Gate 19 (Low-voltage TEOS film) Etching stopper film 19c, 20a Side wall Parts 24, 28 (source / drain region) impurities

Claims (7)

[Claims] 1. Two types of field-effect transistors formed respectively corresponding to respective active regions of a semiconductor substrate, wherein impurity distributions for source / drain regions are different according to the types. A method for manufacturing a semiconductor device including a field-effect transistor, comprising: forming a gate oxide film on the active region of the semiconductor substrate; deeper than the other one of the two types of transistors. In order to form a source / drain region of the one transistor, using a gate formed on the gate oxide film on the active region for the one transistor requiring the impurity distribution as at least a part of a mask, Implanting an impurity and subjecting the semiconductor substrate to a heat treatment for diffusing the impurity, after the heat treatment, The gate formed on the gate oxide film on the active region for the transistor is used as at least a part of a mask to form a source / drain region of the other transistor. A method of manufacturing a semiconductor device, comprising: implanting an impurity at a shallow depth; and performing a heat treatment on the semiconductor substrate at a lower temperature than in the heat treatment of the one transistor for diffusion of the impurity. 2. The high withstand voltage MO having a relatively deep impurity distribution and a relatively long gate length.
2. The method according to claim 1, wherein the transistor is an S transistor, and the other transistor is a high-speed MOS transistor having a shallower impurity distribution and a shorter gate length than a high-voltage MOS transistor. 3. Two types of field-effect transistors formed corresponding to respective active regions of a semiconductor substrate, wherein impurity distributions for source / drain regions are different from each other according to the types. A method of manufacturing a semiconductor device including a field-effect transistor, comprising: forming a gate for the transistor on a gate oxide film formed on each of the active regions of the semiconductor substrate; Forming an etching stopper film covering the gate oxide film; in relation to the gates for the two transistors, one of the two types of transistors requiring a deeper impurity distribution and a longer gate length Forming a sidewall portion having a thickness dimension suitable for the etching stopper film on the etching stopper film; In the active region for the register, the side wall portion as part of the etching mask,
Implanting impurities for source / drain, and subjecting the semiconductor substrate to a heat treatment for diffusing the impurities; after the heat treatment, the gate oxide film under the gate is protected by the etching stopper film by etching. Removing at least the sidewall portion provided in connection with the other gate, in the impurity implantation for the one transistor into the active region of the other transistor from which the sidewall portion has been removed. A method of manufacturing a semiconductor device, comprising: implanting an impurity at a shallower depth; and performing a heat treatment on the semiconductor substrate at a lower temperature than in the one transistor for diffusion of the impurity. 4. A side portion of the etching stopper film remaining on a side portion of the gate after removing the sidewall portion of the gate in the other transistor, as a part of a mask in impurity implantation of the other transistor. The method according to claim 3, wherein the method is used. 5. The method according to claim 5, wherein the gate is formed on a top portion between the gate and the etching stopper film after the upper portion of the stopper film is removed when the sidewall portion on the etching stopper film is removed. 4. The manufacturing method according to claim 3, further comprising a sacrificial film for protecting the top. 6. An electric field having two types of field-effect transistors formed respectively corresponding to active regions of a semiconductor substrate and having different impurity distributions for source / drain regions according to the types. A method of manufacturing a semiconductor device including an effect transistor, comprising: forming a gate layer for a gate of the transistor on a gate oxide film formed on the active region of the semiconductor substrate; By performing selective etching on part of the two types of transistors, a gate for one of the two transistors requiring a deep impurity distribution and a long gate length is formed, and the gate for the transistor is formed. Relatedly, forming a sidewall portion to be a part of a mask at the time of impurity implantation, and forming the sidewall portion for the one transistor. Implanting impurities for source / drain into the active region using the sidewall portion as a part of a mask, and subjecting the semiconductor substrate to heat treatment for diffusion of the impurities; selecting the remaining portion of the gate layer By performing an etching process, a gate for the other transistor is formed, and the activation region for the other transistor is shallower for the source / drain than in the impurity implantation for the one transistor. A method of manufacturing a semiconductor device, comprising: implanting an impurity; and performing heat treatment on the semiconductor substrate at a lower temperature than in the heat treatment of the one transistor for diffusion of the impurity. 7. The activated region for the other transistor has a sidewall portion having a smaller thickness dimension than a sidewall portion of the one transistor in relation to the gate after the gate is formed. 7. The method according to claim 6, wherein the impurity is implanted using the sidewall portion as a part of the mask.